diff --git a/README.md b/README.md
index c3e0e7b..b2d9937 100644
--- a/README.md
+++ b/README.md
@@ -120,6 +120,10 @@ hardware floating point, which is not supported by nutshell. RVV related workloa
 require the vector ISA extension, and hypervisor related workloads require the
 hypervisor ISA extension.
 
+NutShell uses the RV64IMAC/LP64 software stack. See the
+[SPEC2006 configuration](workloads/linux/spec2006/README.md#configuration)
+section for `riscv_gcc16_rv64imac_lp64.cfg`.
+
 ## Build Requirements
 
 Any modern Linux distributions should be okay. The build system of this project is using the toolchain provided by buildroot, so you do not have to set up the toolchains manually to build most workloads. Some workloads require additional toolchians not provided by buildroot. Please refer to the README file of each workload (`README.md` in the workload directory) for details.
diff --git a/dts/README.md b/dts/README.md
index a475243..9e79e1c 100644
--- a/dts/README.md
+++ b/dts/README.md
@@ -41,6 +41,19 @@ profiles, FPGA noAIA names, and QEMU `nemu` names of the form
 custom template passed through `--custom-template-dir`; otherwise generation
 fails with an `unsupported DTS basename` error.
 
+`nutshell` is the 128 MiB machine description used by NEMU's
+`riscv64-nutshell_defconfig`: uartlite at `0x40600000`, no PLIC.
+NutShell simulation uses the same map. `nutshell-mem2g` keeps that
+MMIO and enlarges DRAM to 2 GiB. `nutshell-fpga` describes NutShell
+FPGA: UART16550 @ `0x310b0000`, PLIC @ `0x3c000000`, 2 GiB.
+
+All three names emit `riscv,isa = "rv64imac_zicsr_zifencei"` to match
+`riscv,isa-extensions`. NutShell implements Zicsr and Zifencei; it
+does not implement Zicntr or Zihpm.
+
+Pass them as `DEFAULT_DTB=nutshell`, `DEFAULT_DTB=nutshell-mem2g`, or
+`DEFAULT_DTB=nutshell-fpga`.
+
 For generated FPGA noAIA and QEMU `nemu` names, select the ISA declaration
 independently of the basename:
 
diff --git a/dts/generate-nemu-board-dts.py b/dts/generate-nemu-board-dts.py
index 5f93fd1..799bfc6 100644
--- a/dts/generate-nemu-board-dts.py
+++ b/dts/generate-nemu-board-dts.py
@@ -14,6 +14,10 @@
 NEMU_BOARD_DTSGEN = ROOT / "dts" / "DTSGen.py"
 PROFILE_FILE = ROOT / "dts" / "workload-builder-profiles.json"
 DRAM_BASE = 0x80000000
+# Shared by nutshell / nutshell-mem2g / nutshell-fpga. Omit Zicntr/Zihpm:
+# U-mode cycle/time/instret are not mapped, and HPM is not architectural.
+NUTSHELL_ISA_EXTENSIONS = ["i", "m", "a", "c", "zicsr", "zifencei"]
+NUTSHELL_LEGACY_ISA = "rv64imac_zicsr_zifencei"
 VECTOR_EXTENSIONS = {"v", "zvbb", "zvfh", "zvfhmin", "zvkt",
                      "zvl128b", "zvl32b", "zvl64b"}
 INITRD = """linux,initrd-start = <INITRAMFS_BEGIN_HI INITRAMFS_BEGIN_LO>;
@@ -40,6 +44,8 @@ def parse_name(name):
     fixed = {
         "xiangshan": (1, 128 << 20),
         "nutshell": (1, 128 << 20),
+        "nutshell-mem2g": (1, 2 << 30),
+        "nutshell-fpga": (1, 2 << 30),
         "spike": (1, 2 << 30),
         "spike-2core": (2, 2 << 30),
         "yanqihu": (1, 128 << 20),
@@ -304,6 +310,41 @@ def render_profile(profile_name, *, nr_harts=1, memory=None,
     output = output.replace("0x80300000 0x0 0x8300000", "0x80300000 0x0 0x08300000")
     return "/* Generated by nemu_board for workload-builder. */\n" + output + "\n"
 
+def render_nutshell_fpga(DTSGen, memory):
+    """NutShell FPGA: UART16550 + PLIC, 2 GiB, rv64imac/Sv39."""
+    cpu_props = cache_properties(timebase=True) + "\nnext-level-cache = <&l2_cache>;"
+    root_nodes = ["aliases { serial0 = &uart0; };", """l2_cache: l2-cache {
+    compatible = "cache";
+    cache-level = <2>;
+    cache-block-size = <64>;
+    cache-size = <1048576>;
+};"""]
+    gen = DTSGen(
+        compatible="freechips,rocketchip-unknown-dev",
+        model="ucas,nutshell-fpga",
+        cpu_compatibles=["UCAS,COOSCA1.0", "riscv"],
+        isa_extensions=DTSGen.sort_isa_extensions(NUTSHELL_ISA_EXTENSIONS),
+        legacy_isa=NUTSHELL_LEGACY_ISA,
+        mmu_type="riscv,sv39",
+        timebase_freq=1000000,
+        memories=[(DRAM_BASE, memory)],
+        reserved_memories=[],
+        uartlite_addr=None,
+        plic_addr=0x3c000000,
+        plic_ndev=66,
+        cpu_properties=cpu_props,
+        chosen_properties=chosen_properties("fpga"),
+        root_nodes=root_nodes,
+        interrupts_in_soc=True,
+        soc_compatible=["freechips,rocketchip-unknown-soc", "simple-bus"],
+        plic_node_name="interrupt-controller",
+        interrupt_reg_names="control",
+        bootargs="console=hvc0 earlycon=sbi loglevel=8",
+    )
+    gen.add_device(debug_controller(1))
+    gen.add_device(serial16550())
+    return gen
+
 
 def render(name, isa_config_name=None):
     nr_harts, memory = parse_name(name)
@@ -347,13 +388,15 @@ def render(name, isa_config_name=None):
                      uartlite_addr=None, bootargs="console=ttyS0 earlycon",
                      root_nodes=["htif { compatible = \"ucb,htif0\"; };"])
         gen.add_device(serial_spike())
-    elif name == "nutshell":
+    elif name == "nutshell-fpga":
+        gen = render_nutshell_fpga(DTSGen, memory)
+    elif name in {"nutshell", "nutshell-mem2g"}:
         gen = DTSGen(compatible="freechips,rocketchip-unknown-dev",
                      model="xiangshan,xiangshan-kunminghu",
                      cpu_compatibles=["UCAS,COOSCA1.0", "riscv"],
-                     isa_extensions=DTSGen.sort_isa_extensions("i m a c zicntr zicsr zifencei zihpm".split()),
-                     legacy_isa="rv64imafdc", mmu_type="riscv,sv39", timebase_freq=1000000,
-                     clint_addr=0x38000000, plic_addr=None, memories=[(DRAM_BASE, 128 << 20)],
+                     isa_extensions=DTSGen.sort_isa_extensions(NUTSHELL_ISA_EXTENSIONS),
+                     legacy_isa=NUTSHELL_LEGACY_ISA, mmu_type="riscv,sv39", timebase_freq=1000000,
+                     clint_addr=0x38000000, plic_addr=None, memories=[(DRAM_BASE, memory)],
                      reserved_memories=[], uartlite_addr=None,
                      chosen_properties=chosen_properties("nemu"),
                      bootargs="console=hvc0 earlycon=sbi")
diff --git a/workloads/linux/spec2006/README.md b/workloads/linux/spec2006/README.md
index af951d4..b682f5f 100644
--- a/workloads/linux/spec2006/README.md
+++ b/workloads/linux/spec2006/README.md
@@ -220,6 +220,12 @@ For GCC 15, select:
 workloads/linux/spec2006/configs/riscv_gcc15_base.cfg
 ```
 
+For NutShell, select the RV64IMAC/lp64 configuration:
+
+```text
+workloads/linux/spec2006/configs/riscv_gcc16_rv64imac_lp64.cfg
+```
+
 Override it with:
 
 ```sh
diff --git a/workloads/linux/spec2006/configs/riscv_gcc16_rv64imac_lp64.cfg b/workloads/linux/spec2006/configs/riscv_gcc16_rv64imac_lp64.cfg
new file mode 100644
index 0000000..6ee59d4
--- /dev/null
+++ b/workloads/linux/spec2006/configs/riscv_gcc16_rv64imac_lp64.cfg
@@ -0,0 +1,188 @@
+####################################################################
+# RISC-V Config file for SPEC CPU2006
+
+# Please see http://www.spec.org/cpu2006/Docs/config.html (also available in
+# the Docs directory of your SPEC tree) for details on config file setup.  The
+# config.html page has a list of all of the fields required for a full
+# publication ofresults.
+
+#####################################################################
+# System Under Test (SUT) Section
+
+# If it affects performance, you need to describe it, either in the
+# pre-defined fields or by adding it to the notes section. Replace the
+# setting below with the ones that match your machine.
+
+#######################################################################
+
+# Tester Description
+test_sponsor       = OSCPU
+tester             = OSCPU
+
+# System Description
+hw_model           = OSCPU NutShell
+hw_memory          = 2 GiB DDR
+hw_disk            = None
+hw_vendor          = Institute of Computing Technology, Chinese Academy of Sciences
+hw_other           = N/A
+hw_avail           = Dec-9999
+
+# CPU description
+# See http://www.spec.org/cpu2006/Docs/runrules.html#cpucount
+# for a discussion of these fields
+
+hw_cpu_name        = NutShell inorder RV64IMAC
+hw_cpu_char        =
+hw_cpu_mhz         = 350
+hw_fpu             = Soft-float
+hw_nchips          = 1
+hw_ncores          = 1
+hw_ncoresperchip   = 1
+hw_nthreadspercore = 1
+hw_ncpuorder       = N/A
+
+# Cache description
+
+hw_pcache          = N/A
+hw_scache          = N/A
+hw_tcache          = N/A
+hw_ocache          = N/A
+
+# Tester description
+
+license_num     = 0
+
+# Operating system, file system
+
+sw_os           = Linux with OpenSBI firmware boot
+sw_file         = initramfs rootfs
+sw_state        = Single-user
+sw_other        = None
+
+## SW config
+sw_compiler        = gcc, g++ 16.1.0 rv64imac/lp64
+sw_avail           = Jul-2026
+sw_base_ptrsize    = 64-bit
+sw_peak_ptrsize    = 64-bit
+
+#######################################################################
+# End of SUT section
+# If this config file were to be applied to several SUTs, edits would
+# be needed only ABOVE this point.
+######################################################################
+
+ignore_errors = yes
+tune          = base
+basepeak      = no
+ext           = riscv_gcc16_rv64imac_lp64
+teeout        = yes
+teerunout     = yes
+output_format = asc, csv, html
+makeflags     = -j64
+
+reportable    = yes
+
+default=default=default=default:
+#####################################################################
+#
+# Compiler selection
+#
+#####################################################################
+
+COMPILER_PATH      = ${LLVM_INSTALL_PATH}
+GCC_TOOLCHAIN_PATH = ${GNU_RISCV64_PATH}
+
+# Some SPEC C++ benchmarks define replaceable allocation symbols in
+# their own objects, so keep muldefs enabled for the final static link.
+STATIC_LDFLAGS     = -z muldefs -static
+
+CC  = $(COMPILER_PATH)/bin/riscv64-unknown-linux-gnu-gcc -std=gnu89
+CXX = $(COMPILER_PATH)/bin/riscv64-unknown-linux-gnu-g++
+FC  = $(COMPILER_PATH)/bin/riscv64-unknown-linux-gnu-gfortran
+
+#####################################################################
+# Optimization
+#####################################################################
+
+int=base=default:
+    COPTIMIZE       = -static -O3 -march=rv64imac -mabi=lp64 -ffast-math -flto  -ffp-contract=off -fno-tree-vectorize -fno-tree-loop-vectorize -fno-strict-aliasing
+    CXXOPTIMIZE     = -static -O3 -march=rv64imac -mabi=lp64 -ffast-math -flto  -ffp-contract=off -std=c++98 -fno-tree-vectorize -fno-tree-loop-vectorize -fno-strict-aliasing
+
+    EXTRA_LDFLAGS   = $(STATIC_LDFLAGS)
+
+fp=base=default:
+    COPTIMIZE       = -static -O3 -march=rv64imac -mabi=lp64 -ffast-math -flto  -ffp-contract=fast -fno-tree-vectorize -fno-tree-loop-vectorize -fno-strict-aliasing
+    CXXOPTIMIZE     = -static -O3 -march=rv64imac -mabi=lp64 -ffast-math -flto  -ffp-contract=fast -std=c++98 -fno-tree-vectorize -fno-tree-loop-vectorize -fno-strict-aliasing
+    FOPTIMIZE       = -static -O3 -march=rv64imac -mabi=lp64 -ffast-math -flto  -ffp-contract=fast -fno-tree-vectorize -fno-tree-loop-vectorize -fno-strict-aliasing
+
+    EXTRA_LDFLAGS   = $(STATIC_LDFLAGS)
+
+int=peak=default:
+    COPTIMIZE       = -static -O3 -march=rv64imac -mabi=lp64 -ffast-math -flto  -ffp-contract=off -ftree-vectorize -ftree-loop-vectorize -fno-strict-aliasing
+    CXXOPTIMIZE     = -static -O3 -march=rv64imac -mabi=lp64 -ffast-math -flto  -ffp-contract=off -std=c++98 -ftree-vectorize -ftree-loop-vectorize -fno-strict-aliasing
+
+    EXTRA_LDFLAGS   = $(STATIC_LDFLAGS)
+
+fp=peak=default:
+    COPTIMIZE       = -static -O3 -march=rv64imac -mabi=lp64 -ffast-math -flto  -ffp-contract=fast -ftree-vectorize -ftree-loop-vectorize -fno-strict-aliasing
+    CXXOPTIMIZE     = -static -O3 -march=rv64imac -mabi=lp64 -ffast-math -flto  -ffp-contract=fast -std=c++98 -ftree-vectorize -ftree-loop-vectorize -fno-strict-aliasing
+    FOPTIMIZE       = -static -O3 -march=rv64imac -mabi=lp64 -ffast-math -flto  -ffp-contract=fast -ftree-vectorize -ftree-loop-vectorize -fno-strict-aliasing
+
+    EXTRA_LDFLAGS   = $(STATIC_LDFLAGS)
+
+
+#####################################################################
+# 32/64 bit Portability Flags - all
+#####################################################################
+
+default=default=default=default:
+PORTABILITY    = -DSPEC_CPU_LP64
+
+#####################################################################
+# Portability Flags
+#####################################################################
+
+400.perlbench=default=default=default:
+CPORTABILITY   = -DSPEC_CPU_LINUX_X64 -std=gnu89
+
+401.bzip2=default=default=default:
+CPORTABILITY   = -std=gnu89
+
+416.gamess=default=default=default:
+CPORTABILITY   = -funconstrained-commons
+FPORTABILITY   = -std=legacy -funconstrained-commons -fno-strict-aliasing
+
+436.cactusADM=default=default=default:
+CPORTABILITY   = -std=gnu17
+
+462.libquantum=default=default=default:
+CPORTABILITY   = -DSPEC_CPU_LINUX
+
+464.h264ref=default=default=default:
+CPORTABILITY   = -fsigned-char
+
+482.sphinx3=default=default=default:
+CPORTABILITY   = -fsigned-char
+
+483.xalancbmk=default=default=default:
+CXXPORTABILITY = -DSPEC_CPU_LINUX -include cstring -Wno-c++11-narrowing -Wno-template-body
+
+453.povray=base=default=default:
+CXXOPTIMIZE     = -static -O3 -march=rv64imac -mabi=lp64 -flto  -ffp-contract=fast -std=c++98 -fno-tree-vectorize -fno-tree-loop-vectorize -fno-strict-aliasing
+
+453.povray=peak=default=default:
+CXXOPTIMIZE     = -static -O3 -march=rv64imac -mabi=lp64 -flto  -ffp-contract=fast -std=c++98 -ftree-vectorize -ftree-loop-vectorize -fno-strict-aliasing
+
+481.wrf=default=default=default:
+CPORTABILITY   = -DSPEC_CPU_CASE_FLAG -DSPEC_CPU_LINUX
+FPORTABILITY   = -std=legacy -fallow-argument-mismatch
+
+447.dealII=default=default=default:
+CXXPORTABILITY = -fpermissive -include cstring -std=c++11
+
+450.soplex=default=default=default:
+CXXPORTABILITY = -std=gnu++98
+
+#####################################################################
+# Notes
+#####################################################################