docs(dn): Simon Hu 03/01/2026 (#500)

Author: 1fHu

src/design_notebooks/2026spring/yh4970.md

@@ -1,5 +1,12 @@
 # Simon Hu - Design Notebook (Spring 2026)
 
+## Week 5
+### Comments:
+Read the paper NYU Processor Design Team SoC CPU Core
+
+Summary of the paper:
+This report introduces a single-core 32-bit CPU designed by the NYU Processor Design Team, supporting the RISC-V 32I instruction set. It employs a five-stage pipeline architecture (IF-ID-EX-MEM-WB) and implements key processor mechanisms such as branch prediction, a cache system, and hazard detection. The overall design is largely complete, with most modules implemented and tested, but further integration and verification are required to achieve a complete SoC tape-out.
+
 ## Week 4
 ### Comments:
 Understand the core of verification.