diff --git a/.gitignore b/.gitignore index 6a8a56f..86d63ad 100644 --- a/.gitignore +++ b/.gitignore @@ -13,3 +13,18 @@ sim/work-obj*.cf # Captured simulation outputs (e.g. mesh_impulse_response.txt from the testbenches) sim/*.txt +/hardware/_backups/ +/hardware/panel_2row_work/ +/hardware/panel_direct_stack_experiment/ +/hardware/courant_direct_stack_experiment/ +/RADIAN_PCBs_and_case_backup_*/ +/model/outputs/ +*.step +*.stp +*.zip +*.jar +*.png +*.pdf +*.pyc +**/__pycache__/ +/src/tb/*_trace.txt diff --git a/MILESTONES.md b/MILESTONES.md index db3f54d..754bdb5 100644 --- a/MILESTONES.md +++ b/MILESTONES.md @@ -1,23 +1,88 @@ # Milestones ## M0: Numerical reference model & stability study -- [ ] MATLAB/Octave reference model (`model/fdtd_ref.m`) -- [ ] CFL/stability sweep with plots -- [ ] Repository scaffolding: `src/`, `sim/`, `docs/` tree and GHDL CI +- [x] MATLAB/Octave reference model (`model/fdtd_ref.m`) +- [x] CFL/stability sweep with plots (`model/stability_study.m`) +- [x] Repository scaffolding: `src/`, `sim/`, `docs/` tree and GHDL CI + (`.github/workflows/ghdl-ci.yml` installs GHDL and runs `make -C sim`, + which wildcards every testbench) ## M1: Node PE RTL & unit test -- [ ] `src/rtl/fdtd_pkg.vhd` — Q1.23 types and `node_update` function -- [ ] `src/rtl/node_element.vhd` — single-node processing element -- [ ] `src/tb/node_element_tb.vhd` — unit testbench; passes `make -C sim` +- [x] `src/rtl/fdtd_pkg.vhd` — Q1.23 types and `node_update` function +- [x] `src/rtl/node_element.vhd` — single-node processing element +- [x] `src/tb/node_element_tb.vhd` — unit testbench ## M2: Full mesh and system testbench -- [ ] `src/rtl/grid_mesh.vhd` — NX×NY structural mesh with boundary wiring -- [ ] `src/tb/top_resonator_tb.vhd` — impulse-response and stability tests +- [x] `src/rtl/grid_mesh.vhd` — NX×NY structural mesh with boundary wiring +- [x] `src/tb/top_resonator_tb.vhd` — impulse-response and stability tests ## M3: I/O integration -- [ ] `src/rtl/i2s_transceiver.vhd` — I2S RX/TX + sample-strobe -- [ ] `src/rtl/top_resonator.vhd` — top-level with control bus and CDC +- [x] `src/rtl/i2s_transceiver.vhd` — I2S RX/TX + sample-strobe +- [x] `src/rtl/top_resonator.vhd` — top-level with control bus and CDC ## M4: Board bring-up -- [ ] Synthesis for Digilent Arty A7 (Artix-7 + PMOD I2S2) -- [ ] Resource budget documented in `docs/resource_budget.md` +- [x] Synthesis for Digilent Arty A7 (`syn/vivado/arty_synth.vhd`, + `build_arty.tcl`, `arty_a7.xdc`) +- [x] Resource budget documented in `docs/resource_budget.md` + +## M5: Standalone instrument board +- [x] `hardware/courant/` — tscircuit schematic for the Rev A board +- [x] Device pinouts checked against manufacturer datasheets +- [x] Board-specific electrical rule checks (`npm run check`) +- [x] Vivado pin constraints generated from the board's own `io` map +- [x] Route the board. 2192 segments, 4436.7 mm, 313 vias on six layers, both + ground planes uncut, no track under 0.15 mm: **0 DRC errors, 0 + unconnected**. tscircuit places it; KiCad writes the Specctra DSN and + Freerouting cuts most of the copper (`npm run route`). +- [x] Finish the last connections. The nine that no router could close were not + a routing problem: the back-side decoupling array was 0402 centred on the + ball grid, and a 0402 land spans 1.56 mm on a 1.0 mm pitch, so each + capacitor covered all four of its ball's escape slots — ten of the twenty + slots needed. `design.ts` now places them as 0201, offset half a pitch + diagonally onto a slot and turned 45 degrees, which costs one slot per + capacitor instead of four. `scripts/reland_decaps.py` moves that onto the + routed board without re-routing it; `scripts/close.py` then closes what + is left with a real grid search, since every earlier tool could only draw + straight lines, Ls and mitres and the survivors needed 20-36 segment + paths. The two 0.1373 mm clearance violations are fixed by shifting the + offending segment 0.02 mm, not by moving components. +- [ ] Measure the actual 5 V draw on a real board. Estimated at ~0.30 A against + the 3 A the source specifies; that one number decides whether a Eurorack + case's +5 V rail can run it (see `deliverables/courant-eurorack.md`). +- [ ] Eurorack, if wanted: an adapter cable with a fuse and reverse-polarity + diode is enough for power, and one 10 kOhm resistor per CV channel from + VREF25 converts the front end to +/-5 V bipolar exactly. Only modular-level + audio output needs new circuitry — the board is 4.5 dB below it and has no + bipolar rail to swing into. +- [x] Panel board integrated at `hardware/panel/` (RADIAN Panel P1): 180.6 × + 108 mm, 4 layers, carrying the panel controls and the 12 V → 5.08 V + inlet. Ground planes filled (they had outlines but no fill, so there was + no plane), DRC run for the first time and cleared 2 → 0 by moving SW3 + 0.6 mm off two header courtyards, Gerbers and drills generated, and all + 45 harness pins verified against the mainboard interface net for net. + Three `power_pin_not_driven` ERC findings remain by choice — see + `hardware/panel/INTEGRATION.md`. +- [ ] Fabricate and bring up: rails, JTAG, configuration, audio +- [x] SPI master RTL for the MCP3208 panel/CV ADC — `src/rtl/adc_mcp3208.vhd` + with `src/tb/adc_mcp3208_tb.vhd`. Scans CH0-2 (pots, to panel_ctrl) and + CH3-4 (pitch/mod CV, to cv_frontend) round-robin at 1 MHz SCLK, which is + the MCP3208's 2.7 V figure rather than its 5 V one because this board runs + it at VDD 3.3 V. **Not simulated here — GHDL is not installed in this + environment; the GHDL CI job is what verifies it.** + Integration note: the board's CV divider is 20k/20k into a 2.5 V + reference, so one volt is 819.2 codes, not the 4096 codes per volt + `cv_frontend`'s defaults assume. Instantiate it with CV_SCALE = 960, + CV_SHIFT = 16 for 1V/oct tracking. +- [x] Swap U1 to XC7A50T-1FTG256I. Done in `design.ts` and in the routed + board. The pin compatibility is now verified rather than assumed: + `reference/xc7a50tftg256pkg.txt` and `reference/xc7a35tftg256pkg.txt` are + byte-identical from line 2 to the end — all 256 balls, banks, I/O types + and no-connect flags — and differ only in the device name on the header + line. So the swap is a part number and nothing else: same footprint, + placement, copper, ball assignments and generated XDC. It is $51.74 + cheaper (JLCPCB $67.01 against $118.75, 135 in stock against 175), + carries 52,160 logic cells against 33,280 and 120 DSP slices against 90 — + taking the 4-voice build off 82% DSP utilisation — and is industrial + temperature range rather than commercial. `npm run check` passes. + Still worth a Vivado synthesis run to confirm timing closes (same -1 + speed grade, so it should). diff --git a/RADIAN_PCBs_and_case/06_final_actual_CAD_validation.json b/RADIAN_PCBs_and_case/06_final_actual_CAD_validation.json new file mode 100644 index 0000000..5c619da --- /dev/null +++ b/RADIAN_PCBs_and_case/06_final_actual_CAD_validation.json @@ -0,0 +1,57 @@ +{ + "status": "PASS", + "final_assembly": "panel/cad/RADIAN_actual_parts_full_assembly.step", + "colored_step_children": 715, + "children_missing_explicit_color": [], + "near_white_default_children": [], + "u8": { + "reference": "U8 / H11L1M", + "native_footprint_center_mm": [ + 48.0, + 139.0 + ], + "raw_kicad_step_expected_center_mm": [ + 48.0, + -139.0 + ], + "raw_kicad_step_actual_bbox_center_mm": [ + 48.0, + -139.0 + ], + "center_error_mm": [ + 0.0, + 0.0 + ], + "model": "courant/deliverables/cad/models/DIP6_W7.62_U8_centered.step", + "pin_alignment": "PASS: six STEP lead centers map exactly to six native footprint pads under KiCad Y inversion" + }, + "panel_drc": { + "violations": 0, + "unconnected": 0 + }, + "main_drc": { + "violations": 0, + "unconnected": 0 + }, + "direct_stack": { + "status": "PASS", + "checked": 40, + "matched": 40 + }, + "actual_part_collisions": { + "status": "PASS", + "panel_main_unintended_clashes": [], + "rear_guard_or_dock_clashes": [], + "intentional_stack_overlap": "P_STACK <-> M_STACK excluded; validated by direct-stack-validation.json" + }, + "model_policy": { + "actual_or_package_geometry": "PTV09A family, PJ398SM, Omron B3F, LEDs, all normal IC/passive packages and selected Wurth/Molex models", + "explicit_drawing_derived_only": [ + "PEC11R encoder", + "E-Switch MODE", + "Samtec stack pair", + "mainboard Molex J1-J4" + ], + "generic_white_component_envelopes": "NONE" + } +} diff --git a/RADIAN_PCBs_and_case/07_kicad_actual_model_validation.json b/RADIAN_PCBs_and_case/07_kicad_actual_model_validation.json new file mode 100644 index 0000000..84bd4bd --- /dev/null +++ b/RADIAN_PCBs_and_case/07_kicad_actual_model_validation.json @@ -0,0 +1,13 @@ +{ + "status": "PASS", + "renderer": "KiCad 10 high-quality 3D renderer", + "mainboard_models": {"total": 180, "colorless_or_missing": 0}, + "panel_models": {"total": 59, "colorless_or_missing": 0}, + "geometry_validation": "All changed representative 3D component bounding boxes matched before/after exactly.", + "electrical_geometry": "MATCH: footprint/pad/track/via/net signatures unchanged on both boards.", + "mainboard_drc": "0 violations, 0 unconnected items", + "panel_drc": "23 violations, 57 unconnected items; pre-change backup had 44 violations, 57 unconnected items", + "direct_stack": "PASS 40/40 contacts", + "collision_validation": "PASS: 0 enclosure clashes, 0 unintended panel/main clashes", + "j1_power_orientation": "preserved corrected orientation" +} diff --git a/RADIAN_PCBs_and_case/RADIAN_PCBs_and_case_latest/06_final_actual_CAD_validation.json b/RADIAN_PCBs_and_case/RADIAN_PCBs_and_case_latest/06_final_actual_CAD_validation.json new file mode 100644 index 0000000..5c619da --- /dev/null +++ b/RADIAN_PCBs_and_case/RADIAN_PCBs_and_case_latest/06_final_actual_CAD_validation.json @@ -0,0 +1,57 @@ +{ + "status": "PASS", + "final_assembly": "panel/cad/RADIAN_actual_parts_full_assembly.step", + "colored_step_children": 715, + "children_missing_explicit_color": [], + "near_white_default_children": [], + "u8": { + "reference": "U8 / H11L1M", + "native_footprint_center_mm": [ + 48.0, + 139.0 + ], + "raw_kicad_step_expected_center_mm": [ + 48.0, + -139.0 + ], + "raw_kicad_step_actual_bbox_center_mm": [ + 48.0, + -139.0 + ], + "center_error_mm": [ + 0.0, + 0.0 + ], + "model": "courant/deliverables/cad/models/DIP6_W7.62_U8_centered.step", + "pin_alignment": "PASS: six STEP lead centers map exactly to six native footprint pads under KiCad Y inversion" + }, + "panel_drc": { + "violations": 0, + "unconnected": 0 + }, + "main_drc": { + "violations": 0, + "unconnected": 0 + }, + "direct_stack": { + "status": "PASS", + "checked": 40, + "matched": 40 + }, + "actual_part_collisions": { + "status": "PASS", + "panel_main_unintended_clashes": [], + "rear_guard_or_dock_clashes": [], + "intentional_stack_overlap": "P_STACK <-> M_STACK excluded; validated by direct-stack-validation.json" + }, + "model_policy": { + "actual_or_package_geometry": "PTV09A family, PJ398SM, Omron B3F, LEDs, all normal IC/passive packages and selected Wurth/Molex models", + "explicit_drawing_derived_only": [ + "PEC11R encoder", + "E-Switch MODE", + "Samtec stack pair", + "mainboard Molex J1-J4" + ], + "generic_white_component_envelopes": "NONE" + } +} diff --git a/RADIAN_PCBs_and_case/RADIAN_PCBs_and_case_latest/07_kicad_actual_model_validation.json b/RADIAN_PCBs_and_case/RADIAN_PCBs_and_case_latest/07_kicad_actual_model_validation.json new file mode 100644 index 0000000..84bd4bd --- /dev/null +++ b/RADIAN_PCBs_and_case/RADIAN_PCBs_and_case_latest/07_kicad_actual_model_validation.json @@ -0,0 +1,13 @@ +{ + "status": "PASS", + "renderer": "KiCad 10 high-quality 3D renderer", + "mainboard_models": {"total": 180, "colorless_or_missing": 0}, + "panel_models": {"total": 59, "colorless_or_missing": 0}, + "geometry_validation": "All changed representative 3D component bounding boxes matched before/after exactly.", + "electrical_geometry": "MATCH: footprint/pad/track/via/net signatures unchanged on both boards.", + "mainboard_drc": "0 violations, 0 unconnected items", + "panel_drc": "23 violations, 57 unconnected items; pre-change backup had 44 violations, 57 unconnected items", + "direct_stack": "PASS 40/40 contacts", + "collision_validation": "PASS: 0 enclosure clashes, 0 unintended panel/main clashes", + "j1_power_orientation": "preserved corrected orientation" +} diff --git a/RADIAN_actual_parts_CAD/actual-parts-collision-validation.json b/RADIAN_actual_parts_CAD/actual-parts-collision-validation.json new file mode 100644 index 0000000..884728e --- /dev/null +++ b/RADIAN_actual_parts_CAD/actual-parts-collision-validation.json @@ -0,0 +1,16 @@ +{ + "status": "PASS", + "physical_pcb_faces": { + "panel_back_z_mm": -9.6, + "main_front_z_mm": -29.59, + "gap_mm": 19.99, + "target_mm": 19.99 + }, + "actual_components_vs_physical_enclosure_clashes": [], + "non_samtec_panel_vs_main_clashes": [], + "non_samtec_panel_vs_main_overlap_mm3": 0.0, + "notes": [ + "Reference nuts, shims, standoffs, inks and PCB visualization layers are excluded from enclosure clash classification.", + "The intentionally mated Samtec J100/J101 to J17/J18 pair is excluded from panel-vs-main clash classification." + ] +} diff --git a/RADIAN_actual_parts_CAD/actual-parts-full-assembly-validation.json b/RADIAN_actual_parts_CAD/actual-parts-full-assembly-validation.json new file mode 100644 index 0000000..c6801ba --- /dev/null +++ b/RADIAN_actual_parts_CAD/actual-parts-full-assembly-validation.json @@ -0,0 +1,39 @@ +{ + "status": "PASS", + "assembly": "panel/cad/RADIAN_actual_parts_full_assembly.step", + "renders": [ + "panel/previews/actual_parts_full_assembly_iso.png", + "panel/previews/actual_parts_full_assembly_side.png", + "panel/previews/actual_parts_full_assembly_front.png" + ], + "source_of_truth": "native KiCad component-filter STEP exports", + "color_persistence": "PASS: 715 colored children, 0 missing", + "u8_alignment": { + "reference": "U8 / H11L1M", + "native_footprint_center_mm": [ + 48.0, + 139.0 + ], + "raw_kicad_step_expected_center_mm": [ + 48.0, + -139.0 + ], + "raw_kicad_step_actual_bbox_center_mm": [ + 48.0, + -139.0 + ], + "center_error_mm": [ + 0.0, + 0.0 + ], + "model": "courant/deliverables/cad/models/DIP6_W7.62_U8_centered.step", + "pin_alignment": "PASS: six STEP lead centers map exactly to six native footprint pads under KiCad Y inversion" + }, + "collision_validation": { + "status": "PASS", + "panel_main_unintended_clashes": [], + "rear_guard_or_dock_clashes": [], + "intentional_stack_overlap": "P_STACK <-> M_STACK excluded; validated by direct-stack-validation.json" + }, + "placeholder_component_geometry_included": false +} diff --git a/RADIAN_actual_parts_CAD/actual_parts_report.json b/RADIAN_actual_parts_CAD/actual_parts_report.json new file mode 100644 index 0000000..a3b0231 --- /dev/null +++ b/RADIAN_actual_parts_CAD/actual_parts_report.json @@ -0,0 +1,61 @@ +{ + "status": "PASS", + "panel_native_board": "/home/ik/ChatGPT/Courant/hardware/panel/design/radian_panel.kicad_pcb", + "main_native_board": "/home/ik/ChatGPT/Courant/hardware/courant/deliverables/courant.kicad_pcb", + "dedicated_populated_board_cad": { + "panel": "panel/cad/RADIAN_actual_parts_panel_board.step", + "main": "panel/cad/RADIAN_actual_parts_main_board.step" + }, + "dedicated_populated_board_renders": [ + "panel/previews/actual_parts_panel_board_top.png", + "panel/previews/actual_parts_panel_board_bottom.png", + "panel/previews/actual_parts_main_board_top.png", + "panel/previews/actual_parts_main_board_bottom.png" + ], + "panel_groups": { + "P_POTS": "RV1,RV2,RV3,RV4,RV5,RV6", + "P_ENCODER": "ENC1", + "P_MODE": "SW1", + "P_JACKS": "J301,J302,J303,J304,J305", + "P_LEDS": "D10,D11,D12,D13", + "P_STACK": "J100,J101", + "P_WURTH": "J200,JP1", + "P_MOLEX": "J201,J202,J306", + "P_BUTTONS": "SW3,SW4", + "P_ACTIVE": "U1,U2,D1,D2,D3,D4,L1,F1,F2", + "P_PASSIVES": "R*,C*" + }, + "main_groups": { + "M_STACK": "J17,J18", + "M_MOLEX": "J1,J2,J3,J4", + "M_ICS": "U*,Y*", + "M_PASSIVES": "R*,C*", + "M_MAGNETICS": "L*", + "M_DIODES": "D*" + }, + "collision_validation": "Use direct-stack-validation.json and case_direct_stack_update.json; this renderer preserves native KiCad placement.", + "panel_transform": { + "x": 0, + "y": 128.5, + "z": -9.6 + }, + "main_transform": { + "x": -12, + "y": 164.25, + "z": -31.1 + }, + "actual_or_package_models": [ + "Bourns PTV09A family geometry aligned to PTV09A-4020F-B103 footprint/20 mm shaft", + "QingPu/Thonk PJ398SM open mechanical CAD with knurled nut", + "Omron B3F-1000 package geometry", + "3 mm green LED package geometry", + "all selected Wurth/Molex/Samtec and mainboard package STEP models already attached in KiCad" + ], + "drawing_derived_remaining": [ + "ENC1 Bourns PEC11R-4220F-S0024", + "SW1 E-Switch 100SP1T1B1M2REH", + "Samtec J100/J101/J17/J18", + "Molex mainboard J1-J4" + ], + "note": "No generic white component envelopes are used in this final assembly; component placement comes from KiCad STEP export." +} diff --git a/RADIAN_actual_parts_CAD/direct-stack-validation.json b/RADIAN_actual_parts_CAD/direct-stack-validation.json new file mode 100644 index 0000000..bfa30f1 --- /dev/null +++ b/RADIAN_actual_parts_CAD/direct-stack-validation.json @@ -0,0 +1,972 @@ +{ + "status": "PASS", + "sources": { + "stack_contract": "stack/panel-stack.json", + "panel_board": "panel/design/radian_panel.kicad_pcb", + "main_board": "courant/deliverables/courant.kicad_pcb", + "manufacturer_drawings": [ + "Samtec IPT1-1XX-XX-XX-D-XX Rev AA", + "Samtec IPS1-1XX-XX-XX-D-XX Rev S", + "Samtec IPX1 MATED DOCUMENT Rev C", + "Samtec IPT1 and IPS1 recommended through-hole PCB layouts" + ] + }, + "pairs": [ + { + "id": "A", + "main_ref": "J17", + "panel_ref": "J100", + "main_value": "IPT1-110-06-L-D", + "panel_value": "IPS1-110-01-L-D", + "main_side": "F", + "panel_side": "B", + "main_models": [ + "${KIPRJMOD}/../../stack/models/Samtec_IPT1-110-06-L-D_drawing_reference.step" + ], + "panel_models": [ + "${KIPRJMOD}/../../stack/models/Samtec_IPS1-110-01-L-D_drawing_reference.step" + ], + "pins": [ + { + "pin": 1, + "net": "GND", + "main_product_xy_mm": [ + 122.73, + 73.18 + ], + "panel_product_xy_mm": [ + 122.73, + 73.18 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 2, + "net": "VIN5", + "main_product_xy_mm": [ + 125.27, + 73.18 + ], + "panel_product_xy_mm": [ + 125.27, + 73.18 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 3, + "net": "VIN5", + "main_product_xy_mm": [ + 122.73, + 70.64 + ], + "panel_product_xy_mm": [ + 122.73, + 70.64 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 4, + "net": "VREF25", + "main_product_xy_mm": [ + 125.27, + 70.64 + ], + "panel_product_xy_mm": [ + 125.27, + 70.64 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 5, + "net": "GND", + "main_product_xy_mm": [ + 122.73, + 68.1 + ], + "panel_product_xy_mm": [ + 122.73, + 68.1 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 6, + "net": "POT_PITCH_RAW", + "main_product_xy_mm": [ + 125.27, + 68.1 + ], + "panel_product_xy_mm": [ + 125.27, + 68.1 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 7, + "net": "POT_DECAY_RAW", + "main_product_xy_mm": [ + 122.73, + 65.56 + ], + "panel_product_xy_mm": [ + 122.73, + 65.56 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 8, + "net": "POT_TIMBRE_RAW", + "main_product_xy_mm": [ + 125.27, + 65.56 + ], + "panel_product_xy_mm": [ + 125.27, + 65.56 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 9, + "net": "POT_DRIVE_RAW", + "main_product_xy_mm": [ + 122.73, + 63.02 + ], + "panel_product_xy_mm": [ + 122.73, + 63.02 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 10, + "net": "POT_DELAY_RAW", + "main_product_xy_mm": [ + 125.27, + 63.02 + ], + "panel_product_xy_mm": [ + 125.27, + 63.02 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 11, + "net": "POT_REVERB_RAW", + "main_product_xy_mm": [ + 122.73, + 60.48 + ], + "panel_product_xy_mm": [ + 122.73, + 60.48 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 12, + "net": "GND", + "main_product_xy_mm": [ + 125.27, + 60.48 + ], + "panel_product_xy_mm": [ + 125.27, + 60.48 + ], + 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41.73, + 70.98 + ], + "panel_product_xy_mm": [ + 41.73, + 70.98 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 10, + "net": "LED2_A", + "main_product_xy_mm": [ + 41.73, + 73.52 + ], + "panel_product_xy_mm": [ + 41.73, + 73.52 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 11, + "net": "LED3_A", + "main_product_xy_mm": [ + 44.27, + 70.98 + ], + "panel_product_xy_mm": [ + 44.27, + 70.98 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 12, + "net": "GND", + "main_product_xy_mm": [ + 44.27, + 73.52 + ], + "panel_product_xy_mm": [ + 44.27, + 73.52 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 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1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 17, + "net": "JTAG_TCK", + "main_product_xy_mm": [ + 51.89, + 70.98 + ], + "panel_product_xy_mm": [ + 51.89, + 70.98 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 18, + "net": "JTAG_TDO", + "main_product_xy_mm": [ + 51.89, + 73.52 + ], + "panel_product_xy_mm": [ + 51.89, + 73.52 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 19, + "net": "JTAG_TDI", + "main_product_xy_mm": [ + 54.43, + 70.98 + ], + "panel_product_xy_mm": [ + 54.43, + 70.98 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 20, + "net": "JTAG_TMS", + "main_product_xy_mm": [ + 54.43, + 73.52 + ], + "panel_product_xy_mm": [ + 54.43, + 73.52 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + } + ], + "main_center_product_mm": [ + 43.0, + 72.25 + ], + "panel_center_product_mm": [ + 43.0, + 72.25 + ], + "contract_center_product_mm": [ + 43.0, + 72.25 + ], + "matched_pins": 20 + } + ], + "mechanical": { + "fully_mated_gap_mm": 19.99, + "max_gap_mm": 20.45, + "fully_mated_wipe_mm": 0.84, + "min_wipe_at_max_gap_mm": 0.38, + "main_insulation_height_mm": 15.3, + "panel_height_mm": 8.51, + "nominal_geometric_insertion_mm": 3.82, + "geometric_insertion_at_max_gap_mm": 3.36, + "panel_tail_protrusion_past_opposite_face_mm": 0.94, + "main_tail_protrusion_past_opposite_face_mm": 0.75, + "panel_tail_to_faceplate_rear_clearance_mm": 7.06 + }, + "errors": [], + "total_contacts_checked": 40, + "total_contacts_matched": 40 +} diff --git a/RADIAN_actual_parts_CAD/final_actual_cad_validation.json b/RADIAN_actual_parts_CAD/final_actual_cad_validation.json new file mode 100644 index 0000000..5c619da --- /dev/null +++ b/RADIAN_actual_parts_CAD/final_actual_cad_validation.json @@ -0,0 +1,57 @@ +{ + "status": "PASS", + "final_assembly": "panel/cad/RADIAN_actual_parts_full_assembly.step", + "colored_step_children": 715, + "children_missing_explicit_color": [], + "near_white_default_children": [], + "u8": { + "reference": "U8 / H11L1M", + "native_footprint_center_mm": [ + 48.0, + 139.0 + ], + "raw_kicad_step_expected_center_mm": [ + 48.0, + -139.0 + ], + "raw_kicad_step_actual_bbox_center_mm": [ + 48.0, + -139.0 + ], + "center_error_mm": [ + 0.0, + 0.0 + ], + "model": "courant/deliverables/cad/models/DIP6_W7.62_U8_centered.step", + "pin_alignment": "PASS: six STEP lead centers map exactly to six native footprint pads under KiCad Y inversion" + }, + "panel_drc": { + "violations": 0, + "unconnected": 0 + }, + "main_drc": { + "violations": 0, + "unconnected": 0 + }, + "direct_stack": { + "status": "PASS", + "checked": 40, + "matched": 40 + }, + "actual_part_collisions": { + "status": "PASS", + "panel_main_unintended_clashes": [], + "rear_guard_or_dock_clashes": [], + "intentional_stack_overlap": "P_STACK <-> M_STACK excluded; validated by direct-stack-validation.json" + }, + "model_policy": { + "actual_or_package_geometry": "PTV09A family, PJ398SM, Omron B3F, LEDs, all normal IC/passive packages and selected Wurth/Molex models", + "explicit_drawing_derived_only": [ + "PEC11R encoder", + "E-Switch MODE", + "Samtec stack pair", + "mainboard Molex J1-J4" + ], + "generic_white_component_envelopes": "NONE" + } +} diff --git a/RADIAN_actual_parts_CAD/j1_power_orientation_validation.json b/RADIAN_actual_parts_CAD/j1_power_orientation_validation.json new file mode 100644 index 0000000..c0f048b --- /dev/null +++ b/RADIAN_actual_parts_CAD/j1_power_orientation_validation.json @@ -0,0 +1,13 @@ +{ + "status": "PASS", + "reference": "J1", + "part": "Molex 22-23-2021", + "board_center_mm": [30.0, 65.0], + "left_board_edge_mm": 19.95, + "model_rotation_about_footprint_deg": 180.0, + "lock_ramp_before_step_x_mm": 32.72, + "lock_ramp_after_step_x_mm": 27.28, + "orientation": "locking/friction-ramp side faces the left board edge", + "electrical_geometry": "pads and copper unchanged; J1.1 remains VIN5 and J1.2 remains GND", + "drc": "PASS: 0 violations, 0 unconnected items" +} diff --git a/README.md b/README.md index 4c129d2..da8f9b3 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -# Courant +# RADIAN A 2D finite-difference physical-modeling synthesis engine in structural VHDL, with an amplitude-dependent non-linear "chaos injection" term, playable @@ -16,7 +16,7 @@ shaped by recallable instrument presets and a live front panel. > **Status: simulation-first, feature-complete in simulation, pre-hardware.** > The engine, a Q1.23 reference model that is *bit-exact* to the RTL, and a full > playable top (MIDI/CV $\rightarrow$ polyphony $\rightarrow$ I2S audio) are -> developed and verified in GHDL across 23 testbenches. Board bring-up on a +> developed and verified under the current RTL regression across 31 testbenches. Board bring-up on a > Digilent Arty A7 + Pmod I2S2 is the next step; nothing is claimed to work on > hardware until it does. @@ -231,30 +231,22 @@ The engine is wrapped into a complete, flashable instrument - **MIDI** ([`midi_frontend.vhd`](src/rtl/midi_frontend.vhd) over [`midi_uart_rx.vhd`](src/rtl/midi_uart_rx.vhd)): parses the 31250-baud serial - stream and maps note number $\rightarrow$ $\gamma^2$ (pitch), velocity - $\rightarrow$ $\alpha$ (timbre) and strike amplitude, emitting note-on/off - events plus a one-frame excitation. See [`docs/midi.md`](docs/midi.md). -- **Control voltage** ([`cv_frontend.vhd`](src/rtl/cv_frontend.vhd)): the same - note-mapping interface, driven from 1V/oct pitch, a gate, and a mod CV. A - runtime `cv_sel` mux picks MIDI or CV, so one design plays from either; CV - inputs default off. See [`docs/cv.md`](docs/cv.md). + stream, maps note number through a discrete-mesh calibrated pitch table, and + maps velocity to strike amplitude only. CHAOS is an independent panel/CV + control. See [`docs/midi.md`](docs/midi.md). +- **Control voltage** ([`cv_frontend.vhd`](src/rtl/cv_frontend.vhd)): the same note-mapping interface, driven from 1V/oct pitch, a gate, and a mod CV. MIDI/CV arbitration is normally automatic: the newest MIDI note-on or CV gate edge claims the source. Presets/registers can force MIDI or CV, while the legacy `cv_sel` port remains only as a force-CV/debug override. See [`docs/cv.md`](docs/cv.md). - **Polyphony** ([`poly_voices.vhd`](src/rtl/poly_voices.vhd) + [`voice_allocator.vhd`](src/rtl/voice_allocator.vhd)): allocates each note to a free voice, runs `NVOICES` independent meshes, and averages their stereo pickups. With `TIME_MUX` the voices fold onto shared PEs so polyphony fits a small part. See [`docs/polyphony.md`](docs/polyphony.md). -- **Presets** ([`preset_bank.vhd`](src/rtl/preset_bank.vhd)): supplies the - instrument "body", the decay coefficients $a_0$ / $\mathrm{sigk1}$ and the CFL - clamp $\gamma^2_{\max}$, recalled and saved via the panel. A preset picks the - instrument; notes play it. See [`docs/presets.md`](docs/presets.md). -- **Front panel** ([`panel_ctrl.vhd`](src/rtl/panel_ctrl.vhd)): maps three pots - to live coefficients (with a dead-band so only real movement writes), a rotary - encoder to the preset index, and a button to short-press recall / long-press - save. See [`docs/panel.md`](docs/panel.md). +- **Presets** ([`preset_bank.vhd`](src/rtl/preset_bank.vhd)): supplies TENSION, DECAY, CHAOS, the CFL clamp, **STIFFNESS / plate dispersion**, **HARDNESS / stateful physical mallet**, pickup geometry, RIM compliance, STRIKE SIZE/X/Y, MATERIAL/ANISO/CHARACTER and source override. Voice-relevant settings are latched into each newly struck voice. See [`docs/presets.md`](docs/presets.md). +- **Front panel** ([`panel_ctrl.vhd`](src/rtl/panel_ctrl.vhd)): the existing MODE switch is PLAY/EDIT. PLAY keeps TENSION/DECAY/CHAOS/DRIVE/DELAY/REVERB and encoder preset navigation; EDIT reuses the encoder to select soft-takeover parameter pages, with SURFACE currently mapping ANISO/RIM/STRIKE SIZE/STRIKE X/STRIKE Y/CHARACTER. The four LEDs show voices in PLAY and the selected page in EDIT. No new pot, ADC channel, connector or PCB signal is required. See [`docs/panel.md`](docs/panel.md). The end-to-end path (MIDI/CV $\rightarrow$ note mapping $\rightarrow$ preset merge $\rightarrow$ polyphonic meshes $\rightarrow$ CDC $\rightarrow$ I2S) is described in [`docs/synth_top.md`](docs/synth_top.md). +The 2026-09-16 musical calibration/quality repair and acceptance results are in [`docs/sound_engine_repair.md`](docs/sound_engine_repair.md). --- @@ -266,12 +258,7 @@ explore the physics and to *lock the RTL numerically*. The linear spatially-varying ([`VarMesh2D.m`](model/VarMesh2D.m)) and non-linear ([`NLMesh2D.m`](model/NLMesh2D.m)) meshes each have a study script (stability, chaos, exciters, oversampling, materials). Crucially, -[`nl_reference.m`](model/nl_reference.m) regenerates a Q1.23 golden trace -(`src/tb/nl_mesh_trace.txt`) using the *same* saturating fixed-point arithmetic -as the fabric, and the corresponding testbench replays it step for step, so the -hardware is verified to be **bit-exact** to the model, not merely "close." -[`demo_render.m`](model/demo_render.m) renders musical, nonlinear, polyphonic -demo audio. +[`nl_reference.m`](model/nl_reference.m) regenerates the legacy nonlinear Q1.23 golden trace, while [`stiffness_reference.py`](model/stiffness_reference.py) and [`mallet_reference.py`](model/mallet_reference.py) independently regenerate the production fixed-point STIFFNESS and physical-mallet/HARDNESS traces. Their testbenches replay those traces step for step, so the corresponding hardware paths are verified **bit-exact** to independent models rather than merely "close." [`demo_render.m`](model/demo_render.m) renders musical, nonlinear, polyphonic demo audio. --- @@ -283,7 +270,7 @@ src/ I2S transceiver + master clock gen + sample strobe, cdc_word, MIDI + CV front-ends, voice allocator + polyphony, preset bank, panel controller, control bus, synth_top (the playable design) - tb/ 23 GHDL testbenches: unit (node, fdtd_pkg, i2s, cdc, uart) -> + tb/ 31 RTL testbenches: unit (node, fdtd_pkg, i2s, cdc, uart, mallet) -> bit-exact golden traces (nl_mesh, mesh_impulse, boundary, pickup) -> end-to-end audio (synth_top, poly, preset_top, latency) model/ MATLAB/Octave reference model (bit-exact to the RTL) + physics @@ -303,7 +290,7 @@ docs/ derivations, fixed-point + CFL analysis, per-feature notes The reference flow uses **GHDL** (open-source, VHDL-2008): ```sh -make -C sim # analyse + elaborate + run all 23 testbenches +make -C sim # analyse + elaborate + run all 31 testbenches octave-cli --eval "demo_render" # render nonlinear polyphonic demo audio (model/) cd syn/yosys && ./report_util.sh # DSP / LUT / FF resource estimate (yosys) ``` @@ -326,6 +313,19 @@ cheap and reproducible. The FPGA is the I2S master; the constraints live in flow ([`build_synth.tcl`](syn/vivado/build_synth.tcl)) runs opt/place/route and fails the build on negative slack (a pass/fail timing gate). +Beyond the dev board there is a **standalone instrument PCB** — a 160 x 100 mm +six-layer board carrying the XC7A35T, its configuration flash, both oscillators, +a PCM5102A stereo DAC, and the analog front end the Arty build leaves off (panel +pots and CV over an MCP3208, an opto-isolated MIDI input, a gate comparator). +It is written in [tscircuit](https://tscircuit.com) and lives in +[`hardware/courant/`](hardware/courant/); every device pinout is checked against +its manufacturer datasheet and the FPGA ball map against AMD's own package file. +It is **routed but never fabricated**: 1800 segments and 4152 mm of copper on +six layers, both ground planes uncut, with six BGA escapes still to finish by +hand. tscircuit places the board and owns the netlist; KiCad writes the Specctra +file and [Freerouting](https://freerouting.org) cuts the copper. See +[`docs/board.md`](docs/board.md) for what is and is not verified. + Using the time-multiplexed mesh (~18 DSP per voice, independent of grid size), resources scale roughly linearly with voice count: @@ -352,8 +352,9 @@ Vivado would infer LUTRAM/BRAM). Full table and caveats in verified in simulation. - It is **not** zero-latency, zero-aliasing, or single-clock-cycle. Those are marketing, and this document avoids them deliberately. -- It is **not** yet a hardware product: board bring-up and the analog front-end - (the pot / CV sampling ADC) remain. +- It is **not** yet a hardware product. The standalone board is drawn and + checked but unrouted and unfabricated, and the RTL that would read its panel / + CV ADC over SPI is not written yet. --- diff --git a/docs/README.md b/docs/README.md index 3f49fce..1b42642 100644 --- a/docs/README.md +++ b/docs/README.md @@ -8,12 +8,16 @@ Planned contents: - `deviations.md` — log of intentional deviations from the reference model - `synth_top.md` — end-to-end board top (MIDI → polyphony → I2S), datapath + clocking (issue #68) - `resource_budget.md` — DSP/LUT estimates per target (spatial vs. time-multiplexed) -- `exciters.md` — physical mallet/bow exciter front-ends study + recommendation (issue #33) +- `exciters.md` — physical mallet derivation + production HARDNESS/contact RTL; bow remains follow-up (issues #33/#87) - `spatial_variation.md` — per-node/region coefficient maps study + go/no-go (issue #32) -- `materials_stiffness.md` — bending-stiffness / anisotropy study + go/no-go (issue #31) +- `materials_stiffness.md` — bending-stiffness / anisotropy derivation plus production STIFFNESS RTL integration (issues #31/#86) - `presets.md` — preset format, factory presets, and how to author/load them -- `panel.md` — front-panel controller: knobs→coefficients, encoder→presets (issue #78) +- `panel.md` — front-panel PLAY/EDIT controller: six soft-takeover knobs, encoder-selected edit pages and presets (issues #78/#85) - `polyphony.md` — voice abstraction, allocation/stealing, and voice-count vs. cost -- `midi.md` — MIDI/CV front-end: note→pitch, velocity→strike/timbre mapping +- `midi.md` — calibrated MIDI/CV pitch; velocity→strike; independent CHAOS - `cv.md` — control-voltage front-end: 1V/oct pitch, gate strike, mod→timbre (issue #70) - `codec_bringup.md` — Pmod I2S2 (CS5343/CS4344) clocking, wiring, and bring-up +- `board.md` — standalone Rev A instrument PCB: blocks, footprints, routing status +- `finishing_the_route.md` — the six connections left on the routed board, and + how to close them in KiCad's interactive router +- `sound_engine_repair.md` — 2026-09-16 pitch/strike/CHAOS repair and RTL listening acceptance diff --git a/docs/board.md b/docs/board.md new file mode 100644 index 0000000..d77d60d --- /dev/null +++ b/docs/board.md @@ -0,0 +1,352 @@ +# Courant standalone board (Rev A) + +The Arty A7 + Pmod I2S2 target in [`syn/vivado/`](../syn/vivado/) is a bring-up +rig: it proves the RTL on hardware someone can buy for $130, but it is a +dev board with a synth bolted to it. This is the instrument version — a single +160 x 100 mm board carrying the FPGA, its configuration flash, both clocks, a +stereo DAC, and the whole analog front end the Arty build leaves off. + +The design lives in [`hardware/courant/`](../hardware/courant/) and is written in +[tscircuit](https://tscircuit.com): React/TypeScript that evaluates to Circuit +JSON, from which SVGs, Gerbers, a netlist, KiCad files and a Specctra DSN are +generated. `design.ts` is the netlist, `footprints.tsx` holds the few custom land +patterns, `courant.circuit.tsx` is the board. + +> **Current status (2026-09-16): routed, native DRC 0 errors / 0 warnings / 0 unconnected; not physically validated.** +> 2158 track segments, 4386.2 mm of track, 299 vias. Overlapping via holes and dangling copper were repaired. +> See [`hardware/REPAIR_STATUS.md`](../hardware/REPAIR_STATUS.md) and the current native JSON reports. +> The routing-development narrative below describes earlier stages, not the current outstanding work. + +--- + +## 1. Blocks + +| Block | Parts | Notes | +| --- | --- | --- | +| Power | U11–U13 TPS62130A, L1–L3 1 µH | 5 V in → 1.0 V / 1.8 V / 3.3 V, cascaded | +| FPGA | U1 XC7A50T-1FTG256I | 256-ball BGA, 1.0 mm pitch | +| Config | U2 W25Q64JVSSIQ | master SPI, 64 Mbit | +| Clocks | Y1 100 MHz, Y2 12.288 MHz | separate parts, see §3 | +| Audio | U3 PCM5102A | I2S, FPGA is master | +| Controls | U4 MCP3208, U5 REF3125 | 3 pots over SPI, 2.5 V reference | +| CV | U6 MCP6002, U7 MCP6561, D10–D12 BAT54S | pitch/mod in, gate comparator | +| MIDI | U8 H11L1M | opto-isolated, 31250 baud | + +### Power + +Three TPS62130A buck converters in a chain, each enabled by the previous one's +power-good pin: 5 V → 1.0 V (`VCCINT`/`VCCBRAM`) → 1.8 V (`VCCAUX`) → 3.3 V +(all `VCCO` banks). The A suffix matters — on the plain TPS62130 the power-good +pin is high-impedance while the part is disabled, so the chain would not start; +on the TPS62130A it is actively low, which is what makes the cascade a sequencer. +The last stage's power-good drives `PROGRAM_B`, holding the FPGA in reset until +3.3 V is up. + +Feedback dividers set 0.8 V x (1 + Rtop/Rbot): 24.9k/100k = 0.9992 V, 124k/100k = +1.79 V, 316k/100k = 3.33 V. `FSW` and `DEF` are tied low on all three, selecting +2.5 MHz and the nominal (not +5 %) output, which is what makes the 1 µH / 22 µF +output filter the right size. + +### FPGA and configuration + +Mode pins are strapped M[2:0] = 001 for master SPI (`M0` high, `M1`/`M2` low). +`CFGBVS` is tied to 3.3 V for a 3.3 V configuration bank. The XADC is unused, so +`VREFP` and `VREFN` are grounded and `VCCADC` sits on the 1.8 V rail, per UG480's +unused-XADC configuration. `PUDC_B` is pulled high so the I/O pull-ups are off +during configuration. + +The flash clock comes out of the dedicated `CCLK` ball (E8), not a user I/O — in +master SPI mode the STARTUPE2 primitive drives it. + +Decoupling is 38 x 100 nF 0201 on the back side directly under the BGA, distributed beneath the FPGA, plus bulk 47 µF/4.7 µF per rail. + +### Clocks + +Two oscillators rather than one, deliberately. A single 100 MHz source would +have to reach 12.288 MHz through an MMCM, and 12.288 does not divide cleanly +from 100 — the closest ratio leaves a residual frequency error that shows up as +audio sample-rate drift. A second 12.288 MHz part costs about a dollar and makes +the audio clock exact. Both land on clock-capable balls (D4 is MRCC, E3 is SRCC). + +### Audio + +PCM5102A in hardware mode: `FMT` low for I2S, `DEMP` low, `FLT` low for normal +latency, `XSMT` driven by the FPGA so the output can be muted before the mesh is +excited. Its analog 3.3 V comes through a series 1 Ω and its own bulk rather than +a separate LDO, which would cost output headroom for no measurable noise gain at +this level. Outputs are 470 Ω + 2.2 nF into the line jack. + +### Controls, CV and MIDI + +Three panel pots and both CV inputs are sampled by one MCP3208 over SPI, against +a REF3125 2.5 V reference. CV inputs are 0–5 V into a 20k/20k divider (so 0–2.5 V +at the ADC) with BAT54S rail clamps. The gate input is a comparator with a +divider-set threshold of about 2.0 V at the jack. MIDI is the standard +opto-isolated DIN input; DIN pin 2 is deliberately *not* connected to board +ground, which is the entire point of the isolation. + +--- + +## 2. Footprints + +Standard packages use [footprinter](https://github.com/tscircuit/footprinter) +strings, which are library-maintained and IPC-derived. Three are custom, each for +a reason recorded in `footprints.tsx`: + +- **`ftg256`** — footprinter's `bga256_…` numbers pin 1 from the lower left. The + design maps AMD's ball names (A1…T16) onto `pin(row*16 + col)` with A1 upper + left, so using the string would mirror every ball on the package vertically. +- **`qfn16`** — `qfn16_w3_h3_p0.5mm_thermalpad` places the signal pads' inner + edges 0.525 mm from centre against a 1.75 mm thermal pad that reaches 0.875 mm, + overlapping them by 0.35 mm and shorting all sixteen pins to the pad. TI's + RGT0016C exposed pad is 1.68 mm and its leads reach 1.5 mm from centre, so the + custom pattern uses 1.68 mm with the pads spanning 1.10–1.80 mm. +- **`soic8w208`** — the W25Q64JV's `SS` package is 208-mil SOIC-8, and + footprinter silently ignores the width modifier in `soic8_w5.3mm_p1.27mm`, + returning the 150-mil pattern. Derived from Winbond's package table with + IPC-7351 nominal fillets. + +The 3.2 x 2.5 mm oscillators and the 4 x 4 mm inductors have no footprinter +family and are spelled out. + +--- + +## 3. Routing + +tscircuit places this board and owns its netlist; it does not cut the copper. +That is done by [Freerouting](https://freerouting.org), through KiCad, and the +result comes back into the same board file the placement came out of: + +```sh +npm run export # dist/courant.kicad_pcb -- placed, no copper +npm run route # -> dist/courant.routed.kicad_pcb +npm run fab # -> DRC report, Gerbers, drill, placement, BOM, previews +``` + +`scripts/route.py` drives that loop end to end: it writes the design rules, has +KiCad write the Specctra DSN, runs the router headless, imports the session file +back and refills the ground planes. `scripts/fab.py` then runs KiCad's DRC and +plots the fabrication outputs. Both need tools npm cannot install -- KiCad 9+ +with its `pcbnew` Python module, a JRE, and `freerouting.jar` (point +`$FREEROUTING_JAR` at it) -- and both say so plainly if they are missing. + +Five things about that path are not obvious, and each one is a trap. + +### tscircuit's own autorouter does not converge + +tscircuit's bundled `capacity-autorouter` fails on this board with + +``` +Pipeline9 route "source_net_25_mst41" changes layers from z=5 to z=0 +without an explicit via (capacity-autorouter@0.0.900) +``` + +and emits no copper at all, leaving every port unrouted. That is a router defect +on a 256-ball BGA escape across six layers, not a netlist problem -- the same +netlist passes `tsci check netlist` and builds cleanly with routing disabled. +The board therefore carries `autorouter="none"`, which keeps every build fast +instead of spending about seventeen minutes to produce nothing. + +### tscircuit's Specctra export cannot be used either + +`tsci export -f specctra-dsn` is the advertised handoff to an external router, +and it is not usable here. It fails two ways, one loud and one silent: + +- **It crashes.** `convertCircuitJsonToDsnJson` groups pads by + `pcb_component_id` and then dereferences the resulting `pcbComponent.center` + without checking that the lookup found anything. This board's three fiducials + emit `pcb_smtpad` elements whose `pcb_component_id` is null, so the export + dies with `TypeError: undefined is not an object (evaluating + 'pcbComponent.center')` and writes no file. +- **It would be wrong if it did not crash.** The converter writes + `side: "front"` for every component regardless of the layer it is on. All 38 + decoupling capacitors on this board are on the back, directly under the BGA. + A DSN from that converter puts them on top, and nothing downstream would + catch it. + +KiCad's exporter gets both right, so `scripts/route.py` loads +`dist/courant.kicad_pcb` and calls `pcbnew.ExportSpecctraDSN`. That has a second +benefit: the router, the DRC and the Gerber plot then all read the same board +file and the same rules, so they cannot disagree about the board. + +### Net names must be distinct with case ignored + +Specctra folds net names to a single case. tscircuit and KiCad do not: `led0` +and `LED0` are two nets to them, and the DSN written from the board contains +both. Freerouting reads them as one, and the session file it writes back +mentions only `led0` -- so the four 1 kOhm LED series resistors R147-R150 came +back shorted across, as twelve `shorting_items` in DRC. + +The panel-side nets are therefore `LED0_A`..`LED3_A`, and `scripts/check.ts` +now fails the build if any two nets differ only by case. This is not a +theoretical hazard; it cost a routing run. + +### Keeping signals off the planes is a net-class rule, not a layer type + +This is the mistake worth reading before changing anything about the handoff. + +The obvious way to stop the router cutting up the ground planes is to declare +those layers `(type power)` in the DSN. It does not do that. Freerouting treats +a `power` layer as unavailable for connections altogether -- including the GND +pins that need to reach their own pour. The symptom is not an error; it is a +board that comes back with 55 to 60 connections unrouted, about fifty of them +GND, which reads exactly like a board too dense to route. + +It was misread that way here for three consecutive routing runs, and the +conclusion drawn was that the design needed eight layers. It did not. The +evidence was already visible and pointing elsewhere: fanout escape dropped from +94% to 69% the moment the planes were reserved, the via count *fell* while +routing layers were being added, and the new inner layers sat nearly empty +while the router "could not finish". All three say connections are being +refused, not that there is nowhere to put them. + +The mechanism that does what is wanted is a per-net-class `use_layer` clause. +Every layer stays `signal`, so vias and plane connections work normally, and +each class except the ground class is restricted to the non-plane layers. +`scripts/route.py` derives that from the board's own zones: layers carrying a +pour whose net is in `RETURN_NETS` are reserved, everything else is routable. +GND keeps the whole stackup. + +Measured on this board, all other settings equal: + +| Reserved | Unrouted | Signal segments cut through the planes | +| --- | --- | --- | +| nothing | 8 | 166 (1301 mm) | +| both ground planes, via `(type power)` | 56 | 0 | +| ditto, plus a V3V3 plane | ~90 | 0 | +| **both ground planes, via `use_layer`** | **9** | **0** | + +Eight layers with the broken mechanism gave 14; six layers with the correct one +gives 9. The board never needed the extra copper. + +### The default design rules cannot route a 1.0 mm BGA + +KiCad's defaults -- 0.2 mm track, 0.2 mm clearance, 0.6/0.3 mm via -- are not +merely tight here, they are geometrically impossible. FTG256 balls are 0.5 mm +pads on a 1.0 mm pitch, so the gap between two neighbouring balls is 0.5 mm. +Escaping a signal between them needs `width + 2 x clearance`, which at the +defaults is 0.6 mm. Nothing fits, and the router reports the pins as unroutable +rather than explaining why. + +`scripts/rules.json` carries the rules the package actually needs. It is written +out as `dist/courant.kicad_pro`, because KiCad keeps design rules in the project +file rather than the board file: + +| | Default | Power | Why | +| --- | --- | --- | --- | +| track | 0.15 mm | 0.4 mm | 0.15 + 2 x 0.15 = 0.45 mm clears the 0.5 mm ball gap | +| clearance | 0.15 mm | 0.15 mm | same sum; also the via-to-ball margin below | +| via | 0.55 / 0.25 mm | 0.55 / 0.25 mm | a dog-bone via sits 0.707 mm from four balls: 0.707 - 0.25 - 0.275 = 0.182 mm of clearance. A 0.6 mm via leaves 0.157 mm and fails | + +0.25 mm through a 1.6 mm board is a 6.4:1 aspect ratio, comfortably inside the +8:1 that plating prefers, and the 0.15 mm annular ring is past the 0.13 mm knee +where breakout risk collapses. All of it sits inside a standard six-layer +process. + +The Power class widens the rails but keeps the Default clearance and via +deliberately. `VCCINT`, `VCCAUX` and every `VCCO` ball is inside the same 1.0 mm +ball field as the signals, so a fatter power via could not be fanned out at all. +The rails take their width the moment they leave the package. + +Freerouting's automatic neckdown is switched off for the same reason the rules +exist: left on, it thins a trace to squeeze past an obstacle, and it produced +0.1124 mm copper against the 0.15 mm minimum in 70 places. The minimum is a fab +limit, not a preference. + +### Some copper is placed by hand, and the router must not touch it + +The twelve grounded thermal vias in the switchers' exposed pads (section 1) are +a thermal structure, not a connection. No autorouter has a reason to invent them +and every reason to delete them: KiCad writes pre-existing copper into the DSN's +wiring section as `(type route)`, which tells Freerouting it is looking at its +own previous output and may rip it up. `scripts/route.py` rewrites those to +`(type protect)` -- Freerouting's `SYSTEM_FIXED` -- before the router sees the +file, so the vias survive the round trip and are treated as obstacles while the +rest of the board is routed around them. All twelve come back. + +`scripts/check.ts` checks the same vias from the other side, in the netlist: that +each one lands inside a TPS62130A exposed pad without overhanging it, and that +no two barrels overlap. That is geometry the netlist cannot express and the +router will not police, and it is what would silently break if a regulator were +ever moved. + +### Running the router + +Freerouting's defaults are wrong for a batch run in three ways that cost real +time, and none of them is a command-line flag: + +- it opens a GUI and spends the run repainting it; +- its multi-threading feature flag is off -- though note this only affects the + optimizer, since the autorouter is single-threaded and measures at almost + exactly 1.00 cores whatever you pass to `-mt`; +- its fanout stage has no budget of its own and will spend the entire job on + itself. On this board fanout escapes about 94% of pins in three passes and + then grinds on the same ~30 it cannot place, at a minute or more a pass, until + the job times out with the autorouter never having started. + +All three live in a settings file, so `scripts/route.py` writes one and points +`$FREEROUTING__USER_DATA_PATH` at it. That also keeps the run out of the user's +own `~/.config/freerouting` and turns off the telemetry that is on by default. +Fanout is capped at six passes and the optimizer at 45 minutes so that the stage +which actually routes nets gets the time. + +`--gui` puts the board window up if you want to watch; it is slower. + +--- + +## 4. Building it + +```sh +cd hardware/courant +npm install +npm run verify # typecheck, board rules, netlist, and a clean build +npm run export # SVGs, netlist, KiCad board, and the Vivado XDC +npm run route # KiCad -> Freerouting -> routed KiCad board +npm run fab # DRC, Gerbers, drill, placement, BOM, board previews +``` + +`npm install` covers the first three. The last two need tools outside npm's +reach: + +| Tool | Used for | Where | +| --- | --- | --- | +| KiCad 9+ with `pcbnew` | DSN export, session import, DRC, Gerbers | distro package | +| a JRE | running the router | distro package | +| `freerouting.jar` | the router itself | [releases](https://github.com/freerouting/freerouting/releases), then `$FREEROUTING_JAR` | + +`npm run check` runs `scripts/check.ts`, which enforces the rules tscircuit +cannot know, all against AMD's own package file (`fpga-pins.json`, generated +from the checked-in `xc7a35tftg256pkg.txt` by `scripts/make-pinmap.py`): + +- no single-connection nets, no duplicate reference designators +- no two nets differing only by case, which Specctra would merge (section 3) +- every assigned ball exists in the FTG256 package, and no user signal lands on + a dedicated configuration or supply ball +- every bank carrying user I/O has all of its `VCCO` pins on the 3.3 V rail +- both clock inputs are on clock-capable (MRCC/SRCC) balls +- the master-SPI mode straps, `CFGBVS`, `VCCADC` and the unused-XADC ties +- no FPGA supply ball left unconnected, and one decoupling capacitor per + powered ball +- every thermal via inside the exposed pad it cools, and no two overlapping + +`npm run export` also generates `dist/courant_rev_a.xdc` from the same `io` map +the schematic uses, so the board's pinout and the constraints handed to Vivado +cannot drift apart. It is the board's half of the contract with +`src/rtl/synth_top.vhd`. + +`npm run fab` refuses to run on an unrouted board. Gerbers plotted from one +carry pads, soldermask and drills but no copper -- a file that looks exactly +like fabrication data and is not, which is the single mistake in this directory +that would cost real money. + +--- + +## 5. Current verification and remaining work + +Native Backplane KiCad 10.0.6 DRC reports zero errors, zero warnings and zero unconnected items on the installed mainboard. Checks include all configured severities. Original check settings were retained; ignored checks are listed in the report. Physical pads, net assignments, component placement and board outline were preserved. + +The former six remaining connections, clearance findings and dangling copper are no longer current open work. `finishing_the_route.md` is retained as historical context only. + +No native mainboard schematic is supplied, so mainboard ERC and native schematic/PCB parity are not claimed. No new manufacturer footprint approval, FPGA timing/bitstream execution, physical assembly, electrical, audio, thermal or fault tests were performed in this repair. Native geometric connectivity does not validate circuit function. + +The repository contains `src/rtl/adc_mcp3208.vhd` and its testbench; they were not modified or executed in this PCB repair. Validate the actual FPGA build before ordering hardware. diff --git a/docs/cv.md b/docs/cv.md index 663579f..0f5e022 100644 --- a/docs/cv.md +++ b/docs/cv.md @@ -22,8 +22,7 @@ the `gate` is brought in through a two-flop synchroniser inside the block. ## Mapping - **Pitch: 1V/oct → note → `gamma2`.** The pitch CV is quantised to a semitone - and looked up in the same note→`gamma2` table as `midi_frontend` (one octave = - `gamma2` x4, CFL-clamped). Calibration is by generics: + and looked up in the same **discrete-mesh calibrated** fixed/free table as `midi_frontend`. The table depends on `NX`, `NY`, `OS`, `FS_HZ`, and the current boundary mode; one octave still requires approximately `gamma2` x4 in the low-frequency limit. CV voltage calibration itself is by generics: ``` note = NOTE_REF + (pitch_cv - CV_OFFSET) * CV_SCALE >> CV_SHIFT (semitone) @@ -46,9 +45,7 @@ the `gate` is brought in through a two-flop synchroniser inside the block. amplitude stiffening): more mod = brighter, more non-linear. Unpatched (`mod_cv = 0`) gives `ALPHA_MIN`. -The fixed body fields (`a0`, `sigk1`, `gamma2_max`) come from generics, as in -`midi_frontend`; in a wired top they would instead come from `preset_bank` -(#30, #69), the same merge `synth_top` (#68) does. +`synth_top` merges the CV note/CHAOS values with the live preset body. TENSION, DECAY, pickup positions, boundary mode, and the CFL ceiling therefore behave the same whether the note source is CV or MIDI. ## Using it @@ -61,8 +58,7 @@ the strike; today the strike level is fixed and `mod_cv` shapes timbre. [`src/tb/cv_frontend_tb.vhd`](../src/tb/cv_frontend_tb.vhd) drives CV stimulus into the front-end and feeds its outputs into a live `mesh_resonator`. It checks: -0 V maps to the reference note (`gamma2 = 0.09`); +4096 counts (one octave) -quadruples `gamma2` (note +12); a gate edge delivers a strike (one frame of +0 V maps to the calibrated reference note; +4096 counts advances one octave and selects the corresponding calibrated coefficient; a gate edge delivers a strike (one frame of `exc_en`) and gate-low a note-off; more mod CV raises `alpha`; and the mesh sounds in response and stays inside Q1.23. Passes under GHDL: diff --git a/docs/exciters.md b/docs/exciters.md index 792073c..26d99a7 100644 --- a/docs/exciters.md +++ b/docs/exciters.md @@ -1,95 +1,133 @@ -# Exciter front-ends: mallet and bow (issue #33) +# Exciter front-ends: physical mallet and bow (issues #33 / #87) -A reference-model exploration of replacing the raw single-sample strike with -**physical exciter models** (milestone M9, stretch): a mallet whose hardness and -velocity shape the attack, and a bow/friction driver for sustained voices. This -note prototypes both, defines how they couple to the mesh, assesses RTL cost, and -recommends one for integration. Study only; the vehicle is -[`model/Exciter.m`](../model/Exciter.m) + -[`model/exciter_study.m`](../model/exciter_study.m). +Issue #33 studied stateful physical exciters. Issue #87 integrates the mallet +into the production RTL; the bow remains a follow-up study. -## Coupling: a stateful, bidirectional exciter on one node - -Courant's excitation today is a raw sample added at one node (`exc_in`, one-way). -A physical exciter is **bidirectional and stateful**: each step it *reads* the -surface displacement at the excitation node, computes a force from its own -internal state, and *adds that force back* at the node. Mechanically it is a -small state machine hanging off the existing `exc_in` node, the change is to make -`exc_in` dynamic and state-dependent rather than a fixed sample. - -## Mallet (lumped mass-spring contact) - -A piano-hammer / Chaigne-Askenfelt style contact. With hammer displacement `uh` -and surface displacement `us`, compression `eta = uh - us`: +The important change is that a mallet is no longer just a short envelope. It is +a state machine coupled to the modeled surface: ``` -F = k * [eta]_+^p (force only while in contact, eta > 0) -m * d2uh/dt2 = -F (the surface reaction decelerates the hammer) +eta = hammer_x - surface_u +F ~= HARDNESS * [eta]_+^2 +hammer_v' = hammer_v - reaction(F) +hammer_x' = hammer_x + hammer_v' ``` -**Hardness = `k`** (spring stiffness): a stiffer spring gives a shorter contact -and a broader, brighter attack; softer gives a longer, duller one. Contact time -also shortens with strike velocity, so brightness tracks how hard you hit, the -expressive core of a struck instrument, and exactly what a raw impulse cannot do. - -### Measured (from `exciter_study.m`) +Every mesh step the mallet reads the **actual quarter-cell strike-point surface +displacement**, computes contact force, applies it through the existing strike +footprint, and receives the reaction back into its own velocity. Contact can +therefore end early or late depending on both hammer state and surface motion. -| Mallet | `k` | Contact time | Spectral centroid | -| --- | --- | --- | --- | -| soft | 1e5 | 2.29 ms | 422 Hz | -| medium | 1e6 | 1.08 ms | 668 Hz | -| hard | 1e7 | 0.69 ms | 1029 Hz | +## Production HARDNESS control -Harder -> shorter contact -> brighter, monotonic and confirmed, with contact -times in the physically plausible sub-millisecond-to-few-millisecond range. -Audio: `model/outputs/exc_{soft,hard}.wav`. +HARDNESS is an unsigned 8-bit preset/control value stored in register 6 bits +23..16. Zero is an exact pre-#87 bypass. Nonzero values activate the physical +mallet when CHARACTER is **AUTO** or **MALLET**; explicit Point, Pluck, Rim and +Scrape modes keep their existing shaped-envelope behavior. -## Bow (friction / stick-slip driver) +Strike velocity and HARDNESS are independent: velocity initializes hammer +momentum, while HARDNESS changes the contact spring law. -A continuous friction force from the relative velocity `vrel = vbow - vs` -(`vs` = surface velocity): +The production contact curve is a multiplier-free piecewise approximation to +`eta^2`. The leading bit of positive compression selects a shift approximating +the second power, then the 8-bit HARDNESS value continuously scales that result +with static shift/add terms. The normalized gain is: ``` -F = Fn * sign(vrel) * (muD + (muS - muD) * exp(-|vrel| / vc)) +contact_gain = (32 + HARDNESS) / 64 ``` -The velocity-weakening (negative-slope) region is what sustains self-oscillation -(bowed metal / plate). The friction force is applied for the whole stroke, so -unlike a strike the excitation never stops. - -**Honest status**: in the simple lumped coupling used here the surface velocity -stays well below bow speed, so `vrel ~ vbow` (near-constant) and the drive is -closer to a quasi-static push than true stick-slip. A clean self-oscillating -Helmholtz motion needs the coupling **impedance-matched** so the surface velocity -reaches bow-speed scale and actually traverses the negative-slope region. Tuning -that loop (and its fixed-point limit-cycle stability) is real work, which is why -the bow is the **riskier, follow-up** exciter. The model, friction curve, and -coupling are in place as the starting point; `model/outputs/exc_bow.wav` is the -driven response. - -## RTL feasibility / cost - -Both exciters are a few operations on one node, reusing the node read the mesh -already exposes: - -- **Mallet**: hammer state (`uh`, `vh`), one `[eta]_+^p` (a compare + a square - for `p=2`), one constant `1/m` multiply, two integrator adds. **~3-4 DSP** and - a handful of registers, per voice. Cheap, self-contained, drops onto the - existing `exc_in` node with no mesh changes. -- **Bow**: the friction curve `mu(vrel)` is best a small **LUT (ROM)** + 1-2 - multiplies, plus a one-subtract surface-velocity estimate. Also cheap in gates, - but the stick-slip feedback loop needs care (impedance match + limit-cycle - stability in fixed point). - -## Recommendation: GO, mallet first; bow as a follow-up - -The mallet is the highest expressivity-per-gate feature on the roadmap: ~3-4 DSP -on one node turns the raw strike into a hardness- and velocity-sensitive contact, -most of what makes a struck instrument feel alive, and it needs no mesh changes. -Build it first. The bow (LUT friction) is the natural second exciter for -sustained voices once the mallet is proven and the friction feedback loop is -tuned. - -**Gate**: land exciters after the core is validated on real hardware (#26/#27); -they sit on the excitation node, so they want the baseline strike path proven in -silicon first. +The contact force that reacts on the hammer and the force injected into the mesh +use separate fixed unit-conversion scales. This mirrors the study model's +separate mechanical mass/contact and mesh coupling units without adding a +runtime divider. + +## Measured contact behavior + +`model/mallet_reference.py` independently mirrors the fixed-point production +mapping at the 192 kHz mesh-step rate used by OS=4 / 48 kHz audio: + +| Setting | HARDNESS | Contact steps | Contact time | +| --- | ---: | ---: | ---: | +| soft | `0x20` | 180 | **0.938 ms** | +| medium | `0x80` | 133 | **0.693 ms** | +| hard | `0xFF` | 105 | **0.547 ms** | + +At medium HARDNESS, changing strike velocity from 0.20 to 0.85 shortens contact +from 185 to 108 mesh steps. Thus the two contact-duration trends from the #33 +floating-point study survive the production normalization: **harder -> shorter +contact**, and **higher velocity -> shorter contact**. Shorter contact is the +physical mechanism expected to broaden/brighten the excitation; the automated +acceptance claim here is the measured contact duration rather than an invented +spectral score. + +The original SI-scale `Exciter.m` study measured 2.29 / 1.08 / 0.69 ms for its +soft / medium / hard examples. The exact milliseconds differ because the +production engine uses normalized fixed-point state and a deliberately +DSP-free contact approximation, but the physical ordering and sub-ms-to-ms +contact regime are preserved. + +## RTL architecture + +`physical_mallet.vhd` owns per-voice hammer position, velocity, contact history +and a bounded lifetime. It is instantiated inside both `grid_mesh` and +`grid_mesh_tdm`, where the actual strike-point surface state is available. + +- **Spatial mesh:** the contact displacement is bilinearly interpolated directly + from the live grid. +- **TDM mesh:** the four strike interpolation corners are captured during the + normal raster and become the next-step contact displacement at `FINISH`. +- The one-cycle note trigger only initializes the hammer. Force continues across + later oversample steps and audio frames until first separation. +- First separation terminates the contact episode; it cannot leave a stuck DC + force or enter an accidental uncontrolled re-contact/rattle loop. +- The existing balanced-free strike rule still applies when required. + +The TDM implementation latches the mallet force at the beginning of a sweep +before the hammer state advances on that same strobe. This preserves the same +update ordering as the spatial backend and is verified bit-for-bit. + +## FPGA cost + +The original study estimated ~3-4 DSPs for a literal power-law/contact +multiplier implementation. That is not acceptable on the current XC7A50T, +because the four-voice synth already uses 116/120 DSPs. + +The production implementation therefore uses no multiplier for the contact +curve. Open-source XC7 mapping of `physical_mallet` is: + +| Resource | Count | +| --- | ---: | +| DSP48E1 | **0** | +| LUT1..6 | **1,280** | +| FF | **61** | +| CARRY4 | **173** | + +This is per mallet instance before flattening/optimization with the surrounding +mesh. The binding resource remains the existing mesh/FX DSP budget. + +## Verification + +`mallet_tb` checks: + +- independent Python golden force, contact, active, position and velocity state; +- soft > medium > hard contact duration; +- higher strike velocity shortens contact; +- changing `surface_u` changes contact force (the feedback path is real); +- clean release with zero force after separation; +- bit-exact spatial/TDM mesh response under the stateful mallet. + +`preset_bank_tb` round-trips HARDNESS through user presets, and +`musical_controls_tb` writes HARDNESS through the real register interface and +requires the decoded I2S audio to change. + +## Bow status + +The #33 bow/friction model remains reference-only. It uses a velocity-weakening +friction curve and can provide sustained drive, but the simple study coupling +does not yet produce a robust impedance-matched stick-slip regime. That should +remain a separate follow-up rather than being hidden inside the completed +mallet issue. + +The original models remain in `model/Exciter.m` and `model/exciter_study.m`; +`model/mallet_reference.py` is the exact production fixed-point reference. diff --git a/docs/finishing_the_route.md b/docs/finishing_the_route.md new file mode 100644 index 0000000..656f850 --- /dev/null +++ b/docs/finishing_the_route.md @@ -0,0 +1,198 @@ +> Historical routing notes, superseded by the 2026-09-16 native repair. No unconnected items remain in the current mainboard; see `../hardware/REPAIR_STATUS.md`. + +# Finishing the last six connections + +`hardware/courant/dist/courant.routed.kicad_pcb` is routed except for six +connections. All six are BGA escapes that have to travel 15 to 46 mm, and all +six are blocked by a neighbouring trace rather than by distance -- which is why +the autorouter oscillated on them and why they need a router that can shove +existing copper aside. + +There were nine. Three were a BGA ball on the top and its decoupling capacitor +directly underneath, needing only a via between them, and `scripts/stitch.py` +placed those: it searches for a via position clear on *every* copper layer and +keeps the result only if KiCad's DRC agrees. The remaining six are real routing +and want a person. + +Budget twenty minutes. + +## 1. Open it + +```sh +cd hardware/courant +pcbnew dist/courant.routed.kicad_pcb +``` + +The project file `dist/courant.routed.kicad_pro` sits beside it, so the board's +real design rules load rather than KiCad's defaults. Confirm in +`File → Board Setup → Net Classes` that you see: + +| Class | Clearance | Track | Via | +| --- | --- | --- | --- | +| Default | 0.15 mm | 0.15 mm | 0.55 / 0.25 mm | +| Power | 0.15 mm | 0.40 mm | 0.55 / 0.25 mm | +| Ground | 0.15 mm | 0.30 mm | 0.55 / 0.25 mm | + +If those are missing you are editing without constraints — close, check the +`.kicad_pro` is present, and reopen. + +## 2. Turn on the one setting that matters + +`Route → Interactive Router Settings…` → **Mode: Shove**. + +This is the whole reason the job is quick. In *Highlight collisions* mode the +router refuses to cross an obstruction; in **Shove** it pushes the obstructing +trace out of the way and re-routes it. Every one of the six is blocked by a +neighbour, so without this you will be fighting the tool. + +Also worth setting, in the same dialog: + +- **Remove redundant tracks**: on +- **Optimise pad connections**: on +- **Allow DRC violations**: off — you want it to refuse rather than let you + create a short + +## 3. Work the list + +Open `Inspect → Design Rules Checker`, press **Run DRC**, and select the +**Unconnected Items** tab. That is your worklist: click an entry and the canvas +jumps to it. Re-run DRC to tick items off. + +The six, shortest first. Coordinates are KiCad page coordinates, which is what +the DRC panel and the cursor readout show. + +| # | Net | From | To | Gap | +| --- | --- | --- | --- | --- | +| 1 | `FLASH_CLK_RAW` | U1 ball **E8** @ 99.50, 91.50 | track on F.Cu @ 109.34, 102.43 | 14.7 mm | +| 2 | `INIT_B` | U1 ball **K10** @ 101.50, 96.50 | via @ 110.33, 108.67 | 15.0 mm | +| 3 | `PUDC_B` | track on F.Cu @ 111.17, 115.00 | U1 ball **L15** @ 106.50, 97.50 | 18.1 mm | +| 4 | `FLASH_MISO` | U1 ball **J14** @ 105.50, 95.50 | track on F.Cu @ 119.45, 121.36 | 29.4 mm | +| 5 | `JTAG_TCK` | track on In3.Cu @ 110.26, 140.41 | U1 ball **L7** @ 98.50, 97.50 | 44.5 mm | +| 6 | `reset_n` | track on F.Cu @ 87.17, 132.00 | U1 ball **B10** @ 101.50, 88.50 | 45.8 mm | + +Every one is the same shape of job: get off the ball, out through the ball +field, then across to the target. The standard move is a dog-bone -- a short +stub on F.Cu into the diagonal gap between four balls, a via there, then run out +on an inner layer. + +**The one thing to watch when placing that via.** A through via crosses all six +layers, and the diagonal gap that looks empty on F.Cu and B.Cu is often occupied +on In2 or In3 by a trace you cannot see. Two automated attempts here placed vias +that shorted to exactly that -- once to `dac_bclk` on In2. Before committing a +via, switch the view to In2 and In3 and check the slot is clear there too. The +interactive router in Shove mode will refuse a genuine collision, which is the +main reason to leave *Allow DRC violations* off. + +### What blocks each of the six + +Every one of these balls has four diagonal escape slots, and every one of those +24 slots is occupied -- almost always by traces the autorouter placed for other +nets, sometimes also by a back-side decoupling capacitor. This is the list to +work from: drag the named obstruction clear first, then escape. + +| Net | Ball | Best slot | In the way | +| --- | --- | --- | --- | +| `INIT_B` | K10 | (101.0, 97.0) | C121 + 1 trace | +| `JTAG_TCK` | L7 | (98.0, 98.0) or (99.0, 98.0) | 1 trace | +| `reset_n` | B10 | (101.0, 89.0) | 2 traces | +| `FLASH_MISO` | J14 | (105.0, 95.0) | 2 traces | +| `FLASH_CLK_RAW` | E8 | (99.0, 92.0) or (100.0, 91.0) | 3 traces | +| `PUDC_B` | L15 | (106.0, 97.0) | 4 traces | + +`JTAG_TCK` is the easiest -- one trace in the way and no capacitor. `PUDC_B` is +the worst. Working in that order is the path of least resistance. + +Note that the decoupling capacitors *can* be moved: a 0402 pad is 0.64 mm +across and needs 0.425 mm of clearance from a via, so a cap centred on a ball +blocks all four of its slots and a 0.3 mm nudge frees two of them. C121 sits at +exactly ball K10's coordinates. Moving one is fine; it is a decoupling cap on a +3 mm grid, not a critical placement. + +### Why this cannot be automated here + +Worth knowing before anyone tries again. Threading a trace between two FTG256 +balls is sub-grid geometry: + +``` +ball pad radius 0.250 mm ++ clearance 0.150 mm ++ half trace width 0.075 mm += trace centre at least 0.475 mm from a ball centre +midpoint between balls is 0.500 mm from each +-> routable corridor 0.050 mm wide +``` + +Fifty microns. A grid router needs cells well inside that to find the gap: at +0.1 mm it sees half a cell and reports the board as blocked, at 0.05 mm one +cell and only if it happens to align. 0.025 mm would work and is 640 million +cells across this board's signal layers. + +That is why every scripted attempt here failed, and it is not a matter of +writing them better -- they were grid routers, and this is continuous geometry. +Freerouting manages the other 1800 segments because it is a topological router +working in exact coordinates; KiCad's interactive router is the same, which is +why Shove mode solves in seconds what a lattice search cannot solve at all. + +Four of the six do have a clear escape via slot, found geometrically: +`INIT_B` at (103.0, 95.0), `PUDC_B` at (106.0, 99.0), `JTAG_TCK` at +(97.0, 96.0), `reset_n` at (100.0, 89.0). `FLASH_CLK_RAW` (ball E8) and +`FLASH_MISO` (ball J14) have no clear slot within 2.2 mm and will need a +neighbour moved first. + +## 4. Routing, concretely + +| Key | Does | +| --- | --- | +| `X` | start routing from whatever is under the cursor | +| click | anchor a corner | +| `V` | drop a via and switch to the next layer | +| `PgUp` / `PgDn` | jump to F.Cu / B.Cu | +| `Backspace` | undo the last segment while routing | +| `Esc` | abandon this trace | +| double-click | finish on the target | +| `D` | drag an existing trace | +| `Ctrl+Z` | undo | +| `` ` `` | highlight the net under the cursor | + +Highlighting the net (`` ` ``) before you start is worth the keystroke: it dims +everything else, so the ratsnest line you are chasing is unambiguous. + +## 5. Two rules while you work + +**Do not put copper on In1.Cu or In4.Cu.** They are the ground planes. Keeping +them uncut is the single biggest thing this layout has going for it — the +autorouter's unrestricted run cut them 166 times, including the I2S master and +bit clocks, and fixing that was most of the work. KiCad will happily let you +route there; don't. Your signal layers are **F.Cu, In2.Cu, In3.Cu, B.Cu**. In3 +also carries the 3.3 V pour, which is fine to cross — the pour refills around +you. + +**Leave the twelve via-in-pad warnings under U11–U13 alone.** Those are the +grounded thermal vias in the switchers' exposed pads, on GND, per TI's layout +guidance for the RGT0016C package. They are deliberate. + +## 6. While you are in there + +Two small things already on the board, both easy to fix by hand and neither +worth a separate session: + +- **Two clearance violations at 0.1373 mm** against the 0.150 mm rule. They + would very likely fabricate — most processes hold 0.09 to 0.127 mm — but they + break the rule the board declares. `Inspect → DRC` lists them; nudge the trace. +- **Four dangling vias**: escape vias the autorouter placed and then routed + around. Harmless, but they are holes the fab drills for nothing. Select and + delete. + +## 7. When you are done + +```sh +npm run fab +``` + +DRC, Gerbers, drill files, placement, BOM and board previews, into `dist/fab/` +plus `dist/courant-fab.zip`. It refuses to run while connections are missing, +which is why it has not run yet. + +Before ordering, see the open item in `MILESTONES.md` about swapping U1 to +**XC7A50T-1FTG256I** — same package, byte-identical pinout, $51.74 cheaper, 57% +more logic. It is a one-line change and it should happen before money is spent. diff --git a/docs/materials_stiffness.md b/docs/materials_stiffness.md index 82163da..33a0178 100644 --- a/docs/materials_stiffness.md +++ b/docs/materials_stiffness.md @@ -1,16 +1,17 @@ -# Advanced materials: bending stiffness and anisotropy (issue #31) +# Advanced materials: bending stiffness and anisotropy (issues #31 / #86) -A reference-model exploration of richer physics beyond the ideal membrane -(milestone M9, stretch): a 4th-order **bending-stiffness** term (bars, plates, -bells) and **anisotropic** propagation (direction-dependent wave speed). This -note derives the scheme, its stability condition, confirms it against the model, -estimates the RTL cost, and gives a go/no-go. It is a study, not an RTL change; -the vehicle is [`model/StiffMesh2D.m`](../model/StiffMesh2D.m) + -[`model/stiffness_study.m`](../model/stiffness_study.m). +Issue #31 established the reference-model physics and stability result for a +4th-order **bending-stiffness** term (bars, plates, bells) plus **anisotropic** +propagation. Issue #86 now integrates the bending term into the production RTL +for both spatial and time-multiplexed meshes. The floating-point study remains +[`model/StiffMesh2D.m`](../model/StiffMesh2D.m) + +[`model/stiffness_study.m`](../model/stiffness_study.m); the production fixed-point +control mapping is independently regenerated by +[`model/stiffness_reference.py`](../model/stiffness_reference.py). ## The equation -The ideal membrane (what Courant ships) is `u_tt = c^2 ∇^2 u`. Adding bending +The legacy/zero-STIFFNESS membrane is `u_tt = c^2 ∇^2 u`. Adding bending stiffness and anisotropy: ``` @@ -112,33 +113,80 @@ the partial ratios sharp (dispersion -> inharmonic bar/bell), and anisotropy "oval drum"). The wavs are git-ignored artefacts; regenerate with `octave-cli --eval "stiffness_study"`. -## RTL cost of the wider stencil - -The scheme stays **linear and explicit** (same class of update), so the only -changes are stencil width and one coefficient: - -- **Arithmetic**: neighbour taps grow `4 -> 12` (`~+8` adds in the accumulate); - `+1` coefficient multiply for `mu2*Biharm`; anisotropy splits the single - `gamma2*lap` multiply into `g2x*Dxx + g2y*Dyy` (`+1` multiply). Net roughly - **+1..2 DSP per node** over the 18-DSP membrane PE (~10%). -- **Memory / routing is the real cost**: the second ring needs `+-2` rows, so - the time-multiplexed mesh (issue #24) needs **two row line-buffers instead of - one**, and the fully-spatial mesh needs a wider neighbour fabric (diagonals + - second ring). Boundaries need a **2-cell ghost margin** and, for a properly - clamped plate, an extra edge condition (`u = 0` and `du/dn = 0`); the study - uses the simply-supported case (`u = 0`). -- **Stability** folds in for free: the existing compile-time CFL clamp just uses - the new closed-form bound `(g2x + g2y) + 16 mu2 <= 1`. - -## Recommendation: GO (conditional) - -The extension is modest and well-understood: one extra coefficient, a wider but -still-linear stencil, and a tighter but closed-form stability bound that drops -straight into the existing clamp. DSP cost is small; the line-buffer and -ghost-margin work is the real integration effort. It meaningfully widens the -palette (bars, plates, bells, anisotropic "oval" drums), which is exactly the -kind of distinctive voice worth having. - -**Gate**: land it *after* the core is validated on real hardware (issues -#26/#27), because it widens both the datapath and the memory subsystem, changes -best made once the baseline mesh is proven in silicon. +## Production RTL integration (#86) + +### Control encoding and stability + +STIFFNESS is stored in register 5 bits 23..16 and is latched per voice. The +production mapping deliberately makes zero an exact legacy bypass: + +``` +mu2 = STIFFNESS / 4096 +gamma2_max_eff = min(gamma2_max, 0.5 - STIFFNESS/512) +``` + +The second expression is the studied bound specialized to RADIAN's current +anisotropy operator, which redistributes X/Y propagation while preserving +`g2x+g2y = 2*gamma2`. Thus every nonlinear local `gamma2` value is clamped +before the update can violate `(g2x+g2y)+16*mu2 <= 1`. + +### Datapath + +`physical_pkg.biharmonic_term` evaluates the 13-point operator with adds and +shifts. `physical_pkg.stiffness_term` implements `mu2*Biharm` as an eight-bit +shift/add multiply followed by the same round-then-shift convention as +`mul_coeff`; it therefore does not allocate another DSP multiplier. +`node_element` subtracts that term in stage 3 and keeps its four-clock +pipeline latency. + +The fixed-boundary case uses zero padding outside the surface, matching the +reference study. Runtime free/compliant boundaries mirror the inward sample and +apply the existing RIM reflection law to the wider stencil as well. + +### Spatial and time-multiplexed backends + +The spatial backend forms the wider stencil directly from the live node grid. +The TDM backend avoids eight new simultaneous memory reads: four gather states +fetch two diagonal/second-ring taps per clock, followed by the normal update +state. These gather states are completely bypassed when STIFFNESS=0, preserving +legacy membrane timing. + +For the production 8x8 TDM grid a nonzero-stiffness mesh step is **322 system +clocks**; at OS=4 that is 1288 mesh clocks per audio frame before the small +`mesh_resonator` handshake overhead, below the 2083-clock budget at +100 MHz / 48 kHz. + +### Verification + +- `model/stiffness_reference.py` independently regenerates the committed + Q1.23 golden trace using the production 8-bit control encoding. +- `stiffness_tb` compares the TDM output to that golden trace, requires + spatial/TDM bit equality, exercises fixed and free/compliant boundaries, + checks the high-stiffness CFL clamp, and pins the 322-clock TDM step. +- The analytic discrete-mode check confirms dispersion rather than a global + pitch shift: with STIFFNESS=0x60, mode (1,1) rises about **3.5%** while mode + (4,4) rises about **41.9%**. +- Existing membrane golden tests remain bit-exact at STIFFNESS=0. + +### Open-source synthesis snapshot + +Using GHDL 6.0's built-in VHDL synthesis followed by Yosys 0.68 +`synth_xilinx -family xc7`: + +| block | DSP48E1 | LUT1..6 | FF | +| --- | ---: | ---: | ---: | +| `node_element` with runtime STIFFNESS | **18** | 1,911 | 480 | +| 8x8 `grid_mesh_tdm` with runtime STIFFNESS | **18** | 28,575 | 3,615 | + +The binding result is that STIFFNESS adds **no DSPs** to the mesh. The LUT number +is intentionally not treated as a board-fit verdict: this open-source flow +expands the multi-read TDM state into mux fabric, and the wider plate stencil +makes that pessimism more visible. Vivado implementation on the XC7A50T remains +the physical resource/timing sign-off. + +## Status + +The #31 recommendation is now implemented rather than conditional. RADIAN can +continuously move from the legacy tension-dominated membrane at STIFFNESS=0 +toward dispersive stiff sheets/plates while retaining the same preset format and +physical panel hardware. diff --git a/docs/midi.md b/docs/midi.md index 5378d15..50476d7 100644 --- a/docs/midi.md +++ b/docs/midi.md @@ -1,105 +1,74 @@ # MIDI / CV input front-end -Turning the engine from a physics demo into a playable instrument (milestone -M8). A serial MIDI stream drives pitch, strike energy, and timbre. The front-end -is [`src/rtl/midi_frontend.vhd`](../src/rtl/midi_frontend.vhd) (parser + mapping) -on top of [`src/rtl/midi_uart_rx.vhd`](../src/rtl/midi_uart_rx.vhd) (the serial -receiver). It emits a full `coeffs_t` plus the excitation, ready to drive -`mesh_resonator` / `top_resonator` in place of the control-bus + I2S excitation. +The playable RADIAN path maps MIDI/CV notes to the **actual discrete mesh** rather +than treating `gamma2` as an arbitrary pitch knob. RTL lives in +[`midi_frontend.vhd`](../src/rtl/midi_frontend.vhd), +[`cv_frontend.vhd`](../src/rtl/cv_frontend.vhd), and +[`musical_pkg.vhd`](../src/rtl/musical_pkg.vhd). -## Signal chain +## Pitch calibration -``` -MIDI in --> midi_uart_rx --> parser --> note/velocity mapping --> coeffs + exc - (31250 (8N1 byte) (note-on/ (pitch / strike / timbre) to the mesh - baud) note-off) -``` - -- **midi_uart_rx**: standard oversampling UART at 31250 baud, 8 data bits - LSB-first, no parity, one stop bit. The bit period is `CLK_HZ / BAUD` system - clocks (3200 at 100 MHz). Synchronise the raw MIDI pin with a two-flop - synchroniser before this block on hardware. -- **parser**: recognises Note On (`0x9n`) and Note Off (`0x8n`), including - running status (a data byte with no preceding status reuses the last one) and - the Note On velocity-0 convention (treated as Note Off). Other channel and - system/real-time bytes are skipped without disturbing running status. - -## Mapping (all generics, so it is configurable) - -### Pitch: note number -> `gamma0^2` (`coeffs.gamma2`) - -A mesh mode's frequency scales with the wave speed `c`, and -`gamma2 = (c*k/h)^2` scales with `c^2`. So doubling the frequency (one octave) -needs `gamma2` to quadruple. The note-to-gamma2 map is therefore exponential -with a slope of 6 semitones per gamma2 doubling: +For a requested note frequency `f`, `note_gamma2` solves the discrete 2-D mesh +dispersion relation at the configured `NX`, `NY`, oversampling factor `OS`, +audio rate, and boundary mode: ``` -gamma2(note) = GAMMA2_REF * 2^((note - NOTE_REF) / 6) +gamma2 = 4*sin(pi*f/(fs*OS))^2 / lambda_mode ``` -clamped to `[GAMMA2_MIN, GAMMA2_CLAMP]` with `GAMMA2_CLAMP < 0.5` to stay inside -the CFL stability limit. The table is precomputed at elaboration into a 128-entry -ROM (note -> Q1.23), so there is no runtime `pow`. Defaults: `NOTE_REF = 69` -(A4), `GAMMA2_REF = 0.09`, `GAMMA2_CLAMP = 0.45`. - -Because the grid is fixed, the playable pitch range is bounded: high notes -saturate at `GAMMA2_CLAMP` (a fixed mesh has a finite pitch range; retuning the -physical size/`h` would extend it). This is honest, documented behaviour. +`lambda_mode` is the lowest non-DC eigenvalue for the selected fixed or free +boundary. The 128-entry fixed/free tables are evaluated at elaboration, so no +real-valued arithmetic is synthesized. The old raw `GAMMA2_REF` mapping remains +available with `CALIBRATED_PITCH=false` for explicit coefficient experiments. -| Note | Offset from A4 | `gamma2` | Notes | -| --- | --- | --- | --- | -| A3 (57) | -12 | 0.0225 | one octave down (÷4) | -| A4 (69) | 0 | 0.090 | reference | -| A5 (81) | +12 | 0.360 | one octave up (×4) | -| high | large | 0.45 (clamped) | CFL ceiling | +The acceptance sweep checks notes 45/57/69/81 (110/220/440/880 Hz), 8x8 and +16x16 meshes, OS=1/2/4, 48/96 kHz, and fixed/free boundaries. Analytic error is +required below 5 cents; native RTL spectral probes on the production 8x8/OS4 +configuration measured the four fixed/free notes within about 1 cent. -### Strike: Note On -> excitation impulse (the mallet) +## Strike and CHAOS -A Note On delivers one frame of excitation into the mesh (`exc_en` asserted for -the next audio frame). The impulse amplitude scales with velocity: +MIDI velocity now controls **strike energy only** by default: ``` -exc_in = STRIKE_GAIN * velocity / 128 (Q1.23) +exc_in = STRIKE_GAIN * velocity / 128 ``` -Default `STRIKE_GAIN = 0.9`, so velocity 127 is a near-full-scale strike and -velocity 1 is a gentle tap. A Note Off (or Note On with velocity 0) does **not** -strike: the mesh decays naturally through its damping (`sigk1`), exactly like a -struck instrument releasing. - -### Timbre: velocity -> chaos coupling `alpha` +`STRIKE_GAIN` defaults to `0.002`, chosen to keep musical acceptance probes away +from Q1.23 cell clipping. `ALPHA_MAX` defaults to zero on the MIDI front end, so +a harder key no longer silently increases CHAOS. -Harder hits also ring more non-linearly. Velocity maps to `coeffs.alpha` -(README §2, amplitude-dependent stiffening) between `ALPHA_MIN` and `ALPHA_MAX`: +CHAOS is an independent control. The panel/preset register and CV modulation +feed it separately; `synth_top` scales the non-linear coefficient with the +current tuned `gamma2` so its audible strength remains useful across pitch. +The CFL ceiling remains 0.451. -``` -alpha = ALPHA_MIN + (ALPHA_MAX - ALPHA_MIN) * velocity / 128 -``` +## TENSION and body controls -Defaults `ALPHA_MIN = 0.0`, `ALPHA_MAX = 0.3`. Set `ALPHA_MAX = 0` for a purely -linear instrument (velocity then affects loudness only). The CFL clamp -(`gamma2_max`, default 0.451) keeps the non-linear term stable at any velocity. +The note table establishes concert pitch. Preset register 0 is then a normalized +**TENSION** multiplier: `0.25` is unity, the panel default range 0.0625..~1.0 +covers approximately -1 to +1 octave around the played note. DECAY (`a0` / +`sigk1`), CHAOS, pickup positions, and boundary mode come from the live preset +registers and are captured into a voice when it is struck. -### Fixed coefficients +## MIDI parser -`a0`, `sigk1` (damping) and `gamma2_max` (CFL clamp) are held at generic -defaults (`0.99996875`, `0.99996875`, `0.451`); only `gamma2` and `alpha` move -with the note. Adjust the generics for a different decay time or stability -margin. +The UART remains 31,250 baud, 8N1. The parser handles Note On/Off, running +status, and Note-On velocity zero as Note Off. Other channel/system bytes are +ignored without corrupting running status. A strike is delivered on the next +audio frame; Note Off releases allocation and leaves the resonator tail to +decay naturally. -## CV alternative +## CV path -The same mapping applies to control voltage: replace `midi_uart_rx` with an ADC -reading a pitch CV (-> note index) and a gate/velocity CV (-> strike), feeding -the identical note/velocity mapping. The parser stage is MIDI-specific; the -mapping stage is not. +Pitch CV quantizes to the same calibrated note table. Gate produces a strike; +mod CV controls CHAOS independently. The fixed/free table is selected from the +current preset boundary mode, exactly as for MIDI. ## Verification -[`src/tb/midi_frontend_tb.vhd`](../src/tb/midi_frontend_tb.vhd) sends a real -MIDI byte stream (start / 8 data LSB-first / stop) into the front-end, feeds its -coeffs + excitation into a live `mesh_resonator`, and checks: a Note On is parsed -(note + velocity recovered); an octave up quadruples `gamma2`; a Note On delivers -a strike; a harder hit raises both the strike amplitude and `alpha`; the mesh -produces output in response; and a Note Off does not strike (natural decay). All -pass under GHDL. +`midi_frontend_tb`, `cv_frontend_tb`, `pitch_calibration_tb`, +`musical_controls_tb`, `runtime_mesh_tb`, and `synth_top_tb` cover parsing, +calibrated pitch, independent CHAOS, runtime pickup/boundary routing, the panel +macros reaching audio, and the complete MIDI/CV -> polyphony -> I2S path. +The final repair regression passes all 28 RTL testbenches under NVC. diff --git a/docs/panel.md b/docs/panel.md index 0cbe99f..6587dfb 100644 --- a/docs/panel.md +++ b/docs/panel.md @@ -1,58 +1,75 @@ # Panel controller -Wires the physical front panel to the engine (issue #78): macro knobs set the -live coefficients and a rotary encoder + button select and recall presets, all -through the `preset_bank` register / preset interface (#30, #69). RTL: -[`src/rtl/panel_ctrl.vhd`](../src/rtl/panel_ctrl.vhd). +Wires the physical front panel to the engine (issues #78 and #85): six macro +pots edit live parameters, while the existing MODE switch and bottom-left push +encoder provide a PLAY/EDIT page model through the `preset_bank` register / +preset interface. RTL: [`src/rtl/panel_ctrl.vhd`](../src/rtl/panel_ctrl.vhd). ## Control map -| Control | Target | Register | Range (default) | -| --- | --- | --- | --- | -| `pot_pitch` | `gamma2` (pitch / tension) | 0 | 0.02 .. 0.44 | -| `pot_decay` | `sigk1` **and** `a0` (decay) | 2, 1 | 0.9950 .. 0.99999 | -| `pot_timbre` | `alpha` (chaos / timbre) | 3 | 0.0 .. 0.40 | -| encoder turn | `preset_index` | - | 0 .. N_PRESETS-1 | -| encoder button, short press | `recall` | - | load selected preset | -| encoder button, long press | `save` | - | store into a user slot | - -The pot ranges, ADC width, dead-band, and long-press threshold are all generics. - -## Behaviour - -- **Pots -> coefficients.** Each pot is scaled from its ADC range into the - register's Q1.23 range and written on **change only**: a scanner cycles the - four macro registers one per clock, and a register is rewritten only when its - pot moved past the `DEADBAND` (rejecting ADC LSB jitter), so the single-port - register bus is never flooded. The decay knob drives both `sigk1` and `a0` - with the same value (`a0 ~= sigk1` over the small `sigma*k` a knob spans - a - documented macro approximation). -- **Encoder.** One `preset_index` step per rising edge of channel A, direction - from channel B, saturating at the ends. Turning only *selects*; it does not - auto-recall. -- **Button.** A short press pulses `recall` (load the selected preset); holding - past the long-press threshold pulses `save` (store the live registers into the - selected user slot; `preset_bank` ignores saves aimed at factory slots). -- **Recall vs. live knobs ("pickup").** After a recall the live registers hold - the recalled preset. The panel only writes a register when its pot *moves* - (the pot target then differs from the panel's last write), so the recalled - sound stays until you actually turn a knob, which then takes over that - parameter. Simple pickup behaviour, no knob-jump on recall. +No pot, ADC channel, connector, or PCB signal was added. The existing two-state +MODE switch is now semantic rather than a direct two-layer selector: + +- **PLAY (`sw0=0`)**: the six knobs are the immediate performance controls and + the encoder selects presets. +- **EDIT (`sw0=1`)**: the encoder selects an edit page and the same six knobs + edit that page. The four panel LEDs become a one-hot page indicator. + +EDIT page 0 is **SURFACE**, preserving the previous Membrane-layer mapping: + +| Physical pot | PLAY | EDIT / SURFACE (page 0) | +| --- | --- | --- | +| TENSION | TENSION | ANISO (-8..+7, center = isotropic) | +| DECAY | DECAY | RIM compliance (fixed -> compliant/free) | +| CHAOS | CHAOS | STRIKE SIZE (point -> broad membrane contact) | +| DRIVE | DRIVE | STRIKE X | +| DELAY | DELAY | STRIKE Y | +| REVERB | REVERB | CHARACTER (Auto / Point / Mallet / Pluck / Rim / Scrape) | + +`N_EDIT_PAGES` is a synthesis-time panel-controller generic in the range 1..4. +Only page 0 is populated by issue #85. Higher pages are intentionally inert +until their backing parameter sets land; selecting a reserved page cannot alias +SURFACE registers. The production wrapper currently defaults to one edit page. + +## Encoder and LEDs + +In **PLAY**, encoder behavior is unchanged: turn selects `preset_index`, short +press recalls, and long press saves. In **EDIT**, encoder A/B instead changes +`edit_page` by one page per detent, wrapping at either end. The preset index is +not touched. The selected page is remembered when returning to PLAY. + +Button gestures are disabled in EDIT. A press begun in EDIT stays blocked until +the button is physically released after returning to PLAY, so it cannot become +an accidental preset recall or save. + +The four LEDs show the active-voice mask in PLAY. In EDIT they show the page +one-hot: page 0 = `0001`, page 1 = `0010`, page 2 = `0100`, page 3 = +`1000`. + +## Soft takeover + +A unified scanner reads the currently stored register value before considering +each pot. On reset, preset recall, PLAY/EDIT transition, or EDIT-page change, +all six pots disarm. A pot produces no write until its mapped value crosses the +stored parameter (or lands inside its dead-band), then tracks normally. + +That rule also applies when returning to a previously edited page: page +selection alone cannot move any physical parameter. DECAY continues to write +both `sigk1` and `a0`. ## Inputs -The pot ADC samples are assumed synchronous to `clk`; the encoder (A/B) and the -button are asynchronous and are brought in through two-flop synchronisers inside -the block. Drop `panel_ctrl` alongside `synth_top` and connect its `cfg_*` / -`preset_*` outputs to the `preset_bank` control ports (the same ports -`synth_top` already exposes). +Pot ADC samples are assumed synchronous to `clk`. Encoder A/B and its push +button are asynchronous and pass through two-flop synchronisers in +`panel_ctrl`. `arty_synth` connects the physical MODE switch to `edit_mode`; +MIDI/CV source claiming remains automatic in `synth_top`. ## Verification -[`src/tb/panel_ctrl_tb.vhd`](../src/tb/panel_ctrl_tb.vhd) wires `panel_ctrl` into -a real `preset_bank` and checks the panel reaches the coefficients: moving the -pitch/timbre/decay pots writes and updates `gamma2` / `alpha` / `sigk1`+`a0` on -`preset_bank.coeffs`; stable pots produce no further writes (dead-band); the -encoder steps `preset_index`; a short button press recalls the selected preset -(coeffs load the gong factory values) and a long press emits save. Passes under -GHDL. +[`src/tb/panel_ctrl_tb.vhd`](../src/tb/panel_ctrl_tb.vhd) wires `panel_ctrl` +into a real `preset_bank`. It instantiates three edit pages to verify the page +infrastructure even though only SURFACE is populated: contextual encoder +routing, forward/reverse page wrap, remembered page state, one-hot LED state, +inert reserved pages, blocked EDIT button gestures, and soft takeover across +PLAY/EDIT/page transitions. It also regression-checks all PLAY controls, +SURFACE controls, and PLAY preset recall/save. diff --git a/docs/polyphony.md b/docs/polyphony.md index 2599175..2f526e2 100644 --- a/docs/polyphony.md +++ b/docs/polyphony.md @@ -30,7 +30,26 @@ pool, in priority order: A note-off marks its voice free for reuse; it does not silence it (the mesh keeps ringing and decays naturally, so a released note still sounds until it decays). Stealing is bounded and deterministic: the active-voice count never exceeds -`NVOICES`, and the pool never diverges. +`NVOICES`, and the pool never diverges. In the playable `MUSICAL_VOICES` mode, +retrigger/steal resets the selected mesh instead of inheriting the previous +resonator state, with a 32-frame output crossfade from the old pickup value to +avoid a hard discontinuity. The fade interpolation is now time-multiplexed +through one shared narrow DSP multiplier for the whole voice pool; at four +voices it completes in nine 100 MHz clocks, rather than dedicating four +left/right multiplier pairs to every voice. + +Musical voices additionally enable RTL-only physical-model refinements: + +- **velocity/exciter-dependent strike shape**: auto/point/soft-mallet/pluck/rim/scrape-burst modes use the existing oversample substeps rather than another audio engine; +- **sub-grid geometry**: strike force is bilinearly distributed and left/right pickups are bilinearly interpolated at quarter-cell offsets, increasing positional resolution without increasing `NX*NY`; +- **anisotropy**: a signed macro applies a shift/add X-vs-Y Laplacian bias, splitting otherwise symmetric modes without another coefficient multiplier; +- **bending stiffness / plate dispersion**: an 8-bit STIFFNESS macro drives the 13-point biharmonic operator; it is latched per voice and its `mu2*Biharm` scale is shift/add so the mesh still uses 18 DSPs; +- **physical mallet**: an 8-bit HARDNESS macro is latched per voice; nonzero HARDNESS with AUTO/MALLET CHARACTER runs a stateful hammer that reads the actual strike-point surface, reacts to contact force, and continues across frames after the one-shot note trigger. The contact curve is shift/add and consumes 0 DSPs; +- **MATERIAL macro**: neutral/membrane/wood/metal/glass coordinate anisotropy bias, high-frequency loss, nonlinearity and default exciter character; +- **micro-variation**: a deterministic LFSR adds ±3.125% strike variation and moves each stereo pickup by at most one grid node on a new strike; +- **frequency-dependent loss**: a Laplacian-of-velocity term damps high spatial modes faster than low modes, with MATERIAL selecting the loss strength. + +These are preset/register features only: no ADC channels or PCB signals are added. `musical_refine_tb` drives nonzero material, anisotropy, fractional geometry and explicit scrape excitation; `stiffness_tb` drives nonzero bending stiffness against an independent fixed-point golden; `mallet_tb` does the same for the stateful physical mallet and requires spatial/TDM contact-driven responses to remain bit-identical. ## Mixing @@ -55,8 +74,9 @@ Fully-spatial polyphony is hopeless on the target board even for one voice, for the same O(N^2) reason a single spatial mesh is (issue #24). The DSP cost is the binding resource. -**Time-multiplexing is what makes polyphony fit.** With `TIME_MUX = true` each -voice folds its mesh through one shared PE (~18 DSP), independent of grid size: +**Time-multiplexing is what makes polyphony fit.** The table below records the older ~18-DSP/voice planning model. The current full physical-model 8x8 `grid_mesh_tdm` maps to **18 DSP** in the open-source XC7 flow, including runtime STIFFNESS/plate dispersion, HARDNESS/stateful contact, MATERIAL/anisotropy, HF loss and fractional strike/pickup geometry; see `resource_budget.md`. Four grids therefore use 72 DSP before mixer/front-end/FX glue. Full-top Vivado utilization remains the authoritative board number. + +Historical planning table: | Voices | TIME_MUX DSP (~18/voice) | Fits A7-35T (90)? | Fits A7-100T (240)? | | --- | --- | --- | --- | @@ -65,19 +85,19 @@ voice folds its mesh through one shared PE (~18 DSP), independent of grid size: | 8 | ~144 | no (35T) / yes (100T) | yes | | 12 | ~216 | no | yes | -So an A7-35T comfortably runs ~4 voices and an A7-100T ~12, at 8x8 (a further PE -pool per voice, issue #24, trades DSP for cycles and can go larger). +Those rows are retained as pre-FX historical planning data. The current custom board target is the XC7A50T. Each fully refined 8x8 time-mux surface voice, including runtime STIFFNESS and HARDNESS, maps to **18 DSPs**, so four voice meshes account for 72 DSPs before the shared fade/front-end/FX logic. The current four-voice `synth_top` maps to **116 / 120 DSPs (96.7%)** in the open-source XC7 flow; the separate PLAY/EDIT panel controller adds one standalone DSP, for an approximate board-level planning total of **117 / 120**. That margin is intentionally treated as provisional until Vivado place/route. ### The cycle budget is the other limit Each voice sweeps its mesh every oversampled step. Per audio frame there are -~2083 cycles at 100 MHz / 48 kHz ([`timing_budget.md`](timing_budget.md)). A -`TIME_MUX` voice at NX*NY = 64 nodes, OS = 4 costs ~`OS * NX*NY` = ~256 -cycles/frame per voice if the voices run **sequentially** through one pool; run -them on **parallel** PE pools (one per voice) and they overlap. The as-built -`poly_voices` gives each voice its own resonator, so voices run concurrently and -the per-frame cost is one voice's sweep regardless of `NVOICES` (area, not time, -scales) - the same trade the single mesh makes. +~2083 cycles at 100 MHz / 48 kHz ([`timing_budget.md`](timing_budget.md)). For +the 8x8/OS=4 production configuration, STIFFNESS=0 retains the legacy ~264 +mesh clocks/frame. Nonzero STIFFNESS activates four two-tap gather states per +node for the 13-point plate stencil: `stiffness_tb` measures **322 clocks per +mesh step**, or 1288 mesh clocks at OS=4 before the small resonator handshake +overhead. The as-built `poly_voices` gives each voice its own resonator, so +voices run concurrently and the per-frame cost is one voice's sweep regardless +of `NVOICES` (area, not time, scales). ## Configurability diff --git a/docs/presets.md b/docs/presets.md index a80b6c2..b0ffe52 100644 --- a/docs/presets.md +++ b/docs/presets.md @@ -8,20 +8,61 @@ register bus (a superset of [`control_bus`](../src/rtl/control_bus.vhd)). ## Preset format (register layout) -Each preset is 10 words of 24 bits (coefficients are Q1.23): +Each preset is 16 words of 24 bits (mesh coefficients are Q1.23): | Addr | Field | Meaning | | --- | --- | --- | -| 0 | `gamma2` | `gamma0^2 = (c*k/h)^2`: pitch / tension | +| 0 | `gamma2` | legacy raw coefficient; in `synth_top` musical mode this is normalized **TENSION** (`0.25` = unity) | | 1 | `a0` | `1/(1+sigma*k)`: forward damping scale | | 2 | `sigk1` | `1 - sigma*k`: backward damping (decay time) | | 3 | `alpha` | chaos coupling: timbre (amplitude stiffening) | | 4 | `gamma2_max` | CFL-safe clamp ceiling (< 1/2) | -| 5..8 | `pick_lx/ly/rx/ry` | stereo pickup tap coordinates | -| 9 | `boundary` | bit 0: 0 = fixed (Dirichlet), 1 = free (Neumann) | - -This is the `control_bus` map (0..8) plus the boundary bit (9). The live -registers drive the mesh continuously and are sampled when it strobes. +| 5 | `pick_lx` + `RIM` + `STIFFNESS` | low coordinate bits = left pickup X; bits 15..8 = RIM compliance; bits 23..16 = STIFFNESS | +| 6 | `pick_ly` + `STRIKE_SIZE` + `HARDNESS` | low coordinate bits = left pickup Y; bits 15..8 = strike footprint size; bits 23..16 = physical mallet HARDNESS | +| 7 | `pick_rx` + `STRIKE_X` | low coordinate bits = right pickup X; bits 15..8 = full strike-X control | +| 8 | `pick_ry` + `STRIKE_Y` | low coordinate bits = right pickup Y; bits 15..8 = full strike-Y control | +| 9 | `physical_ctrl` | bit 0 legacy boundary; bits 3..1 MATERIAL; 6..4 CHARACTER/EXCITER; 10..7 signed ANISO; 12..11 source mode; 16..15 L pickup X frac; 18..17 L pickup Y frac; 20..19 R pickup X frac; 22..21 R pickup Y frac; remaining bits reserved | +| 10 | `fx_ctrl0` | bit 23 master; bits 22..18 drive/tone/chorus/delay/reverb enables; drive + tone amounts | +| 11 | `fx_ctrl1` | chorus rate / depth / mix (8 bits each) | +| 12 | `fx_ctrl2` | delay timing + mix: legacy raw samples when bit 23=0; tempo-grid encoding when bit 23=1 | +| 13 | `fx_ctrl3` | delay feedback / damping / ping-pong flag / `POLISH` macro in bits 6..0 | +| 14 | `fx_ctrl4` | FDN reverb decay / damping / mix | +| 15 | `fx_ctrl5` | FDN size / diffusion / output trim | + +Addresses 0..9 retain the mesh/pickup map; register 9 extends its original boundary bit using previously-unused bits, so old bundles with only bit 0 set remain compatible. Addresses 10..15 are stored in the +same factory/user bundles and feed the post-mesh `fx_chain`. `fx_ctrl3(6..0)` +uses bits that were previously unused, so the new mastering stage requires no +new register, panel control, or PCB signal. `POLISH=0` is an exact bypass; +factory/reset musical presets use `POLISH=64` as a medium finished-output curve. + +### Physical-model control encoding + +Register 9 keeps boundary mode in bit 0 and uses previously-unused bits for MATERIAL, CHARACTER/EXCITER, ANISO, MIDI/CV source override, and fractional pickup offsets. Registers 5..8 reuse upper bytes for physical controls: register 5 bits 15..8 hold RIM and bits 23..16 hold STIFFNESS; register 6 bits 15..8 holds STRIKE SIZE and bits 23..16 hold HARDNESS; registers 7..8 bits 15..8 hold STRIKE X/Y. This preserves the 16-word preset format and keeps every pre-#86/#87 bundle at `STIFFNESS=0` and `HARDNESS=0`. + +`MATERIAL` codes coordinate several physical parameters rather than acting like another post effect: `0=neutral/current`, `1=membrane`, `2=wood`, `3=metal`, `4=glass` (`5..7` currently reserved). They bias anisotropy, high-frequency loss, nonlinearity and the default exciter. Musical factory Drum uses membrane; Gong and Metallic Plate use metal. + +`CHARACTER/EXCITER=0` lets MATERIAL/velocity choose the strike behavior. Explicit codes are `1=point`, `2=soft/broad mallet`, `3=pluck/bipolar`, `4=rim/hard`, `5=scrape/bow-burst`; panel CHARACTER saturates above 5. **HARDNESS** is an unsigned byte for the stateful physical mallet. `HARDNESS=0` is an exact legacy-envelope bypass; nonzero HARDNESS activates the bidirectional mallet when CHARACTER is AUTO or MALLET. Velocity initializes hammer momentum independently of HARDNESS. ANISO is signed 4-bit (`-8..+7`). RIM continuously blends edge reflection from fixed toward compliant/free in 1/16-scale shift/add steps. **STIFFNESS** is an unsigned byte with production mapping `mu2 = STIFFNESS / 4096`; zero is the exact legacy membrane path and 255 approaches the pure-plate stability limit. The runtime wave-speed clamp is tightened to `gamma2 <= min(gamma2_max, 0.5 - STIFFNESS/512)`, implementing `(g2x+g2y)+16*mu2 <= 1`. STRIKE SIZE has four contact-footprint bands: fractional point, compact cross, 3x3 weighted contact, and a wider 13-node contact. STRIKE X/Y encode the complete integer+quarter-cell contact position. + +Source mode in register 9 bits 12..11 is `00=AUTO`, `01=force MIDI`, `10=force CV`, `11=AUTO`. In AUTO, the newest MIDI note-on or CV gate rising edge claims the performance source and stays selected until the other source produces a new note event. The old external `cv_sel` input remains only as a force-CV/debug compatibility override; the board switch no longer drives it. + +### Delay timing encoding + +Register 12 keeps the old raw-sample format whenever bit 23 is clear, so all +existing presets remain compatible: bits 23..8 are delay samples and bits 7..0 +are wet/dry mix. When bit 23 is set, no new register or panel control is needed: +bits 22..16 encode `BPM-60` (60..187 BPM), bits 15..13 select a musical +division, and bits 7..0 remain wet/dry mix. Division codes are 1/16, 1/8, +dotted 1/8, 1/4, dotted 1/4, 1/2, 1/8-triplet, and 1/4-triplet. Times longer +than the physical 500 ms delay RAM are safely clamped. The conversion is an +elaboration-built ROM, not a runtime divider. + +FX parameters are now slewed at the 48 kHz sample rate after initial activation. +Effect enable bits fade their amount/mix toward neutral instead of hard-switching; +the global FX master takes 128 samples (~2.7 ms at 48 kHz) to crossfade against +the latched dry path before returning to exact bit-for-bit bypass. Delay-time +edits move by one RAM tap per audio frame, avoiding large read-pointer jumps. +Preset recall therefore needs no additional PCB or panel hardware to avoid +zipper/click artifacts. ## Storing and recalling @@ -45,25 +86,38 @@ individual registers, then save into a user slot. ## Factory presets -Three are included ([`preset_bank.vhd`](../src/rtl/preset_bank.vhd)); they differ -in pitch (`gamma2`), decay (`sigk1`/`a0`), timbre (`alpha`), taps, and boundary, -so recalling them audibly changes the instrument: - -| # | Name | `gamma2` | `alpha` | Decay | Boundary | Character | -| --- | --- | --- | --- | --- | --- | --- | -| 0 | Drum | 0.180 | 0.10 | short (`sigk1` 0.995) | fixed | membrane, quick decay, mild non-linearity | -| 1 | Gong | 0.300 | 0.40 | very long (`sigk1` 0.99999) | free | big, shimmering, strongly non-linear | -| 2 | Metallic plate | 0.400 | 0.30 | long (`sigk1` 0.9998) | free | bright, stiff, sustained metallic | - -The damping pairs are consistent (`a0 = 1/(1+x)`, `sigk1 = 1-x`, `x = sigma*k`), -and every `gamma2` stays below `gamma2_max = 0.451` so the base scheme is -CFL-stable; the clamp keeps it stable under the non-linear term at any amplitude. +`preset_bank` retains its legacy coefficient presets when `MUSICAL_MODE=false`. +The playable `synth_top` enables `MUSICAL_MODE=true`, where register 0 is a +normalized TENSION macro and damping is calculated for the actual `FS_HZ*OS` +mesh-step rate. Current musical factory starting points are: + +| # | Name | TENSION | CHAOS | Damping `sigma` | Boundary | Pickup character | +| --- | --- | ---: | ---: | ---: | --- | --- | +| 0 | Drum | 0.25 | 0.00 | 18 | fixed | symmetric membrane pickup | +| 1 | Gong | 0.25 | 0.00 | 2 | free | wide off-centre stereo pickup | +| 2 | Metallic plate | 0.25 | 0.02 | 5 | fixed | interior stereo pickup | + +Pitch itself comes from the calibrated MIDI/CV note table; TENSION then retunes +that note. This prevents a preset from silently replacing musical pitch with an +arbitrary raw Courant coefficient. `gamma2_max` remains 0.451 as the base +ceiling; nonzero STIFFNESS automatically reduces the effective per-node ceiling +with the combined stiff-surface CFL bound. Current factory presets retain both +STIFFNESS=0 and HARDNESS=0 for backward compatibility until the MATERIAL edit +page authors explicit stiff-surface / physical-mallet factory voices. + +The pickup coordinates, boundary state, STIFFNESS, and HARDNESS are **live in the playable path**. +They are latched into a voice at strike time along with its coefficients, so +changing a preset affects newly struck voices without mutating a tail already +ringing. Free-boundary musical voices use a balanced two-point strike to avoid +exciting the free membrane's DC translation mode. ## Authoring a preset -Author from physical units with the MATLAB/Octave helper -[`model/preset_gen.m`](../model/preset_gen.m), which computes the Q1.23 register -words from wave speed, damping, chaos coupling, and tap positions: +The MATLAB/Octave helper [`model/preset_gen.m`](../model/preset_gen.m) still +authors **legacy/raw-coefficient** bundles. For the playable musical mode, keep +register 0 as normalized TENSION (0.25 unity) and author damping/CHAOS/taps in +the musical preset table or through the live register interface. The helper is +still useful for explicit raw-coefficient experiments: ```sh octave-cli --eval "preset_gen('name','gong','c',245,'sigma',0.05,'alpha',0.40,'free',true)" @@ -77,15 +131,18 @@ exceeded (reduce `c` or increase `h`). ## Verification [`src/tb/preset_bank_tb.vhd`](../src/tb/preset_bank_tb.vhd) checks that reset -gives the linear default, each factory preset recalls its full bundle and the -three are mutually distinct, a user slot survives an edit / save / clobber / -recall round-trip bit-for-bit, factory slots are read-only, and the read-back -port returns the live registers. All pass under GHDL. - -## Note on boundary mode - -The boundary bit is carried in the preset and exposed as `free_boundary` for -observability, but the mesh's boundary is still a build-time generic -(`FREE_BOUNDARY`) today, so recalling the boundary bit is advisory until a -runtime-selectable boundary lands. The coefficient, tap, and timbre fields are -fully live. +gives the linear default with STIFFNESS=0 and HARDNESS=0, each factory preset recalls its full +bundle, a user slot survives an edit / save / clobber / recall round-trip +including both physical-control bytes, factory slots are read-only, and the read-back +port returns the live registers. [`src/tb/stiffness_tb.vhd`](../src/tb/stiffness_tb.vhd) +verifies STIFFNESS reaches the plate operator; [`src/tb/mallet_tb.vhd`](../src/tb/mallet_tb.vhd) +verifies the HARDNESS/contact model, and `musical_controls_tb` proves both controls +reach decoded I2S audio. All pass under GHDL. + +## Runtime pickup and boundary mode + +Preset tap coordinates and the boundary bit are connected through `synth_top` +to both the spatial and time-multiplexed mesh implementations. +`runtime_mesh_tb` switches them at runtime and requires the two backends to stay +bit-exact. `musical_controls_tb` additionally verifies that changing pickup and +boundary settings changes the decoded I2S audio rather than only a register. diff --git a/docs/resource_budget.md b/docs/resource_budget.md index c1fcba1..ab4d5f9 100644 --- a/docs/resource_budget.md +++ b/docs/resource_budget.md @@ -2,9 +2,11 @@ Synthesis resource budget for the fully-spatial mesh and the case for time-multiplexing (README §3 "Parallel vs. time-multiplexed", §6 target board). -Numbers below are from the open-source yosys `synth_xilinx -family xc7` flow -([`syn/yosys/report_util.sh`](../syn/yosys/report_util.sh)); reproduce sign-off -numbers with Vivado ([`syn/vivado/`](../syn/vivado/)). +Numbers below use the open-source Yosys `synth_xilinx -family xc7` flow. The +historical tables came from [`syn/yosys/report_util.sh`](../syn/yosys/report_util.sh); +post-#86 snapshots explicitly use GHDL 6.0 built-in VHDL->Verilog synthesis into +Yosys 0.68. Reproduce physical sign-off numbers with Vivado +([`syn/vivado/`](../syn/vivado/)). ## Per-node cost (measured) @@ -13,17 +15,27 @@ One `node_element` (the 4-stage non-linear Q1.23 PE) maps to: | Primitive | Count | | --- | --- | | DSP48E1 | **18** | -| Flip-flops (FDRE) | 412 | -| LUTs (LUT2..6) | 702 | -| CARRY4 | 157 | +| Flip-flops (FDRE) | 480 | +| LUTs (LUT1..6) | 1,911 | +| CARRY4 | 391 | The mesh scales linearly: `grid_mesh` at `NX*NY` nodes uses `NX*NY` PEs plus -negligible glue. Measured 8x8 `grid_mesh` (64 nodes): 1152 DSP, 26.4k FF, -45.0k LUT - i.e. exactly 64 x the per-node cost. The full `top_resonator` +negligible glue. At 8x8 (64 nodes), the current refined standalone-PE mapping implies +1152 DSP, ~30.7k FF and ~122.3k LUT before wrapper glue. (A zero-control/legacy build can trim much of the physical-control mux logic, but the fully dynamic figure is the conservative one.) The full `top_resonator` (I2S + CDC + control bus + decimation around an 8x8 OS=4 mesh) adds **no extra DSP** (the `1/OS` decimation average folds to a shift) and only ~600 FF / ~500 LUT of I/O and control glue. +### Refined musical physical model + +The playable `MUSICAL_VOICES` path now combines curvature/velocity loss with runtime MATERIAL, signed X/Y anisotropy, **STIFFNESS / plate dispersion**, **HARDNESS / stateful physical-mallet contact**, explicit exciter modes, and quarter-cell strike/pickup geometry. The legacy/reference zero-control path remains bit-exact. Directional bias, fractional interpolation, the `mu2*Biharm` stiffness scale, and the mallet contact law are shift/add logic; the fundamental DSP multiplier count is unchanged. + +With the runtime physical controls present, standalone XC7 mapping of the current `node_element` is **18 DSP / 1,911 LUT1..6 / 480 FF**. STIFFNESS therefore adds wider shift/add/control logic but no additional DSP multiplier at the PE level. + +For the actual 8x8 time-multiplexed mesh after #86, current GHDL 6 built-in synthesis -> Yosys 0.68 XC7 mapping is **18 DSP, 28,575 LUT1..6, 3,615 FF**. This includes the 27-bit per-node curvature history, runtime STIFFNESS/MATERIAL/ANISO, compliant RIM, full-grid quarter-cell STRIKE X/Y, four strike-footprint bands, and fractional stereo pickups. The open-source LUT estimate rises because the wider stencil exposes more multi-read state muxing; the four TDM gather states deliberately limit the extra concurrent plate reads to two per clock. + +As a DSP planning bound for the XC7A50T, four such TDM grids account for 72 DSP and the current FX chain accounts for 23, leaving 25 of the device's 120 DSPs for the polyphonic mixer/front-end/glue. The complete four-voice `TIME_MUX=true` `synth_top` synthesizes successfully through GHDL; final LUT packing and timing still require the Vivado A50T implementation because the open-source flow pessimistically expands the TDM memories. + ### Why 18 DSP per node The PE has five Q1.23 multiplies (`u^2`, `alpha*u^2`, `gamma2_local*lap`, @@ -61,28 +73,29 @@ the largest Artix-7 (XC7A200T, 740 DSP) only reaches ~6x6. This is exactly the At the 2x2 fit on the 35T: 72/90 DSP (80%), 2.8k/20.8k LUT (13%), 1.6k/41.6k FF (4%) - comfortably DSP-bound. -## Time-multiplexed: the way to a real mesh +## Time-multiplexed: the production architecture -Folding the grid through a pool of `P` shared PEs makes the cost **independent -of mesh size**: `18 * P` DSPs. The grid is swept through the pool in -`ceil(NX*NY / P)` passes per oversampled step, which fits the per-frame cycle -budget (~2083 clocks at 100 MHz / 48 kHz; see -[`timing_budget.md`](timing_budget.md)). +The current `grid_mesh_tdm` folds an entire voice through one shared arithmetic +path, so its DSP count is **18 independent of grid size**. Grid size instead +consumes state storage/read muxing and cycle budget. -| Pool P | DSP (18*P) | Fits 35T? | Sweep for 32x32 (1024 nodes) | -| --- | --- | --- | --- | -| 4 | 72 | yes | 256 passes / step | -| 8 | 144 | no (35T) / yes (100T) | 128 passes / step | -| 16 | 288 | 100T only | 64 passes / step | +At STIFFNESS=0 the 8x8 raster keeps the legacy one-node-per-clock update. For a +stiff surface, the 13-point operator needs eight additional taps; four gather +states read two taps per clock before each node update rather than creating eight +additional simultaneous state-memory read ports. `stiffness_tb` measures +**322 clocks per 8x8 mesh step** when STIFFNESS is nonzero. At OS=4 that is 1288 +mesh clocks/frame before small sequencer overhead, still below the ~2083 clocks +available at 100 MHz / 48 kHz. -A `P=4` pool fits the cheap A7-35T and can sweep a 32x32 mesh at OS=4 in roughly -`4 * 256 * (pipeline) ~ 1024` clocks/frame, well under the 2083-clock budget. -So **time-multiplexing trades latency headroom for the O(N^2) area blow-up**, -and is the route to a full-size mesh on a low-cost board. The same RTL builds -either way (`grid_mesh` is parameterisable); the choice is per-target. +Thus time multiplexing still removes the O(N^2) DSP blow-up, but grid size is +not free: larger grids, higher OS, and nonzero stiffness must be checked against +[`timing_budget.md`](timing_budget.md). The fully spatial and TDM backends +remain synthesis-time choices through the same `mesh` wrapper. ## The playable synth (synth_top) vs. part (issue #77) +The Arty tables immediately below are retained as historical planning data. The current custom-board configuration is measured separately after them with the repaired musical path, four refined time-mux voices, complete onboard FX, and the shared crossfade multiplier. + Measured utilisation of the full playable design `synth_top` (MIDI -> polyphony -> I2S, incl. `midi_frontend` / `preset_bank` / `i2s_*` / CDC glue) at the default 8x8 mesh, OS=4, from the yosys flow (flattened, so the counts are @@ -120,13 +133,74 @@ close. The tension is **LUT**, which in yosys binds sooner (~2 voices on the 35T ### Caveat: the LUT figure is yosys-pessimistic for time-mux The LUT count is a conservative upper bound, not the Vivado number. -`grid_mesh_tdm` uses **combinational-read** grid memory, which yosys expands into -LUT mux-trees rather than the LUTRAM/BRAM Vivado infers. Vivado maps that memory -far more compactly (and the registered-read BRAM line-buffer refactor noted in -`grid_mesh_tdm.vhd` removes it from the LUT budget entirely). So **DSP is the -reliable planning limit** (4 / 12 voices); the true LUT usage sits between the -yosys figure and much lower, and should be confirmed on the Vivado flow -(`build_synth.tcl`) before committing to a voice count near the LUT edge. +`grid_mesh_tdm` uses multi-read asynchronous grid state, which GHDL/Yosys expands +into large LUT mux trees instead of the compact distributed-memory structures a +direct Xilinx flow can infer. DSP is therefore the reliable open-source planning +number; LUT/timing must be confirmed by Vivado (`build_synth.tcl`). + +### Physical mallet / HARDNESS (#87) + +The stateful physical mallet was implemented without DSP multipliers because the +four-voice board already has very little DSP headroom. `physical_mallet.vhd` +uses a leading-bit/shift approximation to compression squared and static +shift/add HARDNESS scaling. + +Standalone GHDL 6 -> Yosys 0.68 XC7 mapping: + +| Resource | `physical_mallet` | +| --- | ---: | +| DSP48E1 | **0** | +| LUT1..6 | **1,280** | +| FF (FDRE) | **61** | +| CARRY4 | **173** | + +There is one mallet state machine per voice. It adds no BRAM and does not add a +mesh sweep state: spatial contact reads the current strike-point interpolation, +while TDM captures those four contact corners during the normal raster. The +binding DSP budget is therefore unchanged by HARDNESS. + +### Current custom-board configuration: XC7A50T, four refined voices + +The finished `NVOICES=4`, `NX=NY=8`, `OS=4`, `TIME_MUX=true` `synth_top` was +synthesized through GHDL and mapped with Yosys `synth_xilinx -family xc7` after +all 2026-09-18 refinements: + +| Resource | Current full top | +| --- | ---: | +| DSP48E1 | **116 / 120 (96.7%)** | +| LUT1..6 | **132,279** *(known Yosys overestimate for multi-read TDM memories; wider #86 stencil magnifies it)* | +| FF (FDRE/FDRE_1/FDSE) | **20,547** | +| RAMB36E1 | **28** | +| RAMB18E1 | **6** | + +This `synth_top` figure includes four runtime-STIFFNESS/HARDNESS-capable 18-DSP TDM voices, shared voice-fade path, automatic MIDI/CV arbitration and the complete 23-DSP FX chain. #86/#87 therefore leave the binding DSP count at **116 / 120** and BRAM at 28 RAMB36 + 6 RAMB18. The physical board wrapper also instantiates `panel_ctrl`; its PLAY/EDIT controller maps separately to about **1 DSP**, so board-level DSP planning remains approximately **117 / 120 (97.5%)**, before Vivado optimization/sharing. The open-source LUT number is not a board-fit verdict: the widened 13-point stencil exposes more of the known asynchronous multi-read TDM state as LUT mux trees. **Vivado place/route is mandatory sign-off** given both that pessimism and the small remaining DSP margin. + +## Onboard stereo FX chain (2026-09-18) + +The current post-mesh `fx_chain` includes drive, tone, BRAM chorus, ping-pong +delay, modulated eight-line FDN, sample-rate parameter smoothing / click-free +master crossfade, optional BPM/division delay timing, and the `POLISH` mastering +bus. Legacy raw delay timing remains compatible. The tempo conversion uses two +128x16 elaboration ROMs; no runtime divider is present. + +Current standalone GHDL -> Verilog -> Yosys `synth_xilinx -family xc7` mapping: + +| FX chain resource | Standalone count | +| --- | ---: | +| DSP48E1 | **23** | +| RAMB36E1 | **28** | +| RAMB18E1 | **6** | +| LUTs (LUT2..6) | **12,011** | +| FFs (FDRE+FDSE) | **2,072** | + +BRAM use is unchanged from the earlier chorus/delay/FDN implementation. The +slow FDN line modulation reuses the existing eight memories and the tempo-grid +feature uses small ROMs rather than another audio delay. The refined +`fx_master_bus` alone maps to **1 DSP48E1, 3,141 LUT2..6, 359 FDRE + 1 FDSE, +and no BRAM**; its EQ/width filters are shift-add and one multiplier is shared +between left/right compressor gain operations. + +The complete FX chain remains **23 DSPs**. The current `synth_top`, including runtime bending STIFFNESS and stateful HARDNESS contact, maps to **116/120 DSPs** and the separate PLAY/EDIT `panel_ctrl` maps to **1 DSP**, giving an approximately **117/120** board-level planning total. **Vivado place/route remains the hardware sign-off** because the margin is small and GHDL/Yosys expands the multi-read TDM grid memories pessimistically. No PCB, clock, ADC, connector, pot, or panel signal was added. ## Reproducing diff --git a/docs/sound_engine_repair.md b/docs/sound_engine_repair.md new file mode 100644 index 0000000..d81caa4 --- /dev/null +++ b/docs/sound_engine_repair.md @@ -0,0 +1,27 @@ +# RADIAN sound-engine repair — 2026-09-16 + +The playable RTL was repaired after the first listening demos exposed uncalibrated pitch and excessive high-frequency/non-linear output. + +## Implemented +- Discrete-mesh pitch calibration for NX/NY, OS, sample rate, and fixed/free boundary mode. +- MIDI velocity controls strike only by default; CHAOS is independent. +- Musical strike gain reduced from 0.9 to 0.002; output level is restored after the resonator instead of clipping cells. +- TENSION is a normalized multiplier (0.25 unity, approximately ±1 octave panel range). +- Rate-aware DECAY mapping and a one-LSB decay-pot change threshold. +- Preset pickup coordinates and boundary mode now reach the active voice path. +- Balanced excitation for free-boundary musical voices to avoid the DC translation mode. +- Voice retrigger/steal resets the selected mesh with a 32-frame output crossfade. +- 20 Hz DC blocker and bounded output gain before I2S CDC. +- Spatial and TDM meshes support the same runtime pickup/boundary controls. + +## Acceptance +- Published repo: **28/28** NVC RTL testbenches pass. +- Fixed/free spectral probes at MIDI 45/57/69/81: maximum measured pitch error **0.89 cents**. +- Instrumented musical probes, including max CHAOS, complete without internal Q1.23 cell-clipping assertions. +- GHDL synthesis of the published 4-voice 8x8 OS4 TIME_MUX `synth_top` succeeds; current Verilator build has no warnings. +- Native NVC and GHDL→Verilator captures match sample-for-sample for both fixed and free validation cases (12,000 stereo frames each). +- Four-second full MIDI→polyphony→CDC→I2S phrase: 3 active voices max, 99.919% spectral power below 2 kHz, 0.000012% above 5 kHz. + +Raw metrics and commands are preserved under `/home/ik/ChatGPT/RADIAN_Sound_Repair_20260916T042905Z`. A pre-apply rollback archive is `/home/ik/ChatGPT/RADIAN_Sound_Repair_20260916T042905Z/repo_before_sound_repair.tar.gz`. + +This validates simulation/synthesis behavior, not physical FPGA timing closure or analog hardware sound. diff --git a/docs/synth_top.md b/docs/synth_top.md index dd707ff..8257874 100644 --- a/docs/synth_top.md +++ b/docs/synth_top.md @@ -8,41 +8,45 @@ master. It is the design a board would flash. RTL: ## Datapath ``` - midi_rx --2FF sync--> midi_frontend --> note events + per-note coeffs + exc + midi_rx --2FF sync--> midi_frontend --> calibrated note gamma2 + strike \ | - preset_index/recall --> preset_bank --> base coeffs (a0/sigk1/gamma2_max) + preset_index/recall --> preset_bank --> TENSION/DECAY/CHAOS + taps/boundary | - merge (note pitch/timbre + preset body) = coeffs + merge + musical scaling = voice coeffs v poly_voices (NVOICES independent meshes + averaging mix) --> L/R v + DC/gain -> drive -> tone -> chorus -> delay -> 8-line FDN + -> POLISH EQ/width/compressor/limiter + v pickup cdc_word (system -> audio clock) --> tx_l/tx_r v i2s_transceiver TX --> sd_tx --> codec DAC ``` -- **midi_frontend** (#28) parses the serial MIDI and maps note -> `gamma2` - (pitch), velocity -> `alpha` (timbre) + strike amplitude, and emits the - note-on/off events plus a one-frame excitation. -- **cv_frontend** (#70) runs in parallel and produces the *same* note-mapping - interface from control voltage (1V/oct pitch, gate, mod CV). A runtime - `cv_sel` mux picks which source (MIDI or CV) drives the voices, so the same - design plays from either. CV inputs default off, so a MIDI-only instantiation - is unaffected. -- **preset_bank** (#30) supplies the instrument "body": `a0`/`sigk1` (decay) and - `gamma2_max` (CFL clamp), recalled/saved via `preset_index`/`recall`/`save` - and editable through the `cfg_*` register port. -- **coefficient merge**: the voice coefficients take pitch (`gamma2`) and timbre - (`alpha`) from the note and the body (`a0`, `sigk1`, `gamma2_max`) from the - preset. So a preset picks the instrument and notes play it. -- **poly_voices** (#29) allocates voices, latches each note's coefficients + - excitation into its voice, runs `NVOICES` independent meshes, and averages - their stereo pickups. `TIME_MUX` (#24) is forwarded so voices can fold onto a - shared PE for area (the only way polyphony fits a small device). -- **i2s_transceiver** streams the mixed stereo to the DAC. +- **midi_frontend** (#28) parses serial MIDI, maps notes through the discrete-mesh pitch table, and maps velocity to strike amplitude. MIDI velocity no longer changes CHAOS by default. +- **cv_frontend** (#70) runs in parallel and produces the same note-mapping interface from control voltage (1V/oct pitch, gate, mod CV). MIDI/CV selection is normally automatic: the newest MIDI note-on or CV gate rising edge claims the source. Register 9 can force MIDI or CV for a preset/debug setup; the legacy `cv_sel` input remains a force-CV compatibility override rather than a panel control. +- **preset_bank** (#30/#86/#87) supplies TENSION, DECAY, CHAOS, `gamma2_max`, STIFFNESS, physical-mallet HARDNESS, stereo pickup geometry, MATERIAL/ANISO/CHARACTER, RIM compliance, STRIKE SIZE/X/Y, source override, runtime boundary mode, and the six stored FX words; recall/save/edit still use the same 4-bit/24-bit register interface. +- **musical merge**: calibrated note pitch is multiplied by normalized TENSION (0.25 = unity); CHAOS is independent of MIDI velocity and scaled with tuned pitch; DECAY and the base CFL ceiling come from the preset. STIFFNESS maps to `mu2=control/4096`, adds the 13-point biharmonic plate term, and automatically tightens the effective wave-speed ceiling with `(g2x+g2y)+16*mu2<=1`. HARDNESS independently controls the stateful physical-mallet contact law while MIDI/CV velocity initializes hammer momentum. MATERIAL can further bias CHAOS/nonlinearity and default CHARACTER. Pickup positions, fractional offsets, boundary mode, anisotropy, material, exciter type, stiffness and hardness are latched into each newly struck voice. +- **poly_voices** (#29) allocates independent resonators and averages their stereo pickups. Musical voices latch the complete surface/exciter state on a strike: STIFFNESS, HARDNESS, RIM, STRIKE SIZE/X/Y, MATERIAL, CHARACTER, ANISO and pickup geometry. Strike position is full-grid plus quarter-cell resolution; STRIKE SIZE expands from a point/sub-grid contact through compact 3x3 and wide 13-node footprints. RIM continuously changes boundary compliance. These refinements are implemented identically in spatial and TDM backends. `TIME_MUX` remains the area-saving implementation. +- **output conditioning + FX** removes DC with a 20 Hz one-pole high-pass and restores level, then `fx_chain` applies drive, tilt tone, BRAM chorus, stereo/ping-pong delay and an eight-line damped FDN reverb. Numeric FX controls slew at audio rate, effect enables fade toward neutral, and the global master crossfades to/from a latched dry sample. Delay keeps legacy sample timing but can alternatively decode BPM + musical division from register 12. The FDN slowly modulates each line by a few samples to break up static metallic modes without another RAM. `fx_master_bus` then adds the `POLISH` macro: ~30 Hz subsonic cleanup, a production-style low-shelf/low-mid/presence curve, low-frequency stereo centering with upper-band widening, a dual-timescale linked compressor with continuous gain law/program-dependent release, and soft limiting. `POLISH=0` is an exact mastering-stage bypass. **i2s_transceiver** then streams the post-FX stereo to the DAC. Output-only voice: the codec ADC input is unused (`sd_rx` tied off). + +## Onboard FX chain + +The effects run in the 100 MHz system domain on the 48 kHz sample-valid pulse; +there is no extra audio clock domain. Chorus and delay use explicit single-port +RAM read/wait/write schedules, and their wet memories are Q1.15 to save BRAM +while the dry path stays Q1.23. The FDN likewise stores Q1.15 state in eight +prime-ish delay lines and uses a shift-normalized Hadamard feedback matrix. A +slow per-line ±few-sample modulation is derived from a shared phase accumulator +and diffusion setting, reducing static comb/metallic character with no extra +wet RAM. `src/tb/fx_chain_tb.vhd` checks exact settled master bypass, gradual +parameter slew, master crossfade, raw and tempo-grid delay timing, drive shaping, +a non-zero FDN tail, and POLISH makeup/reshaping. + ## Clocking Two clock domains: @@ -74,24 +78,18 @@ constrains these crossings (async clock group + bus skew). ## Configuration -Generics: `NVOICES`, `NX`/`NY`/`OS`/`FREE_BOUNDARY`/`TIME_MUX` (the mesh/voice -config, forwarded to `poly_voices`), `CLK_HZ`/`BAUD` (MIDI UART), and -`MCLK_TO_BCLK`/`BCLK_TO_LRCK` (I2S clock division). For a real board build set +Generics: `NVOICES`, `NX`/`NY`/`OS`/`FREE_BOUNDARY`/`TIME_MUX`, `FS_HZ` (used by pitch/damping calibration), `OUTPUT_GAIN_SHIFT`, `CLK_HZ`/`BAUD`, and `MCLK_TO_BCLK`/`BCLK_TO_LRCK`. For a real board build set `TIME_MUX = true` so `NVOICES` voices fit (see `docs/polyphony.md`). ## Verification [`src/tb/synth_top_tb.vhd`](../src/tb/synth_top_tb.vhd) drives a real serial MIDI stream in and decodes the I2S output with a loopback codec (a second -`i2s_transceiver` sampling `sd_tx` off the generated clocks). It recalls the -gong preset, then plays notes and checks: a note allocates a voice (`active` -fills), the codec recovers non-zero stereo audio (the voice sounds), a second -held note adds a second voice, and the output never leaves Q1.23 (no -divergence). Passes under GHDL: +`i2s_transceiver` sampling `sd_tx` off the generated clocks). It recalls the gong preset, then checks MIDI allocation/audio, automatic CV claiming from a gate edge with the legacy `cv_sel` override left inactive, a later MIDI note reclaiming AUTO source, polyphony, and bounded I2S output. Current GHDL run: ``` -synth_top_tb: voice sounded, peak |out| = 191121 -synth_top_tb: CV voice sounded, peak |out| = 276330 +synth_top_tb: voice sounded, peak |out| = 1451476 +synth_top_tb: AUTO CV claim sounded, peak |out| = 254016 synth_top_tb: all checks passed (MIDI and CV -> 3-voice polyphony -> I2S audio; voices allocate, sound, bounded) ``` @@ -100,9 +98,12 @@ synth_top_tb: all checks passed (MIDI and CV -> 3-voice polyphony -> I2S audio; On the board, [`syn/vivado/arty_synth.vhd`](../syn/vivado/arty_synth.vhd) wraps `synth_top` with the MMCM clocking (see `syn/README.md`) and adds the front -panel: [`panel_ctrl`](../src/rtl/panel_ctrl.vhd) (#78) drives `synth_top`'s +panel: [`panel_ctrl`](../src/rtl/panel_ctrl.vhd) (#78/#85) drives `synth_top`'s `cfg_*` / `preset_*` control ports from the pots and rotary encoder (see -[`panel.md`](panel.md)), `sw0` selects MIDI vs CV, and the pot/CV analog samples -come from an XADC / external ADC (that ADC block is out of scope; the sample -ports are left for it). So the flashable design is playable from MIDI or CV with -the knobs live. +[`panel.md`](panel.md)). `sw0` is now PLAY/EDIT: in PLAY the encoder navigates +presets and the LEDs show active voices; in EDIT the encoder selects an edit +page, the LEDs show that page one-hot, and the six pots edit that page with soft +takeover. Page 0 is SURFACE; the selector is generic/extensible without a PCB +change. MIDI/CV source claiming remains automatic in `synth_top`. The pot/CV +analog samples come from an XADC / external ADC (that ADC block is out of scope; +the sample ports are left for it). diff --git a/docs/timing_budget.md b/docs/timing_budget.md index 9d1a937..be36a67 100644 --- a/docs/timing_budget.md +++ b/docs/timing_budget.md @@ -36,23 +36,48 @@ So a fully-spatial mesh has enormous headroom: oversampling up to roughly `OS = 2083 / 7 ~= 290` still fits within one sample period. Grid size does not change this number (the nodes update concurrently); it changes area, not time. -### Time-multiplexed mesh (a pool of P PEs) +### Time-multiplexed mesh -If the grid is folded through `P` shared PEs instead, each oversampled step -sweeps `NX*NY` nodes in `ceil(NX*NY / P)` passes, so: +The current `grid_mesh_tdm` implementation serializes the raster through one +shared arithmetic path. With STIFFNESS=0 it keeps the original one-node-per-clock +sweep. Nonzero STIFFNESS needs the diagonal and second axial ring of the +13-point biharmonic stencil, but it does **not** add eight simultaneous memory +read ports: four gather states fetch two extra taps per clock, then the normal +node-update state runs. -``` -cycles / frame ~= OS * ceil(NX*NY / P) * (pipeline-limited per-pass cost) -``` +For the production 8x8 grid: + +| TDM mode | clocks / mesh step | OS=4 mesh clocks / audio frame | +| --- | ---: | ---: | +| STIFFNESS=0 | legacy ~66 | ~264 | +| STIFFNESS>0 | **322 measured** | **1288** | + +`stiffness_tb` pins the 322-clock nonzero-stiffness value. The surrounding +`mesh_resonator` FIRE/WAIT handshake adds only a few clocks per substep, so a +stiff OS=4 voice remains around 1.3k clocks/frame, below the 2,083-clock budget +at 100 MHz / 48 kHz. Voices are separate TDM engines and run in parallel, so +polyphony consumes area rather than multiplying this per-frame latency. + +Larger grids or higher OS must be re-budgeted: nonzero stiffness costs roughly +five raster clocks per node in the current implementation, while membrane mode +retains the legacy one-clock raster path. + +## Post-mesh FX latency -For example a 32x32 = 1024-node mesh at OS=4 through P=16 PEs is on the order of -`4 * 64 * (~4) ~= 1024` cycles, still under the 2083-cycle budget; larger grids -or higher OS trade against `P`. The fully-spatial and time-multiplexed builds -share the same RTL (`grid_mesh` generics), so this is a synthesis-time choice. +The effects are handshake-driven between audio frames, not part of the mesh +oversampling sweep. `fx_master_bus` accepts one post-FDN sample and returns it +after three additional 100 MHz clocks (shared left/right compressor gain plus +output), about **0.14%** of the 2,083-clock frame budget. Parameter smoothing, +master crossfade and FDN modulation update once per 48 kHz sample and do not add +block buffering. The four-voice retrigger/steal mixer now needs only nine system +clocks for its shared fade interpolation, also negligible versus 2,083 clocks +per frame. The musical mesh's legacy velocity/exciter-shaped strike uses the existing oversample substeps, while high-frequency damping and anisotropy are computed during the normal node update. RIM compliance is applied during the ordinary boundary-neighbour fetch. STRIKE SIZE/X/Y only change the per-node forcing comparison/weight during the same raster, and fractional pickup interpolation captures its four corner samples as the raster already visits them. The #87 physical mallet likewise adds **no extra raster state**: its two scalar hammer states advance on the existing mesh strobe, while the actual strike-point contact corners are captured during the normal TDM raster (the spatial backend reads them directly). STIFFNESS is the exception: when nonzero it activates the four two-tap gather states described above for the wider plate stencil; when zero those states are bypassed exactly. +No audio clock, panel, or PCB change is needed. ## Conclusion The single-cycle `frame` strobe plus the `mesh_resonator` sequencer completes -the full oversampled mesh sweep well within one audio sample period for every -practical configuration: fully-spatial leaves >94% of the budget free even at -16x oversampling, and the time-multiplexed fold still fits a 32x32 mesh. +the configured production 8x8/OS=4 mesh within one audio sample period in both +membrane and stiff-surface modes. Fully-spatial leaves large timing headroom; +for TDM, larger grids or higher oversampling must be checked against the formulas +above, especially when STIFFNESS is nonzero. diff --git a/hardware/CURRENT_DESIGN.md b/hardware/CURRENT_DESIGN.md new file mode 100644 index 0000000..5ad6063 --- /dev/null +++ b/hardware/CURRENT_DESIGN.md @@ -0,0 +1,63 @@ +# RADIAN current hardware baseline — 2026-09-18 + +The repaired native KiCad boards are authoritative. Do not regenerate them in-place from legacy routing/export writers. + +## Canonical native files +- Mainboard: `courant/deliverables/courant.kicad_pcb` +- Mainboard project/library: `courant/deliverables/courant.kicad_pro`, `courant/deliverables/fp-lib-table`, `courant/deliverables/RadianMain.pretty/` +- Panel/interface board: `panel/design/radian_panel.kicad_pcb` +- Panel project/schematic: `panel/design/radian_panel.kicad_pro`, `panel/design/radian_panel.kicad_sch` +- Shared board-stack contract: `stack/panel-stack.json` + +## Native validation +- Mainboard Backplane KiCad 10.0.6 DRC: 0 violations, 0 unconnected. +- Panel Backplane KiCad 10.0.6 ERC: 0 violations. +- Panel DRC: 0 violations, 0 unconnected, 0 schematic/PCB parity findings. +- Mainboard has no native `.kicad_sch`, so mainboard ERC/parity cannot be claimed. + +## Mainboard exact-part reconciliation +The canonical mainboard is now reconciled to its production BOM rather than carrying generator-era package aliases. All **180 referenced placements** have Manufacturer and MPN fields and a resolved project-local 3D model. Important identities are explicit: **U1 = AMD/Xilinx XC7A50T-1FTG256I (FTG256)**, **U5 = TI REF3125AIDBZR (SOT-23)**, **Y1/Y2 = Abracon ASE 100 MHz / 12.288 MHz 3225 oscillators**, **L1–L3 = Changjiang FNR4030S1R0MT**, **D10–D12 = Nexperia BAT54S,215**, and **D20 = Diodes Incorporated 1N4148W-7-F**. Service connectors are **J1/J3/J4 = Molex 22-23-2021**, **J2 = Molex 22-23-2061**, while J17/J18 remain Samtec IPT1-110-06-L-D. + +This reconciliation did **not** move copper, vias, footprints, pads, nets, or component orientations. The only intentional native package change is the Molex J1–J4 through-hole drill correction from **1.00 mm to 1.02 mm** plus their actual connector courtyards. `courant/reports/mainboard_exact_parts.json` records the proof. Mainboard DRC remains 0 violations / 0 unconnected, and the exact-part STEP has been rechecked in the product assembly with zero panel↔mainboard clashes and zero unintended enclosure intersections. Molex J1–J4 and Samtec J17/J18 connector solids are drawing-derived reference models; physical first-article fit remains required. + +## Actual-part product CAD +The canonical product assembly is now rendered from **native KiCad-placed component STEP groups**, not the old white envelope/block references. The final assembly is `panel/cad/RADIAN_actual_parts_full_assembly.step`, and `RADIAN_P1_desktop_fit_study.step` / `RADIAN_P1_case_updated.step` are regenerated from the same actual-part assembly. + +Prominent panel hardware now uses real/open or package-accurate CAD: the six **Bourns PTV09A-series** potentiometers use aligned real family geometry trimmed to the selected 20 mm shaft; J301–J305 use the **PJ398SM/Thonkiconn** open mechanical model with knurled nut; SW3/SW4 use the maintained **Omron B3F-1000** package model; D10–D13 use a real 3 mm green LED package model. Wurth/Molex production connectors, standard IC/passive packages, and all reconciled mainboard packages are likewise exported from the component models attached to the native KiCad boards. + +The remaining non-vendor-download solids are explicitly MPN-specific **drawing-derived reference geometry**, not generic boxes: ENC1 Bourns PEC11R-4220F-S0024, SW1 E-Switch 100SP1T1B1M2REH, Samtec J100/J101/J17/J18, and Molex mainboard J1–J4. `stack/actual_parts/actual_parts_report.json` records this distinction. No generic white component-envelope geometry is used in the final actual-part assembly. + +## Front-panel controls and direct stack +The panel has six 10 kOhm macro pots in two rows. **TENSION · DECAY · CHAOS** are the widely spaced primary controls intended for 23 mm knobs at (38,96), (76,96), (114,96) mm; **DRIVE · DELAY · REVERB** are the tighter FX row intended for 14 mm knobs at (66,70), (88,70), (110,70) mm. The PCB uses the same Bourns PTV09A4 rear-facing pot footprint for all six; knob diameter is an enclosure/assembly choice. The push encoder, MODE switch and four LEDs remain. Internal legacy nets POT_PITCH/POT_DECAY/POT_TIMBRE remain unchanged; the three FX controls use POT_DRIVE/POT_DELAY/POT_REVERB. + +The former per-function panel harness architecture is retired. The corresponding legacy mainboard edge headers **J5–J15 have now been physically removed from the canonical PCB**, along with their dead-end copper branches; J1–J4 remain as service/debug access. Two 20-pin direct mezzanine sites now mate panel to mainboard: J17↔J100 (power/analog/CV/audio) and J18↔J101 (digital/MIDI/service). The selected pair is Samtec **IPT1-110-06-L-D** on the mainboard and **IPS1-110-01-L-D** on the panel. The shared contract targets 19.99 mm fully mated / 20.45 mm maximum PCB spacing and a nominal 20.0 mm assembly support spacing. `stack/validate_direct_stack.py` now checks all **40/40 physical contacts** pin-by-pin for native-board XY, pin number, net name, recommended drill size, board side and attached 3D reference model. It also checks the published -06/-01 insertion/wipe geometry and panel solder-tail clearance. All 40 contacts pass. + +## Exact panel-side service / off-board connector parts +The former generic panel utility headers have been replaced by selected production parts without moving their proven copper endpoints: **J200 = Wurth 61201021621** keyed 2×5 Eurorack power header; **J201 = Molex 22-27-2021** 2-circuit friction-lock desktop-power harness connector; **J306 = Molex 22-27-2021** 2-circuit friction-lock isolated-MIDI harness connector; **J202 = Molex 22-27-2061** 6-circuit JTAG service connector; **JP1 = Wurth 450301014042** SPDT mini slide switch. JP1 uses the real switch numbering: pin 1 common = MOD_IN, pin 2 = MOD_BIPOLAR, pin 3 = MOD_RAW. The selected chassis endpoints are **Switchcraft 722A** for 12 V desktop power and **Same Sky SDS-50J** for MIDI; these remain short off-board harness connections because those parts live in the enclosure rather than between the two PCBs. + +## Actual-part CAD assembly +The current product CAD no longer uses the old generic white component envelopes for either PCB. Component placement is exported directly from the native KiCad boards and assembled in `stack/render_actual_part_cad.py`, so the CAD and KiCad placements share one source of truth. + +Prominent panel parts now use real/open or package-accurate geometry: the six Bourns PTV09A-family potentiometers use real PTV09A mechanical CAD aligned to the selected **PTV09A-4020F-B103** footprint and trimmed to the selected 20 mm shaft; J301–J305 use PJ398SM/Thonkiconn mechanical CAD including the knurled-nut assembly; SW3/SW4 use the Omron B3F-1000 package model; D10–D13 use 3 mm green LED package geometry; U1/U2/D4 and all R/C/fuse/SMB parts use maintained package STEP geometry. Selected Wurth/Molex models remain in use. + +The mainboard is likewise imported as KiCad-placed component groups using its exact/package STEP library rather than rendered as one flat white compound. The remaining non-vendor mechanical references are explicit and documented, not generic placeholders: **ENC1 PEC11R-4220F-S0024** and **SW1 100SP1T1B1M2REH** use drawing-derived full mechanical references; the Samtec direct-stack and mainboard Molex service connector solids are also drawing-derived references because vendor STEP files were unavailable. + +Canonical actual-part assembly: +- `panel/cad/RADIAN_actual_parts_full_assembly.step` +- `panel/cad/RADIAN_P1_desktop_fit_study.step` (same current actual-part assembly) +- `panel/cad/RADIAN_direct_stack_mated.step` +- `panel/previews/actual_parts_full_assembly_iso.png` +- `panel/previews/actual_parts_full_assembly_front.png` +- `panel/previews/actual_parts_full_assembly_side.png` + +`stack/actual_parts/actual_part_collision_report.json` is PASS: zero unintended panel↔mainboard collisions and zero rear-guard/desktop-dock collisions. Model-only reconciliation was also checked against the pre-edit native panel geometry: copper, tracks/vias, pad positions/sizes/drills/nets, footprint positions/orientations and board sides are unchanged. + +The final STEP exporter works at **solid level**, not compound-group level, because STEP compound colors were being dropped by the CAD round trip and appearing as viewer-default white. The current full assembly contains **715 colored STEP children, 0 missing colors and 0 near-white default children**. Light cream is used only for the physical natural-nylon Molex connector bodies. U8/H11L1M is separately proven: the standard DIP-6 geometry is translated **(-3.81,+2.54) mm in STEP coordinates**, which under KiCad's Y inversion maps all six lead centers exactly to the native U8 pads; a placed U8 STEP export centers at **(48.000,-139.000) mm**, exactly matching the native footprint center. + +## Current derived files +`hardware/refresh_outputs.py` regenerates current review Gerbers/drills, placement, BOM/netlist metadata, native board copies, 2D views, mechanical PDF/DXF and fabrication ZIPs from the canonical boards. `CURRENT_EXPORTS.json` records source hashes and commands. `NATIVE_BASELINE.json` protects the verified native copper. + +These are electrically/geometry-checked engineering outputs, not a claim of physical production qualification. The remaining gates require real hardware: bench-fit the Samtec stack and ~20 mm support stack, verify connector seating/retention and enclosure tolerance, run power/load/fault/thermal measurements, and complete FPGA implementation/timing on the target device. + +## Enclosure / case CAD +The product enclosure CAD is synchronized with the two-row six-pot/direct-stack revision. The faceplate carries three large-knob primary controls and three smaller-knob FX controls; primary labels sit above the large row and the lower row is marked as a compact FX group. MODE is restored to its original raised insert at (150.5,84.5) mm. The mainboard/support stack remains shifted 0.46 mm toward the panel for the 19.99 mm fully-mated Samtec PCB gap. Current assembly: `panel/cad/RADIAN_P1_desktop_fit_study.step`; validation: `panel/reports/case_direct_stack_update.json`. The Samtec direct-stack connectors use **drawing-derived IPT1/IPS1 20-contact reference models** attached to the native KiCad footprints, while J200/J201/J306/J202/JP1 use the selected Wurth/Molex part geometry in the panel CAD and native KiCad 3D view. Nominal CAD checks report zero control-hole conflicts, zero panel-component/mainboard clashes and zero unintended enclosure intersections. The published rounded REF dimensions produce a 0.01 mm housing-interface closure in the reference solids; insertion and contact wipe are checked independently against Samtec's mated-view dimensions. Physical first-article tolerance and retention remain release gates. diff --git a/hardware/CURRENT_EXPORTS.json b/hardware/CURRENT_EXPORTS.json new file mode 100644 index 0000000..903148e --- /dev/null +++ b/hardware/CURRENT_EXPORTS.json @@ -0,0 +1,230 @@ +{ + "review_only": true, + "results": { + "mainboard": { + "board_sha256": "92e66042479df826fed7b9fa62116f5fa4a31a84fc075922198cf18b91b7c6c5", + "counts": { + "footprints": 199, + "tracks": 2773, + "vias": 346, + "nets": 102 + } + } + }, + "commands": [ + { + "command": [ + "/usr/bin/kicad-cli", + "pcb", + "drc", + "--refill-zones", + "--all-track-errors", + "--severity-all", + "--exit-code-violations", + "--format", + "json", + "-o", + "/home/ik/ChatGPT/Courant/hardware/courant/deliverables/native_checks/drc.json", + "/home/ik/ChatGPT/Courant/hardware/courant/deliverables/courant.kicad_pcb" + ], + "exit_code": 0, + "stdout": "Found 0 violations\nFound 0 unconnected items\nSaved DRC Report to /home/ik/ChatGPT/Courant/hardware/courant/deliverables/native_checks/drc.json\n", + "stderr": "" + }, + { + "command": [ + "/usr/bin/kicad-cli", + "pcb", + "drc", + "--refill-zones", + "--all-track-errors", + "--severity-all", + "--exit-code-violations", + "--format", + "json", + "-o", + "/home/ik/ChatGPT/Courant/hardware/courant/dist/native_checks/drc.json", + "/home/ik/ChatGPT/Courant/hardware/courant/dist/courant.routed.kicad_pcb" + ], + "exit_code": 0, + "stdout": "Found 0 violations\nFound 0 unconnected items\nSaved DRC Report to /home/ik/ChatGPT/Courant/hardware/courant/dist/native_checks/drc.json\n", + "stderr": "" + }, + { + "command": [ + "/usr/bin/kicad-cli", + "pcb", + "drc", + "--refill-zones", + "--all-track-errors", + "--severity-all", + "--exit-code-violations", + "--format", + "report", + "-o", + "/home/ik/ChatGPT/Courant/hardware/courant/dist/courant.drc.rpt", + "/home/ik/ChatGPT/Courant/hardware/courant/dist/courant.routed.kicad_pcb" + ], + "exit_code": 0, + "stdout": "Found 0 violations\nFound 0 unconnected items\nSaved DRC Report to /home/ik/ChatGPT/Courant/hardware/courant/dist/courant.drc.rpt\n", + "stderr": "" + }, + { + "command": [ + "/usr/bin/kicad-cli", + "pcb", + "export", + "gerbers", + "--check-zones", + "--subtract-soldermask", + "--layers", + "F.Cu,In1.Cu,In2.Cu,In3.Cu,In4.Cu,B.Cu,F.Mask,B.Mask,F.Paste,B.Paste,F.Silkscreen,B.Silkscreen,Edge.Cuts", + "-o", + "/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/", + "--no-protel-ext", + "/home/ik/ChatGPT/Courant/hardware/courant/dist/courant.routed.kicad_pcb" + ], + "exit_code": 0, + "stdout": "Plotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-F_Cu.gbr'.\nPlotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-In1_Cu.gbr'.\nPlotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-In2_Cu.gbr'.\nPlotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-In3_Cu.gbr'.\nPlotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-In4_Cu.gbr'.\nPlotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-B_Cu.gbr'.\nPlotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-F_Paste.gbr'.\nPlotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-B_Paste.gbr'.\nPlotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-F_Silkscreen.gbr'.\nPlotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-B_Silkscreen.gbr'.\nPlotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-F_Mask.gbr'.\nPlotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-B_Mask.gbr'.\nPlotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-Edge_Cuts.gbr'.\n", + "stderr": "" + }, + { + "command": [ + "/usr/bin/kicad-cli", + "pcb", + "export", + "drill", + "--format", + "excellon", + "--excellon-units", + "mm", + "--excellon-separate-th", + "--generate-map", + "--map-format", + "pdf", + "-o", + "/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/", + "/home/ik/ChatGPT/Courant/hardware/courant/dist/courant.routed.kicad_pcb" + ], + "exit_code": 0, + "stdout": "Created file '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-PTH.drl'\nCreated file '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-NPTH.drl'\nCreated file '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-PTH-drl_map.pdf'.\nCreated file '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant.routed-NPTH-drl_map.pdf'.\nDone.\n", + "stderr": "" + }, + { + "command": [ + "/usr/bin/kicad-cli", + "pcb", + "export", + "pos", + "--format", + "csv", + "--units", + "mm", + "--side", + "both", + "-o", + "/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant-pos.csv", + "/home/ik/ChatGPT/Courant/hardware/courant/dist/courant.routed.kicad_pcb" + ], + "exit_code": 0, + "stdout": "Wrote position data to '/home/ik/ChatGPT/Courant/hardware/courant/dist/fab/courant-pos.csv'.\n", + "stderr": "" + }, + { + "command": [ + "/usr/bin/kicad-cli", + "pcb", + "export", + "svg", + "--mode-single", + "--exclude-drawing-sheet", + "--fit-page-to-board", + "--layers", + "F.Cu,F.Silkscreen,Edge.Cuts", + "-o", + "/home/ik/ChatGPT/Courant/hardware/courant/dist/courant-top.svg", + "/home/ik/ChatGPT/Courant/hardware/courant/deliverables/courant.kicad_pcb" + ], + "exit_code": 0, + "stdout": "Plotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/courant-top.svg'.\nDone.\n", + "stderr": "" + }, + { + "command": [ + "/usr/bin/kicad-cli", + "pcb", + "export", + "svg", + "--mode-single", + "--exclude-drawing-sheet", + "--fit-page-to-board", + "--layers", + "B.Cu,B.Silkscreen,Edge.Cuts", + "-o", + "/home/ik/ChatGPT/Courant/hardware/courant/dist/courant-bottom.svg", + "--mirror", + "/home/ik/ChatGPT/Courant/hardware/courant/deliverables/courant.kicad_pcb" + ], + "exit_code": 0, + "stdout": "Plotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/courant-bottom.svg'.\nDone.\n", + "stderr": "" + }, + { + "command": [ + "/usr/bin/kicad-cli", + "pcb", + "export", + "svg", + "--mode-single", + "--exclude-drawing-sheet", + "--fit-page-to-board", + "--layers", + "In1.Cu,In2.Cu,In3.Cu,In4.Cu,Edge.Cuts", + "-o", + "/home/ik/ChatGPT/Courant/hardware/courant/dist/route-inner.svg", + "/home/ik/ChatGPT/Courant/hardware/courant/deliverables/courant.kicad_pcb" + ], + "exit_code": 0, + "stdout": "Plotted to '/home/ik/ChatGPT/Courant/hardware/courant/dist/route-inner.svg'.\nDone.\n", + "stderr": "" + }, + { + "command": [ + "/usr/bin/kicad-cli", + "pcb", + "export", + "dxf", + "--mode-single", + "--output-units", + "mm", + "--layers", + "Edge.Cuts", + "--output", + "/home/ik/ChatGPT/Courant/hardware/courant/deliverables/courant-outline.dxf", + "/home/ik/ChatGPT/Courant/hardware/courant/deliverables/courant.kicad_pcb" + ], + "exit_code": 0, + "stdout": "Plotted to '/home/ik/ChatGPT/Courant/hardware/courant/deliverables/courant-outline.dxf'.\nDone.\n", + "stderr": "" + }, + { + "command": [ + "/usr/bin/kicad-cli", + "pcb", + "export", + "pdf", + "--mode-single", + "--black-and-white", + "--sketch-pads-on-fab-layers", + "--layers", + "Edge.Cuts,F.Fab,F.Silkscreen", + "--output", + "/home/ik/ChatGPT/Courant/hardware/courant/deliverables/courant-mechanical.pdf", + "/home/ik/ChatGPT/Courant/hardware/courant/deliverables/courant.kicad_pcb" + ], + "exit_code": 0, + "stdout": "Plotted to '/home/ik/ChatGPT/Courant/hardware/courant/deliverables/courant-mechanical.pdf'.\nDone.\n", + "stderr": "" + } + ] +} \ No newline at end of file diff --git a/hardware/CURRENT_RELEASE.json b/hardware/CURRENT_RELEASE.json new file mode 100644 index 0000000..8fc2a25 --- /dev/null +++ b/hardware/CURRENT_RELEASE.json @@ -0,0 +1,79 @@ +{ + "generated_utc": "2026-09-16T02:41:55.345723+00:00", + "status": "current engineering baseline; not manufacturing approval", + "boards": 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"hardware/GUARDED_GENERATORS.json", + "refresh_workflow": "hardware/refresh_outputs.py", + "rollback_archive": "/home/ik/ChatGPT/RADIAN_Release_Sync_20260916T015425Z/backup_hardware_before_sync.tar.gz", + "retired_stale_files": "/home/ik/ChatGPT/RADIAN_Release_Sync_20260916T015425Z/retired_from_active_repo/", + "final_audit_directory": "/home/ik/ChatGPT/RADIAN_Release_Sync_20260916T015425Z/final_audit", + "git_commit_created": false, + "git_push_performed": false +} diff --git a/hardware/FINAL_VALIDATION_20260917.json b/hardware/FINAL_VALIDATION_20260917.json new file mode 100644 index 0000000..c22f02e --- /dev/null +++ b/hardware/FINAL_VALIDATION_20260917.json @@ -0,0 +1,116 @@ +{ + "date": "2026-09-17", + "scope": "RADIAN six-pot FX panel + direct panel/mainboard mezzanine + enclosure revision", + "authoritative_boards": { + "mainboard": { + "path": "hardware/courant/deliverables/courant.kicad_pcb", + "sha256": "d7e2a898628225a0c21e27cb2387acf627036a41f7194c9551310b80ddac1b14", + "drc_violations": 0, + "unconnected": 0 + }, + "panel": { + "path": "hardware/panel/design/radian_panel.kicad_pcb", + "sha256": "2640a117c312d2dd634bed3f620eb7622dab7716cf4d0946a9230fb8ff92d2a2", + "erc_violations": 0, + "drc_violations": 0, + "unconnected": 0, + "schematic_parity": 0 + } + }, + "controls": [ + "TENSION", + "DECAY", + "CHAOS", + "DRIVE", + "DELAY", + "REVERB" + ], + "stack": { + "revision": "STACK-P2", + "main_mpn": "IPT1-110-06-L-D", + "panel_mpn": "IPS1-110-01-L-D", + "main_drill_mm": 1.02, + "panel_drill_mm": 1.04, + "fully_mated_gap_mm": 19.99, + "max_gap_mm": 20.45, + "support_target_mm": 20.0, + "mating_pins_checked": 40, + "net_xy_mismatches": 0, + "max_xy_delta_mm": 1.59e-14 + }, + "rtl": { + "ghdl_testbenches_passed": 28, + "failed": 0, + "includes": [ + "six-pot panel RMW", + "onboard FX chain", + "presets", + "MIDI/CV", + "I2S", + "TDM", + "top-level resonator" + ] + }, + "tscircuit": { + "main_typecheck": "pass", + "main_source_check": "pass", + "main_full_build": "pass", + "panel_build": "pass", + "bga_0201_pad_comparison": { + "pads": 76, + "mismatches": 0, + "worst_center_delta_mm": 3.362880601580381e-07, + "note": "custom tscircuit pad-only 0201 model avoids a false rotated-bottom courtyard-overlap diagnostic; native KiCad DRC remains authoritative for courtyards" + } + }, + "bom": { + "main_placements": 191, + "main_unresolved": 0, + "main_stack_qty": 2, + "panel_stack_qty": 2 + }, + "packages": { + "main_fab_zip": { + "path": "hardware/courant/dist/courant-fab.zip", + "sha256": "9159e62b65503af61e786e26a80dcd1be913c5a04e104c1cc5c3a0e2f93ee9a7", + "zip_integrity": "pass", + "embedded_bom_current": true + }, + "panel_fab_zip": { + "path": "hardware/panel/radian_panel-fab.zip", + "sha256": "341016495117f15b1a56e051833066d1dab58a5879c722866f3b8b892b004080", + "zip_integrity": "pass", + "embedded_bom_current": true + } + }, + "remaining_physical_only_gates": [ + "first-article Samtec seating/retention and ~20.0 mm support-stack tolerance check", + "real knob/nut/washer and enclosure manufacturing tolerance check", + "power/load/fault/thermal measurements", + "target FPGA implementation/timing and physical bring-up" + ], + "git_action": "No commit/push/reset/revert performed; existing dirty worktree preserved.", + "case": { + "revision": "CASE-P2-DIRECT-STACK", + "assembly_path": "hardware/panel/cad/RADIAN_P1_desktop_fit_study.step", + "assembly_sha256": "ef70ab0a0f20970f53eebf58b0f1367d4517faeeebfa8a1866a3acb62fd81d42", + "case_shell_path": "hardware/panel/cad/RADIAN_P1_case_shell_updated.step", + "case_shell_sha256": "4537715b2c1a7ae8ba7100f1178de85cac9fc652569fd058491b34546737527b", + "front_panel_path": "hardware/panel/cad/RADIAN_P1_front_panel_updated.step", + "front_panel_sha256": "3fdc030bb6edc160ecaa7e856368a2fdaf281691856615a3044ea26f26cef1b4", + "mainboard_shift_forward_mm": 0.46, + "pcb_gap_mm": 19.99, + "six_control_openings": "pass", + "mode_relocated": "pass", + "support_planes_updated": "pass", + "exported_step_validation": "pass", + "samtec_body_envelope_overlap": "0", + "obsolete_panel_harness_models": 0, + "preview_render": "pass", + "legacy_reference_sha256": "836ae149942d608420dbd1fcac250d0003f63a8b03143adf13a52d9e3234e33c", + "exact_faceplate_thickness_mm": 2.0, + "exact_reverb_insert_thickness_mm": 2.0, + "changed_enclosure_solid_fit": "pass", + "exported_step_roundtrip": "pass" + } +} diff --git a/hardware/FINAL_VALIDATION_20260917.md b/hardware/FINAL_VALIDATION_20260917.md new file mode 100644 index 0000000..272766e --- /dev/null +++ b/hardware/FINAL_VALIDATION_20260917.md @@ -0,0 +1,18 @@ +# RADIAN final validation — 2026-09-17 + +Six-pot FX/direct-stack and enclosure CAD revision is complete at RTL + PCB-source + native-KiCad + reference-mechanical-CAD level. + +- Mainboard: DRC **0**, unconnected **0**; SHA-256 `d7e2a898628225a0c21e27cb2387acf627036a41f7194c9551310b80ddac1b14`. +- Panel: ERC **0**, DRC **0**, unconnected **0**, parity **0**; SHA-256 `2640a117c312d2dd634bed3f620eb7622dab7716cf4d0946a9230fb8ff92d2a2`. +- Controls: **TENSION · DECAY · CHAOS · DRIVE · DELAY · REVERB**. +- Stack: Samtec **IPT1-110-06-L-D ↔ IPS1-110-01-L-D**, 40/40 pins net+XY matched, 19.99 mm fully mated, ~20.0 mm support target. +- RTL: **28/28 GHDL testbenches pass**. +- tscircuit: main typecheck/source check/full build pass; panel build pass. The exact 0201 tscircuit pad model matches **76/76** native pads. +- Main BOM: **191/191** placements resolved. +- Case CAD: CASE-P2-DIRECT-STACK; exact 2.00 mm faceplate/REVERB-insert thickness; six current macro openings + relocated MODE; mainboard shifted +0.46 mm for 19.99 mm fully-mated PCB gap; support planes updated; exported STEP validation and Xvfb preview render pass. +- Updated case assembly: hardware/panel/cad/RADIAN_P1_desktop_fit_study.step — SHA-256 ef70ab0a0f20970f53eebf58b0f1367d4517faeeebfa8a1866a3acb62fd81d42. +- Updated case shell: hardware/panel/cad/RADIAN_P1_case_shell_updated.step — SHA-256 4537715b2c1a7ae8ba7100f1178de85cac9fc652569fd058491b34546737527b. +- Main fab ZIP: `9159e62b65503af61e786e26a80dcd1be913c5a04e104c1cc5c3a0e2f93ee9a7`; embedded BOM current; ZIP integrity pass. +- Panel fab ZIP: `341016495117f15b1a56e051833066d1dab58a5879c722866f3b8b892b004080`; embedded BOM current; ZIP integrity pass. + +Remaining gates require physical hardware only: first-article Samtec seating/retention and support/enclosure tolerance, real knob/fastener stack, power/thermal/fault tests, and target-FPGA implementation/bring-up. diff --git a/hardware/GUARDED_GENERATORS.json b/hardware/GUARDED_GENERATORS.json new file mode 100644 index 0000000..db9dc33 --- /dev/null +++ b/hardware/GUARDED_GENERATORS.json @@ -0,0 +1,21 @@ +{ + "policy": "Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.", + "guarded": [ + "courant/scripts/route.py", + "courant/scripts/finish.py", + "courant/scripts/close.py", + "courant/scripts/bga_escape.py", + "courant/scripts/gnd_stitch.py", + "courant/scripts/hop.py", + "courant/scripts/nudge.py", + "courant/scripts/plane_escape.py", + "courant/scripts/power.py", + "courant/scripts/reland_decaps.py", + "courant/scripts/stitch.py", + "courant/scripts/export.ts", + "panel/source/export_ecad.py", + "panel/source/design_data.py" + ], + "mainboard_sha256": "92e66042479df826fed7b9fa62116f5fa4a31a84fc075922198cf18b91b7c6c5", + "panel_sha256": "9ddd199c1c5e68db47bafff481415ce4db48de8bb185d7cad0d8c10a837b4292" +} diff --git a/hardware/RELEASE_SYNC_STATUS.md b/hardware/RELEASE_SYNC_STATUS.md new file mode 100644 index 0000000..d6174e7 --- /dev/null +++ b/hardware/RELEASE_SYNC_STATUS.md @@ -0,0 +1,16 @@ +# Active RADIAN hardware synchronized — 2026-09-17 + +The canonical mainboard is `courant/deliverables/courant.kicad_pcb`; the canonical panel is `panel/design/radian_panel.kicad_pcb`. Both use project-local footprint libraries and are protected by `NATIVE_BASELINE.json`. + +This revision adds three dedicated FX pots and replaces the old panel/mainboard header-harness bundle with two direct Samtec mezzanine pairs. J17/J18 on the mainboard are IPT1-110-06-L-D; J100/J101 on the panel are IPS1-110-01-L-D. `stack/panel-stack.json` is the shared pinout/mechanical contract. + +Native validation after the final connector-footprint/drill update: mainboard DRC 0 violations / 0 unconnected; panel ERC 0, DRC 0, unconnected 0, schematic/PCB parity 0. The final native connector pads did not move relative to the routed generic stack pads; the exact drill recommendations are 1.02 mm main and 1.04 mm panel. + +The two boards were compared in assembled product coordinates: all 40 connector pins have the same net on both ends and matching XY positions. The selected Samtec combination is represented as 19.99 mm fully mated, 20.45 mm maximum PCB spacing, with a nominal ~20.0 mm mechanical support target. + +`hardware/refresh_outputs.py --board all` is the required synchronization path for Gerbers, Excellon drills, placement files, BOM/netlist metadata, previews and review ZIPs. These outputs remain engineering/review artifacts rather than a claim of physical production qualification. + +Remaining physical gates are first-article connector/support fit, retention, enclosure tolerance, electrical power/thermal/fault tests and actual target-FPGA implementation/timing/bring-up. No Git commit, push or reset was performed by this synchronization. + +## Case synchronization +The enclosure/product CAD is now CASE-P2-DIRECT-STACK. Six control openings and labels are modeled, MODE is relocated, the former MODE insert is the REVERB insert, the mainboard is shifted +0.46 mm to the 19.99 mm fully-mated plane, and front/rear support geometry follows that plane. Exported STEP geometry passes independent shaft-hole/support/Samtec-envelope checks. Current case validation is `panel/reports/case_direct_stack_update.json`. diff --git a/hardware/REPAIR_STATUS.md b/hardware/REPAIR_STATUS.md new file mode 100644 index 0000000..ead10dd --- /dev/null +++ b/hardware/REPAIR_STATUS.md @@ -0,0 +1,39 @@ +# RADIAN hardware status — 2026-09-18 + +The active hardware is the six-control, direct-stack revision. The native KiCad boards are authoritative engineering prototypes; the old panel/mainboard cable-harness topology is retired. + +| Native check (KiCad 10.0.6) | Mainboard | Panel | +|---|---:|---:| +| DRC violations | 0 | 0 | +| Unconnected items | 0 | 0 | +| Schematic ERC violations | N/A: no native mainboard schematic | 0 | +| Schematic/PCB parity findings | N/A | 0 | + +## Current revision +- Panel controls: TENSION, DECAY, CHAOS, DRIVE, DELAY, REVERB; push encoder; MODE; four LEDs. +- MCP3208 uses all eight channels. DRIVE/DELAY/REVERB use the three formerly grounded ADC channels through 1 kOhm / 10 nF input filters. +- FX macros are handled by read-modify-write in `panel_ctrl.vhd`, preserving the other packed FX-register fields. +- Mainboard/panel mate directly with two 2×10 2.54 mm connectors. There is no per-function panel-to-mainboard cable bundle. +- Legacy panel edge headers **J5–J15 have been removed from the mainboard**, and the now-unused copper stubs were pruned. J1–J4 remain for service/debug access. +- Main J17/J18: Samtec IPT1-110-06-L-D. Panel J100/J101: Samtec IPS1-110-01-L-D. +- Shared stack contract: `stack/panel-stack.json`, 19.99 mm fully mated, 20.45 mm maximum, nominal 20.0 mm support spacing. +- Final native pin proof: 40/40 mating pins match both net name and assembled XY; maximum computed XY delta is floating-point noise (<2e-14 mm). +- Generic panel utility headers are retired: J200 = Wurth 61201021621, J201/J306 = Molex 22-27-2021, J202 = Molex 22-27-2061, and JP1 = Wurth 450301014042 SPDT. Their routed endpoints were preserved, so this is a selected-component/footprint change rather than a wholesale reroute. +- Final CAD visualization no longer uses generic white component envelopes: both boards are exported from native KiCad component placements into `RADIAN_actual_parts_full_assembly.step`; actual/open PTV09A, PJ398SM, Omron B3F and LED geometry plus package-accurate production models are rendered. Remaining MPN-specific drawing-derived solids are explicitly documented. +- Mainboard production-part reconciliation is complete: all 180 referenced placements now carry Manufacturer + MPN and a resolved 3D model. U1/U5/Y1/Y2 and the service connectors now use semantic package identities matching the BOM; J1/J3/J4 are Molex 22-23-2021, J2 is 22-23-2061. No copper/pad/net/placement routing changed; only the selected Molex service connectors' finished-hole drills changed from 1.00 to 1.02 mm and their courtyards/models were corrected. +- Final CAD fidelity pass is complete. The old generic white PCB-component envelopes are no longer used by the canonical product assembly. Both boards are assembled from KiCad-placed component STEP groups. Panel pots/jacks/service switches/LEDs and small packages use real/open or maintained package geometry; ENC1/SW1 and vendor-gated connector models are explicitly drawing-derived mechanical references. Actual-part collision validation passes with zero unintended board-to-board or rear-guard/dock clashes. +- The remaining white-render artifact was traced to STEP **compound colors being discarded**. The canonical exporter now emits each physical solid as a colored child; round-trip audit reports **715/715 colored children, 0 missing colors, 0 default-white children**. Only actual natural-nylon Molex housings remain light cream. +- U8/H11L1M alignment is now mathematically locked: six model lead centers exactly match six native pads after KiCad Y inversion; placed U8 STEP center is exactly (48.000,-139.000) mm versus the native (48.000,139.000) PCB center. + +## Current outputs +Mainboard: `courant/deliverables/courant.kicad_pcb` and derived `courant/dist/` outputs. Panel: `panel/design/radian_panel.kicad_pcb` and derived `panel/fab/` / `panel/radian_panel-fab.zip`. `hardware/refresh_outputs.py` regenerates review/fabrication-format outputs only after native checks pass. + +The regenerated main manufacturer BOM now contains **180 placements** after removal of J5–J15; J17/J18 are the exact Samtec IPT1 part. The panel BOM contains the exact IPS1 mate at J100/J101 plus the selected Wurth/Molex utility connectors and JP1 switch listed above. + +## Validation still requiring physical hardware +KiCad/RTL checks do not prove connector seating under real tolerances, enclosure/support fit, insertion/retention force, power integrity, current/thermal/fault behaviour or actual FPGA timing on silicon. Build a first article with a ~20.0 mm board support stack, inspect full connector seating, and bench-test power/audio/control behaviour before ordering production quantity. + +No Git reset/revert/commit was used for this revision; pre-existing worktree changes were preserved. Backups from the direct-stack and connector-finalization work are under `hardware/_backups/`. + +## Current case +The case CAD is updated for the active six-pot/direct-stack hardware. The old three-macro front geometry is retired; the Samtec stack is modeled at 19.99 mm PCB spacing with ~20.0 mm support geometry. `panel/cad/RADIAN_P1_desktop_fit_study.step` is the current product assembly and `panel/reports/CASE_UPDATE.md` summarizes the mechanical changes. Physical first-article fit/retention remains unverified. diff --git a/hardware/courant/.backplane.json b/hardware/courant/.backplane.json new file mode 100644 index 0000000..9aa2e10 --- /dev/null +++ b/hardware/courant/.backplane.json @@ -0,0 +1,6 @@ +{ + "pcb": "deliverables/courant.kicad_pcb", + "gerbers": [ + "dist/fab" + ] +} diff --git a/hardware/courant/.gitignore b/hardware/courant/.gitignore new file mode 100644 index 0000000..e4b960e --- /dev/null +++ b/hardware/courant/.gitignore @@ -0,0 +1,4 @@ +node_modules/ +.tscircuit/ +.cache/ +dist/ diff --git a/hardware/courant/3dmodels/C_0201_0603Metric.wrl b/hardware/courant/3dmodels/C_0201_0603Metric.wrl new file mode 100644 index 0000000..302c1e4 --- /dev/null +++ b/hardware/courant/3dmodels/C_0201_0603Metric.wrl @@ -0,0 +1,208 @@ +#VRML V2.0 utf8 +#kicad StepUp wrl exported + +# Copyright (C) 2017, kicad StepUp +# +# This work is licensed under the [Creative Commons CC-BY-SA 4.0 License](https://creativecommons.org/licenses/by-sa/4.0/legalcode), +# with the following exception: +# To the extent that the creation of electronic designs that use 'Licensed Material' can be considered to be 'Adapted Material', +# then the copyright holder waives article 3 of the license with respect to these designs and any generated files which use data provided +# as part of the 'Licensed Material'. +# You are free to use the library data in your own projects without the obligation to share your project files under this or any other license agreement. +# However, if you wish to redistribute these libraries, or parts thereof (including in modified form) as a collection then the exception above does not apply. +# Please refer to https://github.com/KiCad/kicad-packages3D/blob/master/LICENSE.md for further clarification of the exception. +# Disclaimer of Warranties and Limitation of Liability. +# These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied. +# *USE 3D CAD DATA AT YOUR OWN RISK* +# *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.* +# +Shape { + appearance Appearance {material DEF PIN-01 Material { + ambientIntensity 0.271 + diffuseColor 0.824 0.82 0.781 + specularColor 0.328 0.258 0.172 + emissiveColor 0.0 0.0 0.0 + transparency 0.0 + shininess 0.7 + } + } +} +Shape { + appearance Appearance {material DEF CAP-CERAMIC-06 Material { + ambientIntensity 0.453 + diffuseColor 0.379 0.27 0.215 + specularColor 0.223 0.223 0.223 + emissiveColor 0.0 0.0 0.0 + transparency 0.0 + shininess 0.15 + } + } +} +Shape { geometry IndexedFaceSet +{ creaseAngle 0.50 coordIndex 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of electronic designs that use 'Licensed Material' can be considered to be 'Adapted Material', +# then the copyright holder waives article 3 of the license with respect to these designs and any generated files which use data provided +# as part of the 'Licensed Material'. +# You are free to use the library data in your own projects without the obligation to share your project files under this or any other license agreement. +# However, if you wish to redistribute these libraries, or parts thereof (including in modified form) as a collection then the exception above does not apply. +# Please refer to https://github.com/KiCad/kicad-packages3D/blob/master/LICENSE.md for further clarification of the exception. +# Disclaimer of Warranties and Limitation of Liability. +# These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied. +# *USE 3D CAD DATA AT YOUR OWN RISK* +# *DO NOT RELY UPON ANY INFORMATION FOUND HERE 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electronic designs that use 'Licensed Material' can be considered to be 'Adapted Material', +# then the copyright holder waives article 3 of the license with respect to these designs and any generated files which use data provided +# as part of the 'Licensed Material'. +# You are free to use the library data in your own projects without the obligation to share your project files under this or any other license agreement. +# However, if you wish to redistribute these libraries, or parts thereof (including in modified form) as a collection then the exception above does not apply. +# Please refer to https://github.com/KiCad/kicad-packages3D/blob/master/LICENSE.md for further clarification of the exception. +# Disclaimer of Warranties and Limitation of Liability. +# These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied. +# *USE 3D CAD DATA AT YOUR OWN RISK* +# *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT 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electronic designs that use 'Licensed Material' can be considered to be 'Adapted Material', +# then the copyright holder waives article 3 of the license with respect to these designs and any generated files which use data provided +# as part of the 'Licensed Material'. +# You are free to use the library data in your own projects without the obligation to share your project files under this or any other license agreement. +# However, if you wish to redistribute these libraries, or parts thereof (including in modified form) as a collection then the exception above does not apply. +# Please refer to https://github.com/KiCad/kicad-packages3D/blob/master/LICENSE.md for further clarification of the exception. +# Disclaimer of Warranties and Limitation of Liability. +# These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied. +# *USE 3D CAD DATA AT YOUR OWN RISK* +# *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT 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electronic designs that use 'Licensed Material' can be considered to be 'Adapted Material', +# then the copyright holder waives article 3 of the license with respect to these designs and any generated files which use data provided +# as part of the 'Licensed Material'. +# You are free to use the library data in your own projects without the obligation to share your project files under this or any other license agreement. +# However, if you wish to redistribute these libraries, or parts thereof (including in modified form) as a collection then the exception above does not apply. +# Please refer to https://github.com/KiCad/kicad-packages3D/blob/master/LICENSE.md for further clarification of the exception. +# Disclaimer of Warranties and Limitation of Liability. +# These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied. +# *USE 3D CAD DATA AT YOUR OWN RISK* +# *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT 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refer to https://github.com/KiCad/kicad-packages3D/blob/master/LICENSE.md for further clarification of the exception. +# Disclaimer of Warranties and Limitation of Liability. +# These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied. +# *USE 3D CAD DATA AT YOUR OWN RISK* +# *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.* +# +Shape { + appearance Appearance {material DEF PIN-01 Material { + ambientIntensity 0.271 + diffuseColor 0.824 0.82 0.781 + specularColor 0.328 0.258 0.172 + emissiveColor 0.0 0.0 0.0 + transparency 0.0 + shininess 0.7 + } + } +} +Shape { + appearance Appearance {material DEF IC-LABEL-01 Material { + ambientIntensity 0.082 + diffuseColor 0.691 0.664 0.598 + specularColor 0.0 0.0 0.0 + emissiveColor 0.0 0.0 0.0 + transparency 0.0 + shininess 0.01 + } + } +} +Shape { + appearance Appearance {material DEF IC-BODY-EPOXY-04 Material { + ambientIntensity 0.293 + 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a/hardware/courant/3dmodels/SOIC-8_3.9x4.9mm_P1.27mm.wrl b/hardware/courant/3dmodels/SOIC-8_3.9x4.9mm_P1.27mm.wrl new file mode 100644 index 0000000..7f89013 --- /dev/null +++ b/hardware/courant/3dmodels/SOIC-8_3.9x4.9mm_P1.27mm.wrl @@ -0,0 +1,987 @@ +#VRML V2.0 utf8 +#kicad StepUp wrl exported + +# Copyright (C) 2017, kicad StepUp +# +# This work is licensed under the [Creative Commons CC-BY-SA 4.0 License](https://creativecommons.org/licenses/by-sa/4.0/legalcode), +# with the following exception: +# To the extent that the creation of electronic designs that use 'Licensed Material' can be considered to be 'Adapted Material', +# then the copyright holder waives article 3 of the license with respect to these designs and any generated files which use data provided +# as part of the 'Licensed Material'. +# You are free to use the library data in your own projects without the obligation to share your project files under this or any other license agreement. +# However, if you wish to redistribute these libraries, or parts thereof (including in modified form) as a collection then the exception above does not apply. +# Please refer to https://github.com/KiCad/kicad-packages3D/blob/master/LICENSE.md for further clarification of the exception. +# Disclaimer of Warranties and Limitation of Liability. +# These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied. +# *USE 3D CAD DATA AT YOUR OWN RISK* +# *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.* +# +Shape { + appearance Appearance {material DEF PIN-01 Material { + ambientIntensity 0.271 + diffuseColor 0.824 0.82 0.781 + specularColor 0.328 0.258 0.172 + emissiveColor 0.0 0.0 0.0 + transparency 0.0 + shininess 0.7 + } + } +} +Shape { + appearance Appearance {material DEF IC-LABEL-01 Material { + ambientIntensity 0.082 + diffuseColor 0.691 0.664 0.598 + specularColor 0.0 0.0 0.0 + emissiveColor 0.0 0.0 0.0 + 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0.169 0.084,-1.024 0.331 0.084,-1.015 0.169 0.090,-1.015 0.331 0.090,-1.009 0.169 0.098,-1.009 0.331 0.098,-1.005 0.169 0.108,-1.005 0.331 0.108,-1.004 0.169 0.118,-1.004 0.331 0.118] +}} +appearance Appearance{material USE PIN-01 } +} +Shape { geometry IndexedFaceSet +{ creaseAngle 0.50 coordIndex [0,1,2,-1,2,1,3,-1] +coord Coordinate { point [-1.181 0.169 0.079,-1.043 0.169 0.079,-1.181 0.331 0.079,-1.043 0.331 0.079] +}} +appearance Appearance{material USE PIN-01 } +} +Shape { geometry IndexedFaceSet +{ creaseAngle 0.50 coordIndex [0,1,2,-1,2,1,3,-1] +coord Coordinate { point [-1.181 0.169 0.000,-1.181 0.169 0.079,-1.181 0.331 0.000,-1.181 0.331 0.079] +}} +appearance Appearance{material USE PIN-01 } +} +Shape { geometry IndexedFaceSet +{ creaseAngle 0.50 coordIndex [0,1,2,-1,2,1,3,-1] +coord Coordinate { point [-1.043 0.169 0.000,-1.181 0.169 0.000,-1.043 0.331 0.000,-1.181 0.331 0.000] +}} +appearance Appearance{material USE PIN-01 } +} +Shape { geometry IndexedFaceSet +{ creaseAngle 0.50 coordIndex [0,1,2,-1,2,1,3,-1,3,4,5,-1,1,4,3,-1,5,6,7,-1,4,6,5,-1,7,8,9,-1,6,8,7,-1,9,10,11,-1,8,10,9,-1,11,12,13,-1,10,12,11,-1] +coord Coordinate { point [-0.925 0.169 0.118,-0.929 0.169 0.088,-0.925 0.331 0.118,-0.929 0.331 0.088,-0.941 0.169 0.059,-0.941 0.331 0.059,-0.960 0.169 0.035,-0.960 0.331 0.035,-0.984 0.169 0.016,-0.984 0.331 0.016,-1.013 0.169 0.004,-1.013 0.331 0.004,-1.043 0.169 0.000,-1.043 0.331 0.000] +}} +appearance Appearance{material USE PIN-01 } +} +Shape { geometry IndexedFaceSet +{ creaseAngle 0.50 coordIndex [0,1,2,-1,2,1,3,-1] +coord Coordinate { point [-0.925 0.169 0.285,-0.925 0.169 0.118,-0.925 0.331 0.285,-0.925 0.331 0.118] +}} +appearance Appearance{material USE PIN-01 } +} diff --git a/hardware/courant/NATIVE_BASELINE.json b/hardware/courant/NATIVE_BASELINE.json new file mode 100644 index 0000000..80fd69e --- /dev/null +++ b/hardware/courant/NATIVE_BASELINE.json @@ -0,0 +1,6 @@ +{ + "authoritative_board": "deliverables/courant.kicad_pcb", + "sha256": "92e66042479df826fed7b9fa62116f5fa4a31a84fc075922198cf18b91b7c6c5", + "policy": "Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.", + "review_only": true +} diff --git a/hardware/courant/circuit-jsx.d.ts b/hardware/courant/circuit-jsx.d.ts new file mode 100644 index 0000000..5ec3b3c --- /dev/null +++ b/hardware/courant/circuit-jsx.d.ts @@ -0,0 +1,19 @@ +import type { Attributes } from "react" +import type { BoardProps, ChipProps, ConnectorProps, FiducialProps, CopperPourProps, CourtyardRectProps, SchematicSheetProps, ResistorProps, CapacitorProps, InductorProps, DiodeProps, NetProps, HoleProps, FootprintProps, SmtPadProps, PlatedHoleProps, SilkscreenPathProps, SilkscreenTextProps, ViaProps } from "@tscircuit/props" +declare module "react" { + namespace JSX { + interface IntrinsicElements { + board: BoardProps & Attributes; chip: ChipProps & Attributes; + resistor: ResistorProps & Attributes; capacitor: CapacitorProps & Attributes; + inductor: InductorProps & Attributes; diode: DiodeProps & Attributes; + net: NetProps & Attributes; hole: HoleProps & Attributes; + connector: ConnectorProps & Attributes; fiducial: FiducialProps & Attributes; + copperpour: CopperPourProps & Attributes; courtyardrect: CourtyardRectProps & Attributes; + schematicsheet: SchematicSheetProps & Attributes; + footprint: FootprintProps & Attributes; smtpad: SmtPadProps & Attributes; + platedhole: PlatedHoleProps & Attributes; via: ViaProps & Attributes; + silkscreenpath: SilkscreenPathProps & Attributes; + silkscreentext: SilkscreenTextProps & Attributes; + } + } +} diff --git a/hardware/courant/courant.circuit.tsx b/hardware/courant/courant.circuit.tsx new file mode 100644 index 0000000..dce48d2 --- /dev/null +++ b/hardware/courant/courant.circuit.tsx @@ -0,0 +1,99 @@ +import { parts, nets, thermalVias, type Part } from "./design" +import { lands, fpgaRows } from "./footprints" + +function Component({p,index}:{p:Part;index:number}) { + if(p.name==="U1") { + const toPin=(ball:string)=>`pin${fpgaRows.indexOf(ball[0])*16+Number(ball.slice(1))}` + p={...p,nets:Object.fromEntries(Object.entries(p.nets).map(([ball,net])=>[toPin(ball),net])), + labels:Object.fromEntries(Object.keys(p.labels!).map(ball=>[toPin(ball),ball])), + nc:p.nc!.map(toPin)} + } + const footprint=typeof p.footprint==="string"?p.footprint:lands(p.footprint) + const common={name:p.name,footprint,pcbX:p.x,pcbY:p.y,layer:p.layer??"top" as const, + pcbRotation:p.rotation??0, + schX: (index%12)*7,schY:-Math.floor(index/12)*7} + const connections=Object.fromEntries(Object.entries(p.nets).map(([pin,net])=>[pin,`net.${net}`])) + if(p.kind==="resistor")return + if(p.kind==="capacitor")return + if(p.kind==="inductor")return + if(p.kind==="diode")return + const pinLabels=p.labels??Object.fromEntries([ + ...Object.keys(p.nets).map(pin=>[pin,pin]),...(p.nc??[]).map(pin=>[pin,pin]), + ]) + // Declare supply pins from what they are actually tied to, so the netlist + // checks can tell a rail pin from a signal pin. + const rails:Record={VIN5:5,V3V3:3.3,A3V3:3.3,V1V8:1.8,V1:1} + const pinAttributes=Object.fromEntries(Object.entries(p.nets).flatMap(([pin,net]):[string,object][]=> + net==="GND"?[[pin,{requiresGround:true}]]: + net in rails?[[pin,{requiresPower:true,requiresVoltage:rails[net]}]]:[])) + // Panel/rear I/O headers are connectors, and each is rotated so its pins open + // toward the nearest board edge rather than into the board. + if(p.kind==="connector")return + return +} +export default function Courant() { + return + {/* Routing is handed off: tscircuit's capacity-autorouter does not converge + on this board (docs/board.md section 3), so asking for it costs ~17 + minutes per build and still emits no copper. `none` keeps every build + fast and honest; the DSN and KiCad exports carry the netlist out. */} + + {nets.map(name=>)} + {parts.map((p,index)=>)} + {[[-75,45],[75,45],[-75,-45],[75,-45]].map(([x,y],i)=>)} + {/* Assembly fiducials: three, non-collinear, so pick-and-place can resolve + rotation as well as offset for the 256-ball BGA. The third is at + (-68,-45), not (-72,-41): that put its pad 0.27 mm from J15 pin 1, i.e. + overlapping it, which KiCad DRC reports as a zero-clearance violation + and a soldermask bridge. Fiducials carry no net, so no netlist check + could ever have seen it. */} + {[[-72,41],[72,41],[-68,-45]].map(([x,y],i)=>)} + {/* Thermal vias in the three switchers' exposed pads. Placed here rather + than left to the router: they are a thermal structure, not a + connection, and no autorouter will invent them (see design.ts). */} + {thermalVias.map(v=>)} + {/* Six layers: signal / GND / signal / V3V3 / GND / signal. F.Cu, In2 and + B.Cu carry signal, each with a ground plane beside it (F.Cu and In2 + against In1, B.Cu against In4), so every BGA escape and every I2S/SPI + clock has a continuous return path directly underneath. + + In3 carries 3.3 V as a pour and stays routable. V3V3 reaches 96 pins + and cost 634 mm of trace when routed as copper, the largest net on the + board; as a pour each of those pins is a via straight down, and the + signals that still need In3 simply fill around it. A slot in a power + pour is cheap. A slot in a return path is not, which is why + scripts/route.py reserves the two ground planes and nothing else. + + Eight layers was tried and is not needed. The board appeared to require + them only because of a routing-handoff mistake: declaring the plane + layers `(type power)` in the DSN does not keep signals off them, it + makes them unavailable for connections entirely, so GND pins could not + reach their own pours. That left 55-60 connections unrouted across + three runs and was misread as the board being too dense. With the real + mechanism -- a per-net-class `use_layer` clause that restricts signals + while leaving GND the whole stackup -- six layers routes to 9 unrouted + and eight routes to 14. Fewer layers, better result. */} + + + + + + + + + + + + +} diff --git a/hardware/courant/deliverables/MAINBOARD_REPAIR.md b/hardware/courant/deliverables/MAINBOARD_REPAIR.md new file mode 100644 index 0000000..925ab50 --- /dev/null +++ b/hardware/courant/deliverables/MAINBOARD_REPAIR.md @@ -0,0 +1,52 @@ +> **Release synchronization: 2026-09-16.** Current native boards, fabrication-format exports and CAD are indexed in `../../RELEASE_SYNC_STATUS.md`. Earlier statements below about pre-repair exports are historical; electrical/physical validation limitations still apply. + +# RADIAN mainboard — native repair, 2026-09-16 + +## Result +The corrected mainboard passes Backplane KiCad 10.0.6 native DRC with **0 errors, 0 warnings and 0 unconnected items** under the existing project rules. All error/warning/exclusion severities were requested. No check settings were weakened and no new exclusions were added. + +This is a PCB geometry/connectivity and library/artwork correction, **not a fabrication release or an electrical design sign-off**. + +## Executed changes +- Consolidated 12 groups of overlapping same-net through-vias, removing 13 redundant vias while retaining existing via centres. +- Removed 34 track segments and one additional unused via through native-checked cleanup trials. +- Trimmed/reanchored three branches to their actual intermediate connections: GND to its existing via, V1V8 to C113 pad 1, and adc_cs_n to its existing layer-transition via. Blind whole-segment removal failed checks and was reverted before the accepted localized repairs. +- Restored a local RadianMain.pretty library: 43 variants representing the existing embedded footprint geometry for 202 instances. This is consistency, not manufacturer footprint verification. +- Replaced 45 undersized generic pin labels with 1 mm pin numbers; moved 95 conflicting outline graphics to fabrication layers; repositioned conflicting text. Bottom C100–C137 references now sit horizontally beside their own components instead of being scattered away from them. + +Final native board: **2,158 track segments and 299 vias** (formerly 2,192 and 313). + +## Independent preservation checks +- All 746 pad definitions retain their original positions, sizes, holes, orientation, layers, attributes and pin/net assignments. +- All 202 footprint instance placements are unchanged. +- The 96 connected pad groups match the original board exactly using native connectivity data. +- Board outline, thickness and enabled layers are unchanged. +- The project .kicad_pro file is byte-identical, including rule limits and severity settings. +- Minimum nominal drill-edge spacing: **0.258511 mm**, against the existing 0.25 mm rule. +- Exported Excellon files: 350 plated + 4 non-plated holes; no coincident centres; minimum exported drill-edge spacing **0.258587 mm** after coordinate rounding. + +Original PCB SHA-256: `0683ead4a73049f5a2276b2cd3bf6389199609574a67aab8e27f48040a18deec`. + +## Tool provenance +Checks used Backplane_KiCad 10.0.6, source commit `1c193606eddedbf98f8c9af5100b5e8f79da603d`. Editing used the installed KiCad 10.0.6 Python API and narrowly scoped S-expression edits. The Backplane desktop GUI was not automated. + +## Files and evidence +- `working/courant.kicad_pcb` and its matching project and `fp-lib-table` form the corrected standalone handoff. +- `reports/06_compact_refs/` contains the final working-copy native result. +- `reports/07_published/` contains the post-copy native check when applied to the repository. +- `reports/invariants.json`, `exported_drill_check.json`, `via_consolidation.json`, `safe_dangling_cleanup.json`, `branch_trimming.json`, `footprint_library_mapping.json` and the artwork logs document the tests and changes. +- `review_exports/` contains refreshed review-only Gerbers, Excellon drills/maps and native SVG/PNG previews. These are NOT an approved manufacturing package. +- `baseline/` preserves the original handoff before editing. Trial reports with nonzero counts are historical experiments, not final results. +- `scripts/` records the repair process; do not blindly rerun destructive generation scripts on a later board revision. + +## Scope and remaining release gates +The existing project still ignores missing courtyards, track centering on vias, tuning-profile geometry, footprint filters and footprint-type mismatch checks. Zero findings refers to this unchanged profile. + +No native .kicad_sch was supplied for the mainboard, so **mainboard ERC and schematic/PCB parity were not run**. Empty parity arrays in DRC are not a passed schematic comparison. Electrical correctness, FPGA constraints/timing/boot, power integrity, regulator layout adequacy, actual footprint/MPN correctness, thermal/fault behaviour and physical assembly remain separate validations. + +A 0.2585 mm nominal drill spacing is not a fabrication-tolerance guarantee; confirm the actual fabricator's requirements. No component positions, values or nets were redesigned to make this result pass. + +## Avoid stale outputs +The TypeScript generators, routing intermediates under `hardware/courant/dist`, earlier fab ZIPs, and the older assembly STEP / SVG exports have NOT been regenerated or certified by this repair. The older STEP still represents the original drill/copper artwork. Re-export from the corrected native board for new geometry-sensitive outputs. Keep the recorded repaired board as the baseline until generator output has been reconciled and revalidated. + +No commit or push was made. Unrelated dirty files and the separate panel PCB were not changed. diff --git a/hardware/courant/deliverables/README.md b/hardware/courant/deliverables/README.md new file mode 100644 index 0000000..8383d46 --- /dev/null +++ b/hardware/courant/deliverables/README.md @@ -0,0 +1,96 @@ +> **Release synchronization: 2026-09-16.** Current native boards, fabrication-format exports and CAD are indexed in `../../RELEASE_SYNC_STATUS.md`. Earlier statements below about pre-repair exports are historical; electrical/physical validation limitations still apply. + +# Current native mainboard — 2026-09-16 + +The PCB in this folder passes Backplane KiCad 10.0.6 DRC: **0 errors, 0 warnings, 0 unconnected**, with unchanged project rules. Current counts: **2,158 track segments and 299 vias**. See `MAINBOARD_REPAIR.md` and `native_checks/drc.json`. + +The assembly STEP, mechanical PDF/DXF, `dist/` PCB copies, 2D views, Gerbers, drills, placement data, BOM/netlist metadata and `dist/courant-fab.zip` have been regenerated from the current repaired native board. Use `hardware/refresh_outputs.py` for future review-export refreshes. Legacy route/reconstruction scripts are guarded from overwriting the authoritative native PCB. + +**Not a manufacturing approval.** Component/footprint sign-off, FPGA operation/timing, electrical power integrity, thermal/fault behavior and physical assembly remain separate release gates. + +The original handoff notes below are preserved as historical information; their old track/via counts are superseded above. + +--- + +# Courant Rev A — handoff package + +Standalone Artix-7 instrument board. **160 × 100 mm** on the Edge.Cuts +centreline (160.1 × 100.1 measured over the 0.1 mm stroke), 6 layers, 1.6 mm. +Four NPTH 3.2 mm mounting holes at (25,55), (175,55), (25,145), (175,145) — +150 × 90 mm spacing. +Routed and native-checked: **0 DRC errors, 0 warnings, 0 unconnected**, 2158 track segments, +4386.2 mm of copper, 299 vias, both ground planes uncut. + +| File | What it is | +| --- | --- | +| `courant.kicad_pcb` | the board. KiCad 10 | +| `courant.kicad_pro` | project file — **open it alongside the board or you get KiCad's default design rules, not this board's** | +| `courant-assembly.step` | populated assembly, 3D. Board body, copper, silkscreen, soldermask and 183 of 202 component bodies | +| `courant-bom.csv` | bill of materials, 57 line items / 183 placements | +| `courant-netlist.txt` | 96 nets, extracted from the routed board | +| `courant-panel-interface.csv` | pinout of all 15 headers — the spec for building the front panel | +| `courant-mechanical.pdf` | outline, fabrication layer, silkscreen | +| `courant-outline.dxf` | board outline for mechanical CAD | +| `courant-schematic.svg` | schematic — 183 components, 739 pins, 532 wires, 248 net labels, 7038 x 6958 px vector | +| `courant-panel-hardware.md` | off-board parts, with `datasheets/` alongside | +| `courant-eurorack.md` | Eurorack status: what works as built, what changes, with values | +| `courant-source-design.ts` | the design source | + +## Design rules + +Default 0.15 mm track / 0.15 mm clearance, vias 0.55 / 0.25 mm. Power class +0.40 mm track, Ground 0.30 mm. These are set by the FTG256's 1.0 mm ball pitch: +escaping between two balls needs width + 2 × clearance inside a 0.5 mm gap, and +0.15 + 0.30 = 0.45 mm fits where KiCad's 0.2 mm defaults (0.6 mm) cannot. +0.25 mm drill through 1.6 mm is a 6.4:1 aspect ratio — inside any standard +6-layer process. + +## Notes on three of these + +**The schematic is rendered by `scripts/schematic.py`, not by tscircuit.** +`tsci export -f schematic-svg` and `-f schematic-pdf` both emit a near-empty +sheet for this design — about ten kilobytes, twenty text elements for two +hundred components — while the circuit JSON behind them holds all 183 +components, 739 ports and 532 traces. The data was never missing, only the +drawing, so the drawing is done here. It is complete and to scale; it is not +arranged for signal flow, because tscircuit places symbols in declaration +order and no autolayout turns that into a drafted sheet. + +**Every placement has a manufacturer part number**, and each one was checked +against live stock rather than inferred. Two families are covered by one +verified member plus the manufacturer's own value coding, noted on the line: +the Murata C0G run and the Yageo RC0603FR series. + +**The panel hardware in `courant-panel-hardware.md` is a proposal.** The design +names no off-board parts and the right ones depend on a panel format that does +not exist yet, so those selections are specified to be electrically correct and +mechanically ordinary — a starting BOM, not a decision already taken. The four +that are sourced have datasheets in `datasheets/`. + +## One design fix made while preparing this + +R10 was **25 kΩ**, which is on no E-series grid and is not a stocked 1 % part — +a search for it returns 24.9 kΩ. It sets the V1 rail through the TPS62130's +0.8 V reference, so it is now **24.9 kΩ**: 0.8 x (1 + 24.9/100) = 0.9992 V +against a 1.000 V target, nearer than the 1 % resistors can hold. Fixed in +`design.ts` and in the board; `npm run check` passes. + +## Before ordering + +U1 is **XC7A50T-1FTG256I**, swapped from the XC7A35T-1FTG256C. The pin +compatibility is verified, not assumed: AMD's package files for the two parts +in FTG256 — both kept in `reference/` — are byte-identical from line 2 to the +end. All 256 balls, their banks, I/O types and no-connect flags match; the only +difference in either file is the device name on the header line. That makes the +swap a part number and nothing else, and it is the cheaper part besides +($67.01 against $118.75 at JLCPCB, both in stock) with 57% more logic and an +industrial temperature range. + +One check is still worth doing and cannot be done from here: a Vivado synthesis +run against the A50T using the generated `courant_rev_a.xdc`. It will reject +any invalid ball assignment outright, and it confirms timing still closes — +the speed grade is unchanged at -1, so it should. + +## Native repair and current files + +See `../../REPAIR_STATUS.md` and `../reports/native/`. The local `RadianMain.pretty` snapshots and `fp-lib-table` must travel with the board. Both routed board copies and the manufacturing-format review exports were replaced on 2026-09-16. Native checks are not electrical or physical product validation. diff --git a/hardware/courant/deliverables/RadianMain.pretty/1N4148W__9d65e6bad1.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/1N4148W__9d65e6bad1.kicad_mod new file mode 100644 index 0000000..d3fafe7 --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/1N4148W__9d65e6bad1.kicad_mod @@ -0,0 +1,150 @@ +(footprint "1N4148W__9d65e6bad1" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -0.705 0) + (layer "F.SilkS") + (uuid "1999545f-514b-4814-a482-a86c29bd0f3a") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "1N4148W" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "1e0fabde-52e0-4cf3-8def-0e824679d275") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid 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"F.Fab") + (uuid "7c20e63f-3bea-4bd7-8a6e-371ba6371089") + ) + (fp_line + (start -0.2688 0.336) + (end -0.2688 -0.336) + (stroke + (width 0.042) + (type default) + ) + (layer "F.Fab") + (uuid "185bceee-793f-418b-94e3-583966b7ff5c") + ) + (fp_line + (start 0.2688 -0.336) + (end 0.2688 0.336) + (stroke + (width 0.042) + (type default) + ) + (layer "F.Fab") + (uuid "6aa8e644-6125-447e-aff8-ab4f9f9eea67") + ) + (fp_line + (start 0.2688 0) + (end -0.2688 0.336) + (stroke + (width 0.042) + (type default) + ) + (layer "F.Fab") + (uuid "57d74393-e902-4f07-b331-2aae42465c6f") + ) + (fp_line + (start 0.2688 0) + (end 0.42 0) + (stroke + (width 0.042) + (type default) + ) + (layer "F.Fab") + (uuid "eafe8a70-1d3c-4627-885f-c271acd58e31") + ) + (pad "1" smd rect + (at -1.65 0) + (size 0.9 1.2) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "3647f89a-4bc5-4b13-827f-bf1907897e6e") + ) + (pad "2" smd rect + (at 1.65 0) + (size 0.9 1.2) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "da2aa0a8-6aeb-4d9a-8e56-67c55bb05f7c") + ) + (embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/5V_INPUT__f4047b8a89.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/5V_INPUT__f4047b8a89.kicad_mod new file mode 100644 index 0000000..e4a4a2f --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/5V_INPUT__f4047b8a89.kicad_mod @@ -0,0 +1,116 @@ +(footprint "5V_INPUT__f4047b8a89" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -2.54 0) + (layer "F.SilkS") + (uuid "e9973227-7f2d-4457-8d78-21a5ef1c38b3") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "J1" + (at 0 3 270) + (layer "F.Fab") + (hide yes) + (uuid "005d9517-6a3e-4bb8-90a5-d1a6ce067dec") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 270) + (layer "F.Fab") + (hide yes) + (uuid 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"1ceba3f5-c1f3-4355-b033-335da84ce503") + (effects + (font + (size 0.9 0.9) + (thickness 0.15) + ) + ) + ) + (pad "1" thru_hole rect + (at -1.27 0) + (size 1.5 1.5) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "dcb8bb6c-c10e-4309-b0d2-4b9d39530b6b") + ) + (pad "2" thru_hole circle + (at 1.27 0 270) + (size 1.5 1.5) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "e3dbc1c9-7695-4d60-abb8-31f8208f1877") + ) + (embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/ASE-100_000MHZ-LC-T__ae75d0e002.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/ASE-100_000MHZ-LC-T__ae75d0e002.kicad_mod new file mode 100644 index 0000000..749d7f0 --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/ASE-100_000MHZ-LC-T__ae75d0e002.kicad_mod @@ -0,0 +1,143 @@ +(footprint "ASE-100_000MHZ-LC-T__ae75d0e002" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -3 0) + (layer "F.SilkS") + (hide yes) + (uuid "d590d5e3-814c-43ed-90e6-de2cfde373cc") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Value" "ASE-100.000MHZ-LC-T" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "37d94b51-f385-4d80-b599-96c2b5970eba") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "e5e1d075-5117-4670-8a9f-076df8a0b094") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "ae0fcc2d-484a-4ea8-a252-64f67aad4571") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Supplier Part Number" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "daa0a587-a57f-436a-8fbe-c9aa2a55d1e4") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (fp_rect + (start -1.95 -1.55) + (end 1.95 1.55) + (stroke + (width 0.05) + (type default) + ) + (fill no) + (layer "F.CrtYd") + (uuid "6c34d874-0d16-4bab-b60a-53521a1c15e1") + ) + (fp_line + (start -1.6 -1.25) + (end 1.6 -1.25) + (stroke + (width 0.12) + (type default) + ) + (layer "F.Fab") + (uuid "1bf8a511-7ffb-4f58-aa09-6fff04933b87") + ) + (fp_line + (start -1.6 1.25) + (end -1.6 -1.25) + (stroke + (width 0.12) + (type default) + ) + (layer "F.Fab") + (uuid "f0204954-a76d-460d-a518-6942f46482ad") + ) + (fp_line + (start 1.6 -1.25) + (end 1.6 1.25) + (stroke + (width 0.12) + (type default) + ) + (layer "F.Fab") + (uuid "454abc17-3350-4e85-afe4-8e010228eaf5") + ) + (fp_line + (start 1.6 1.25) + (end -1.6 1.25) + (stroke + (width 0.12) + (type default) + ) + (layer "F.Fab") + (uuid "2bc9afb5-b2a2-44f0-a763-a7d7dac8823d") + ) + (pad "1" smd rect + (at -1.1 0.8) + (size 1.2 1) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "358063f1-3dca-42d2-a076-df5ac56ccbc3") + ) + (pad "2" smd rect + (at 1.1 0.8) + (size 1.2 1) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "77d52ecb-dfc3-4b97-8f65-33f8aaa6609b") + ) + (pad "3" smd rect + (at 1.1 -0.8) + (size 1.2 1) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "08f19459-130b-4f5f-b516-412d1bdf4c27") + ) + (pad "4" smd rect + (at -1.1 -0.8) + (size 1.2 1) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "1c83578a-f8dd-40e0-9459-d5704f7b4f80") + ) + (embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/Abracon_ASE_3225_4Pin.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/Abracon_ASE_3225_4Pin.kicad_mod new file mode 100644 index 0000000..9de339b --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/Abracon_ASE_3225_4Pin.kicad_mod @@ -0,0 +1,149 @@ +(footprint "Abracon_ASE_3225_4Pin" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -3 0) + (layer "F.SilkS") + (hide yes) + (uuid "d590d5e3-814c-43ed-90e6-de2cfde373cc") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Value" "Abracon ASE 3225" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "37d94b51-f385-4d80-b599-96c2b5970eba") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "e5e1d075-5117-4670-8a9f-076df8a0b094") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "ae0fcc2d-484a-4ea8-a252-64f67aad4571") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Supplier Part Number" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "daa0a587-a57f-436a-8fbe-c9aa2a55d1e4") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (fp_rect + (start -1.95 -1.55) + (end 1.95 1.55) + (stroke + (width 0.05) + (type default) + ) + (fill no) + (layer "F.CrtYd") + (uuid "6c34d874-0d16-4bab-b60a-53521a1c15e1") + ) + (fp_line + (start -1.6 -1.25) + (end 1.6 -1.25) + (stroke + (width 0.12) + (type default) + ) + (layer "F.Fab") + (uuid "1bf8a511-7ffb-4f58-aa09-6fff04933b87") + ) + (fp_line + (start -1.6 1.25) + (end -1.6 -1.25) + (stroke + (width 0.12) + (type default) + ) + (layer "F.Fab") + (uuid "f0204954-a76d-460d-a518-6942f46482ad") + ) + (fp_line + (start 1.6 -1.25) + (end 1.6 1.25) + (stroke + (width 0.12) + (type default) + ) + (layer "F.Fab") + (uuid "454abc17-3350-4e85-afe4-8e010228eaf5") + ) + (fp_line + (start 1.6 1.25) + (end -1.6 1.25) + (stroke + (width 0.12) + (type default) + ) + (layer "F.Fab") + (uuid "2bc9afb5-b2a2-44f0-a763-a7d7dac8823d") + ) + (pad "1" smd rect + (at -1.1 0.8) + (size 1.2 1) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "358063f1-3dca-42d2-a076-df5ac56ccbc3") + ) + (pad "2" smd rect + (at 1.1 0.8) + (size 1.2 1) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "77d52ecb-dfc3-4b97-8f65-33f8aaa6609b") + ) + (pad "3" smd rect + (at 1.1 -0.8) + (size 1.2 1) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "08f19459-130b-4f5f-b516-412d1bdf4c27") + ) + (pad "4" smd rect + (at -1.1 -0.8) + (size 1.2 1) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "1c83578a-f8dd-40e0-9459-d5704f7b4f80") + ) + + (model "${KIPRJMOD}/cad/models/Oscillator_3225_4Pin.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +(embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/BAT54S__32fc1a4b3f.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/BAT54S__32fc1a4b3f.kicad_mod new file mode 100644 index 0000000..8d95319 --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/BAT54S__32fc1a4b3f.kicad_mod @@ -0,0 +1,99 @@ +(footprint "BAT54S__32fc1a4b3f" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -2 0) + (layer "F.SilkS") + (uuid "8ce01a01-bea8-4fbf-8a0b-cd4a741ecd65") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "BAT54S" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "3dc29a40-e9c8-4ba2-9545-0505c90ac2e6") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "6eda879f-8fae-4920-ab17-244b6e77f5ea") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "2fbfa54b-ad19-492b-90c5-0479cc54e894") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Supplier Part Number" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "97c9ebfa-571e-4fcb-8005-bfd28b5e6256") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (fp_poly + (pts + (xy -2.05 -1.5) (xy -1.05 -1.5) (xy -1.05 -1.7) (xy 1.05 -1.7) (xy 1.05 -0.55) (xy 2.05 -0.55) (xy 2.05 0.55) + (xy 1.05 0.55) (xy 1.05 1.7) (xy -1.05 1.7) (xy -1.05 1.5) (xy -2.05 1.5) (xy -2.05 0.39) (xy -1.05 0.39) + (xy -1.05 -0.39) (xy -2.05 -0.39) + ) + (stroke + (width 0.05) + (type default) + ) + (fill no) + (layer "F.CrtYd") + (uuid "30c34bfb-a7c9-4ddc-a3ab-69c6ed673828") + ) + (pad "1" smd rect + (at -1.1375 -0.95) + (size 1.325 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "b451d621-d454-4f35-9117-de61f9ec037c") + ) + (pad "2" smd rect + (at -1.1375 0.95) + (size 1.325 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "c9bf6490-ec5a-4302-a569-32f404457b13") + ) + (pad "3" smd rect + (at 1.1375 0) + (size 1.325 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "ed29a150-8473-4dc8-b439-a95fe75907c8") + ) + (embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/C_0201_0603Metric_A.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/C_0201_0603Metric_A.kicad_mod new file mode 100644 index 0000000..c7edaa0 --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/C_0201_0603Metric_A.kicad_mod @@ -0,0 +1,131 @@ +(footprint "C_0201_0603Metric_A" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -1.099999 0) + (layer "F.SilkS") + (uuid "75c657e8-e439-4bf7-a159-25a42c710f15") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "C_0201" + (at 0 -3 225) + (layer "B.Fab") + (hide yes) + (uuid "750913cd-e98c-4c23-a002-3b4938ea6998") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + (justify mirror) + ) + ) + (property "Datasheet" "" + (at 0 0 225) + (layer "B.Fab") + (hide yes) + (uuid "385fba32-d575-4e8e-89ca-893522cdda7a") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + (justify mirror) + ) + ) + (property "Description" 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b/hardware/courant/deliverables/RadianMain.pretty/C_0805_2012Metric_A.kicad_mod new file mode 100644 index 0000000..c32013b --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/C_0805_2012Metric_A.kicad_mod @@ -0,0 +1,126 @@ +(footprint "C_0805_2012Metric_A" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -1.6 0) + (layer "F.SilkS") + (uuid "889aa00b-0e8a-43ea-ac64-490fa926d511") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "C_0805" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "03f5c07b-9b74-420f-aa65-d74b7d8ffc4f") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "197d7ea9-8f4c-45e8-900b-61e33a8aee5a") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + 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b/hardware/courant/deliverables/RadianMain.pretty/C_1210_3225Metric_Radian.kicad_mod new file mode 100644 index 0000000..4ea6dda --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/C_1210_3225Metric_Radian.kicad_mod @@ -0,0 +1,126 @@ +(footprint "C_1210_3225Metric_Radian" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -2.225 0) + (layer "F.SilkS") + (uuid "c2360251-d5bd-46a1-8238-1fe40962145a") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "C_1210" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "2d9bcaf7-399a-4a74-ae08-614295e05787") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "e6343489-6659-466e-aa54-09a2ea029141") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer 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a/hardware/courant/deliverables/RadianMain.pretty/MCP6561T-E_OT__273f09eb8c.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/MCP6561T-E_OT__273f09eb8c.kicad_mod new file mode 100644 index 0000000..4bca318 --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/MCP6561T-E_OT__273f09eb8c.kicad_mod @@ -0,0 +1,161 @@ +(footprint "MCP6561T-E_OT__273f09eb8c" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -3.04 0) + (layer "F.SilkS") + (uuid "0f6fdc49-1c7c-4e57-b4e0-a8d9b909d974") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "MCP6561T-E/OT" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "89205d77-d811-4790-95d8-adc5ac6a4832") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "683004df-9689-47b5-bb72-8138147c45e8") + (effects + (font + (size 1.27 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) + + (model "${KIPRJMOD}/cad/models/SOT-23-5.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +(embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/Molex_22_23_2021.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/Molex_22_23_2021.kicad_mod new file mode 100644 index 0000000..093d123 --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/Molex_22_23_2021.kicad_mod @@ -0,0 +1,122 @@ +(footprint "Molex_22_23_2021" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -2.54 0) + (layer "F.SilkS") + (uuid "7f8c146b-202f-4632-aa9c-a8c88474746b") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "22-23-2021" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "172e9862-0ffc-41a1-942e-362229beb0ac") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + 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@@ +(footprint "Molex_22_23_2021_RowX" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -2.54 0) + (layer "F.SilkS") + (uuid "7f8c146b-202f-4632-aa9c-a8c88474746b") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "22-23-2021" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "172e9862-0ffc-41a1-942e-362229beb0ac") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "e790f99b-d2d8-441c-bc64-417371476485") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "b4d1ede3-3dc9-403b-a26e-5717e896c25a") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Supplier Part Number" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid 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(uuid "a2a2ff9a-2b0e-49aa-be8d-3240b89cd7e9") + ) + + (model "${KIPRJMOD}/cad/models/Molex_22-23-2021_drawing_reference.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +(embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/Molex_22_23_2021_RowY.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/Molex_22_23_2021_RowY.kicad_mod new file mode 100644 index 0000000..b1ef55d --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/Molex_22_23_2021_RowY.kicad_mod @@ -0,0 +1,122 @@ +(footprint "Molex_22_23_2021_RowY" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -2.54 0) + (layer "F.SilkS") + (uuid "e9973227-7f2d-4457-8d78-21a5ef1c38b3") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "22-23-2021" + (at 0 3 270) + (layer "F.Fab") + (hide yes) + (uuid "005d9517-6a3e-4bb8-90a5-d1a6ce067dec") + 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/dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/Molex_22_23_2061.kicad_mod @@ -0,0 +1,198 @@ +(footprint "Molex_22_23_2061" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -2.54 0) + (layer "F.SilkS") + (uuid "52607895-b3f8-4e97-b312-acb53f3e0325") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "22-23-2061" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "b0258c6f-c2f2-4faf-b3a7-fa23661d92f7") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "6c301c43-7817-4460-8751-5d2459ef897c") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "59dcc29a-f440-431a-abe6-cea0bc591c92") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property 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+++ b/hardware/courant/deliverables/RadianMain.pretty/Nexperia_BAT54S_215_SOT23.kicad_mod @@ -0,0 +1,105 @@ +(footprint "Nexperia_BAT54S_215_SOT23" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -2 0) + (layer "F.SilkS") + (uuid "8ce01a01-bea8-4fbf-8a0b-cd4a741ecd65") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "BAT54S,215" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "3dc29a40-e9c8-4ba2-9545-0505c90ac2e6") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "6eda879f-8fae-4920-ab17-244b6e77f5ea") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "2fbfa54b-ad19-492b-90c5-0479cc54e894") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Supplier Part Number" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "97c9ebfa-571e-4fcb-8005-bfd28b5e6256") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (fp_poly + (pts + (xy -2.05 -1.5) (xy -1.05 -1.5) (xy -1.05 -1.7) (xy 1.05 -1.7) (xy 1.05 -0.55) (xy 2.05 -0.55) (xy 2.05 0.55) + (xy 1.05 0.55) (xy 1.05 1.7) (xy -1.05 1.7) (xy -1.05 1.5) (xy -2.05 1.5) (xy -2.05 0.39) (xy -1.05 0.39) + (xy -1.05 -0.39) (xy -2.05 -0.39) + ) + (stroke + (width 0.05) + (type default) + ) + (fill no) + (layer "F.CrtYd") + (uuid "30c34bfb-a7c9-4ddc-a3ab-69c6ed673828") + ) + (pad "1" smd rect + (at -1.1375 -0.95) + (size 1.325 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "b451d621-d454-4f35-9117-de61f9ec037c") + ) + (pad "2" smd rect + (at -1.1375 0.95) + (size 1.325 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "c9bf6490-ec5a-4302-a569-32f404457b13") + ) + (pad "3" smd rect + (at 1.1375 0) + (size 1.325 0.6) + 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2.225 -0.325) + (size 1.45 0.3) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "3507adf2-0ac2-45da-b8cd-5f8b9b8f7ae2") + ) + (pad "17" smd rect + (at 2.225 -0.975) + (size 1.45 0.3) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "981be796-7d1a-4bc2-9f68-2e624f5d57ab") + ) + (pad "18" smd rect + (at 2.225 -1.625) + (size 1.45 0.3) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "143ba9fa-6878-4400-9076-1a388a72ecb0") + ) + (pad "19" smd rect + (at 2.225 -2.275) + (size 1.45 0.3) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "d2c34026-95dd-4909-8a08-909b792f9c96") + ) + (pad "20" smd rect + (at 2.225 -2.925) + (size 1.45 0.3) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "08f14ab2-09a8-4de0-ab93-fd65bb1b91f7") + ) + (embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/PITCH_CV_GND__251db257b6.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/PITCH_CV_GND__251db257b6.kicad_mod new file mode 100644 index 0000000..d9a06fb --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/PITCH_CV_GND__251db257b6.kicad_mod @@ -0,0 +1,116 @@ +(footprint "PITCH_CV_GND__251db257b6" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -2.54 0) + (layer "F.SilkS") + (uuid "48bbf29e-f01a-42d4-9f09-1b3297461ae6") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "J12" + (at 0 3 90) + (layer "F.Fab") + (hide yes) + (uuid "a2882d06-067c-4c77-9597-e6e0dbb2c985") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "b64ef4a7-29ce-4bb5-ae4d-3ce630a983e1") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "5e20aa4e-6d1d-4b22-acef-b5fbe7af4121") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Supplier Part Number" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "42dca784-a884-4c08-994a-a3b1e5c02797") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (fp_rect + (start -3.04 -1.77) + (end 3.04 1.77) + (stroke + (width 0.05) + (type default) + ) + (fill no) + (layer "F.CrtYd") + (uuid "2480181d-eb60-4001-9d67-dbc1564b1278") + ) + (fp_text user "1" + (at -1.27 -1.35 180) + (layer "F.SilkS") + (uuid "fbcd4fe3-9717-4e51-bb94-d0f2632d7c13") + (effects + (font + (size 0.9 0.9) + (thickness 0.15) + ) + ) + ) + (fp_text user "2" + (at 1.27 -1.35 180) + (layer "F.SilkS") + (uuid "0c4869db-75b5-4911-86dc-531c6978455f") + (effects + (font + (size 0.9 0.9) + (thickness 0.15) + ) + ) + ) + (pad "1" thru_hole rect + (at -1.27 0) + (size 1.5 1.5) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "ae46987e-8d31-40b5-a2d6-5ce3feb204a3") + ) + (pad "2" thru_hole circle + (at 1.27 0 90) + (size 1.5 1.5) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "df17e0a6-a98b-4b3e-986c-9ed52b69eb06") + ) + (embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/POT_DECAY_REF_WIPER_GND__e941a4a611.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/POT_DECAY_REF_WIPER_GND__e941a4a611.kicad_mod new file mode 100644 index 0000000..e445bad --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/POT_DECAY_REF_WIPER_GND__e941a4a611.kicad_mod @@ -0,0 +1,135 @@ +(footprint "POT_DECAY_REF_WIPER_GND__e941a4a611" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -2.54 0) + (layer "F.SilkS") + (uuid "a00f3a5c-9385-424a-8152-2c4e93f3e0ef") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "J7" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "1df81baa-f922-4d8d-ae4e-bf3fb29b8506") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "729e57cc-d6b3-4c69-8140-213da438bac3") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "bf8d457d-4375-4b30-8092-f3af7a5f67a0") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Supplier Part Number" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "213bfb48-9f73-4cd3-94be-8a1c9189ff13") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (fp_rect + (start -4.31 -1.77) + (end 4.31 1.77) + (stroke + (width 0.05) + (type default) + ) + (fill no) + (layer "F.CrtYd") + (uuid "c04a37f4-59e7-4452-919a-5001a8c0b0ab") + ) + (fp_text user "1" + (at -2.54 -1.35 0) + (layer "F.SilkS") + (uuid "cae65009-3b72-4c05-8368-78d083d91af5") + (effects + (font + (size 0.9 0.9) + (thickness 0.15) + ) + ) + ) + (fp_text user "2" + (at 0 -1.35 0) + (layer "F.SilkS") + (uuid "2dcfd05e-6d45-49a3-b73a-b2d4e408048a") + (effects + (font + (size 0.9 0.9) + (thickness 0.15) + ) + ) + ) + (fp_text user "3" + (at 2.54 -1.35 0) + (layer "F.SilkS") + (uuid "1757f2b9-7333-4166-bd76-92b6ce14b60a") + (effects + (font + (size 0.9 0.9) + (thickness 0.15) + ) + ) + ) + (pad "1" thru_hole rect + (at -2.54 0) + (size 1.5 1.5) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "e4a3a2cf-02f3-4ed8-948f-224061e58a9e") + ) + (pad "2" thru_hole circle + (at 0 0) + (size 1.5 1.5) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "c46471cb-b4ea-4aad-8e2a-68796797d30c") + ) + (pad "3" thru_hole circle + (at 2.54 0) + (size 1.5 1.5) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "064a8c3c-91d0-469c-92d0-2669e993a7a0") + ) + (embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/README.md b/hardware/courant/deliverables/RadianMain.pretty/README.md new file mode 100644 index 0000000..9c8a800 --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/README.md @@ -0,0 +1,7 @@ +Project-local production footprint snapshot for the canonical RADIAN mainboard. + +The native board is authoritative. The library now uses semantic package/part identities instead of generator-era aliases while preserving the proven board geometry. All BOM placements carry Manufacturer/MPN metadata and a project-local 3D model. + +Routing reconciliation rule: copper, vias, footprint placement/orientation, pad positions/sizes/nets/layers are preserved. The only intentional package-geometry change in the 2026-09-18 exact-part pass is J1–J4 Molex KK-254 drill diameter 1.00 -> 1.02 mm plus corrected connector courtyards. Geometry variants such as the existing 0201/0805/1210 artwork variants remain separate library footprints so native instances match their library copies exactly. + +J1/J3/J4 are Molex 22-23-2021; J2 is Molex 22-23-2061; J17/J18 are Samtec IPT1-110-06-L-D. Molex and Samtec connector STEP solids in this project are drawing-derived reference geometry, not vendor-supplied STEP files. Standard IC/passive package models are project-local copies of package-accurate KiCad STEP assets. This is not a substitute for first-article fit, solderability, thermal, power, or functional qualification. diff --git a/hardware/courant/deliverables/RadianMain.pretty/REF3125AIDBZR_SOT23.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/REF3125AIDBZR_SOT23.kicad_mod new file mode 100644 index 0000000..c88975b --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/REF3125AIDBZR_SOT23.kicad_mod @@ -0,0 +1,105 @@ +(footprint "REF3125AIDBZR_SOT23" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -2 0) + (layer "F.SilkS") + (uuid "8ce01a01-bea8-4fbf-8a0b-cd4a741ecd65") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "REF3125AIDBZR" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "3dc29a40-e9c8-4ba2-9545-0505c90ac2e6") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "6eda879f-8fae-4920-ab17-244b6e77f5ea") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "2fbfa54b-ad19-492b-90c5-0479cc54e894") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Supplier Part Number" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "97c9ebfa-571e-4fcb-8005-bfd28b5e6256") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (fp_poly + (pts + (xy -2.05 -1.5) (xy -1.05 -1.5) (xy -1.05 -1.7) (xy 1.05 -1.7) (xy 1.05 -0.55) (xy 2.05 -0.55) (xy 2.05 0.55) + (xy 1.05 0.55) (xy 1.05 1.7) (xy -1.05 1.7) (xy -1.05 1.5) (xy -2.05 1.5) (xy -2.05 0.39) (xy -1.05 0.39) + (xy -1.05 -0.39) (xy -2.05 -0.39) + ) + (stroke + (width 0.05) + (type default) + ) + (fill no) + (layer "F.CrtYd") + (uuid "30c34bfb-a7c9-4ddc-a3ab-69c6ed673828") + ) + (pad "1" smd rect + (at -1.1375 -0.95) + (size 1.325 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "b451d621-d454-4f35-9117-de61f9ec037c") + ) + (pad "2" smd rect + (at -1.1375 0.95) + (size 1.325 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "c9bf6490-ec5a-4302-a569-32f404457b13") + ) + (pad "3" smd rect + (at 1.1375 0) + (size 1.325 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "ed29a150-8473-4dc8-b439-a95fe75907c8") + ) + + (model "${KIPRJMOD}/cad/models/SOT-23.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +(embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/RESET_GND__232228838d.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/RESET_GND__232228838d.kicad_mod new file mode 100644 index 0000000..5f90757 --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/RESET_GND__232228838d.kicad_mod @@ -0,0 +1,116 @@ +(footprint "RESET_GND__232228838d" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -2.54 0) + (layer "F.SilkS") + (uuid "7f8c146b-202f-4632-aa9c-a8c88474746b") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "J4" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "172e9862-0ffc-41a1-942e-362229beb0ac") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "e790f99b-d2d8-441c-bc64-417371476485") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "b4d1ede3-3dc9-403b-a26e-5717e896c25a") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Supplier Part Number" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "deb5561a-d3ca-429c-b820-1744d8620adb") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (fp_rect + (start -3.04 -1.77) + (end 3.04 1.77) + (stroke + (width 0.05) + (type default) + ) + (fill no) + (layer "F.CrtYd") + (uuid "79835873-ba34-4d8f-9afd-40f37bf317c5") + ) + (fp_text user "1" + (at -1.27 -1.35 0) + (layer "F.SilkS") + (uuid "6e1a3643-3900-405a-95b1-2cef6146214d") + (effects + (font + (size 0.9 0.9) + (thickness 0.15) + ) + ) + ) + (fp_text user "2" + (at 1.27 -1.35 0) + (layer "F.SilkS") + (uuid "7ba61e84-c6c1-43c5-adee-8188a20b6759") + (effects + (font + (size 0.9 0.9) + (thickness 0.15) + ) + ) + ) + (pad "1" thru_hole rect + (at -1.27 0) + (size 1.5 1.5) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "a1b2e704-e858-44cb-9d1f-d4a0dcdbb003") + ) + (pad "2" thru_hole circle + (at 1.27 0) + (size 1.5 1.5) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "a2a2ff9a-2b0e-49aa-be8d-3240b89cd7e9") + ) + (embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/R_0603_1608Metric_Radian.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/R_0603_1608Metric_Radian.kicad_mod new file mode 100644 index 0000000..6fd5449 --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/R_0603_1608Metric_Radian.kicad_mod @@ -0,0 +1,116 @@ +(footprint "R_0603_1608Metric_Radian" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -1.375 0) + (layer "F.SilkS") + (uuid "3aab4b50-22c1-4325-9393-2d6fd9de33fa") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "R_0603" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "b12d5093-deea-4ae7-8661-a44c0360bb78") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "97e49887-d6c5-41c8-8551-8686b8fd4f95") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "b3a96416-0c95-450b-a20c-0e87d762f870") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Supplier Part Number" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "2a6a704b-76c9-4f37-97dd-04e267686fe4") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start -0.237258 -0.5225) + (end 0.237258 -0.5225) + (stroke + (width 0.12) + (type default) + ) + (layer "F.SilkS") + (uuid "fd164550-deb5-4fbe-8fb1-37319f4bc3e0") + ) + (fp_line + (start -0.237258 0.5225) + (end 0.237258 0.5225) + (stroke + (width 0.12) + (type default) + ) + (layer "F.SilkS") + (uuid "234164d8-be58-4986-b665-e155618de464") + ) + (fp_rect + (start -1.48 -0.73) + (end 1.48 0.73) + (stroke + (width 0.05) + (type default) + ) + (fill no) + (layer "F.CrtYd") + (uuid "34ee8932-2394-4a4a-89bc-bee9e468f86d") + ) + (pad "1" smd rect + (at -0.825 0) + (size 0.8 0.95) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "672b30bc-257d-46f3-9b43-83102a3cf2ae") + ) + (pad "2" smd rect + (at 0.825 0) + (size 0.8 0.95) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "d87ee792-b7c9-4d3b-9b08-887bae9b48ef") + ) + + (model "${KIPRJMOD}/cad/models/R_0603_1608Metric.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +(embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/STEREO_LINE_OUT_L_G_R__812a81a5dc.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/STEREO_LINE_OUT_L_G_R__812a81a5dc.kicad_mod new file mode 100644 index 0000000..58e146d --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/STEREO_LINE_OUT_L_G_R__812a81a5dc.kicad_mod @@ -0,0 +1,135 @@ +(footprint "STEREO_LINE_OUT_L_G_R__812a81a5dc" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -2.54 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"REF**" + (at 0 -2.225 0) + (layer "F.SilkS") + (uuid "c2360251-d5bd-46a1-8238-1fe40962145a") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "47uF" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "2d9bcaf7-399a-4a74-ae08-614295e05787") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "e6343489-6659-466e-aa54-09a2ea029141") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "cf73dfd0-bd74-470f-99be-99336cb3e9d1") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Supplier Part Number" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "d6de00ca-76df-41d3-8fb2-893d4ac5e607") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start -2.225 -1.725) + (end -2.225 1.725) + (stroke + (width 0.1) + (type default) + ) + (layer "F.SilkS") + (uuid "ead09e44-d2ed-4e3e-93c4-8f784d249bc8") + ) + (fp_line + (start -2.225 1.725) + (end 1.4625 1.725) + (stroke + (width 0.1) + (type default) + ) + (layer "F.SilkS") + (uuid "63b9b49e-cb89-4837-ad95-f48624ed8c51") + ) + (fp_line + (start 1.4625 -1.725) + (end -2.225 -1.725) + (stroke + (width 0.1) + (type default) + ) + (layer "F.SilkS") + (uuid "fb9fae8b-385a-4e20-b9ce-2fe2569a3438") + ) + (fp_rect + (start -2.28 -1.58) + (end 2.28 1.58) + (stroke + (width 0.05) + (type default) + ) + (fill no) + (layer "F.CrtYd") + (uuid "3da7ca4b-7e61-4c14-ab06-b204540ccadd") + ) + (pad "1" smd rect + (at -1.4625 0) + (size 1.125 2.65) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "a3669aeb-f42d-4daf-b3e6-d8ceaada1449") + ) + (pad "2" smd rect + (at 1.4625 0) + (size 1.125 2.65) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "f6131a62-dffa-4a7f-bef9-a126573249e6") + ) + (embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/capacitor_cap1210__6451707d90.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/capacitor_cap1210__6451707d90.kicad_mod new file mode 100644 index 0000000..e19eb17 --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/capacitor_cap1210__6451707d90.kicad_mod @@ -0,0 +1,120 @@ +(footprint "capacitor_cap1210__6451707d90" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 3.5 2.475 0) + (layer "F.SilkS") + (uuid "77705386-448f-4ad0-9e58-cbdfa8f39385") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "47uF" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "1323f200-9ae3-4b1e-89f3-ce9853d698b0") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "e532bdb0-539f-4804-95e4-aa6b688ae04a") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "34f5ec37-5707-4276-a6b7-4416a4f7e16c") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Supplier Part Number" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "0c9a58f9-bc44-430e-ba58-4e52e67297ee") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start -2.225 -1.725) + (end -2.225 1.725) + (stroke + (width 0.1) + (type default) + ) + (layer "F.SilkS") + (uuid "dfd6ae03-9fb6-4ccc-af34-ed5bfc1a2dea") + ) + (fp_line + (start 1.4625 -1.725) + (end -2.225 -1.725) + (stroke + (width 0.1) + (type default) + ) + (layer "F.SilkS") + (uuid "53a53feb-4018-452b-b9ed-878d3f695569") + ) + (fp_rect + (start -2.28 -1.58) + (end 2.28 1.58) + (stroke + (width 0.05) + (type default) + ) + (fill no) + (layer "F.CrtYd") + (uuid "a61dc4c4-4bc8-4815-b30d-bbf9c542f294") + ) + (fp_line + (start -2.225 1.725) + (end 1.4625 1.725) + (stroke + (width 0.1) + (type default) + ) + (layer "F.Fab") + (uuid "6629ffa6-110e-40f7-9ab0-7205fda686e3") + ) + (pad "1" smd rect + (at -1.4625 0) + (size 1.125 2.65) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "35c92de0-84aa-4f6e-a3ce-ab6648bf9287") + ) + (pad "2" smd rect + (at 1.4625 0) + (size 1.125 2.65) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "e6ebf892-cf04-4586-a13e-dc34d3765670") + ) + (embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/hole_circle_holeDiameter3.2mm__6815d6f763.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/hole_circle_holeDiameter3.2mm__6815d6f763.kicad_mod new file mode 100644 index 0000000..aa34daa --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/hole_circle_holeDiameter3.2mm__6815d6f763.kicad_mod @@ -0,0 +1,57 @@ +(footprint "hole_circle_holeDiameter3.2mm__6815d6f763" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 0 0) + (layer "F.SilkS") + (uuid "e2872c99-7452-4aa9-a3b2-81b5396ef6ad") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "" + (at 0 0 0) + (layer "F.Fab") + (uuid "8176529b-57f4-4b41-a8a2-7ec5f4570fd8") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "0854c6e5-ad78-4f99-aa0c-2977e7c074db") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "be0ac2cc-9a29-4819-8ac6-b34bc1292559") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (pad "" np_thru_hole circle + (at 0 0) + (size 3.2 3.2) + (drill 3.2) + (layers "*.Cu" "*.Mask") + (uuid "e54ead7a-d07a-43d5-ba7c-a533b2101404") + ) + (embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/inductor__e5f50d491f.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/inductor__e5f50d491f.kicad_mod new file mode 100644 index 0000000..ffdb81c --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/inductor__e5f50d491f.kicad_mod @@ -0,0 +1,131 @@ +(footprint "inductor__e5f50d491f" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -3 0) + (layer "F.SilkS") + (hide yes) + (uuid "17c6c093-8762-4525-9060-053f8866b28c") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Value" "1µH" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "3a616862-e1ff-492f-92e3-51204dde082c") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "503f41d3-f2f4-4b2f-99f0-284a466c62ef") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "6bee5682-0dd7-4161-8b8c-92d39de27e9f") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Supplier Part Number" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "95b8f00f-5ce9-40b1-a7c3-c0bcef11b3bd") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start -2 -2) + (end 2 -2) + (stroke + (width 0.12) + (type default) + ) + (layer "F.SilkS") + (uuid "6f2e57ed-65e5-4937-bc50-a4277fd62584") + ) + (fp_line + (start 2 2) + (end -2 2) + (stroke + (width 0.12) + (type default) + ) + (layer "F.SilkS") + (uuid "664dc861-6022-40c2-89de-8793664f7f25") + ) + (fp_rect + (start -2.6 -2.25) + (end 2.6 2.25) + (stroke + (width 0.05) + (type default) + ) + (fill no) + (layer "F.CrtYd") + (uuid "3f8327d3-826e-41e2-a07a-8e714c233a21") + ) + (fp_line + (start -2 2) + (end -2 -2) + (stroke + (width 0.12) + (type default) + ) + (layer "F.Fab") + (uuid "4470a4ca-58e4-46b9-9ae8-ef9fd640b408") + ) + (fp_line + (start 2 -2) + (end 2 2) + (stroke + (width 0.12) + (type default) + ) + (layer "F.Fab") + (uuid "699620cf-f355-4a10-b135-3060c3a06b84") + ) + (pad "1" smd rect + (at -1.7 0) + (size 1.3 3.7) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "b75bd5d2-fb84-458e-8a71-c131cf6dc640") + ) + (pad "2" smd rect + (at 1.7 0) + (size 1.3 3.7) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "1f8e1a73-a31c-40aa-8fba-a36d2c0599ec") + ) + (embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/resistor_res0603__39c83d2b18.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/resistor_res0603__39c83d2b18.kicad_mod new file mode 100644 index 0000000..5a323b2 --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/resistor_res0603__39c83d2b18.kicad_mod @@ -0,0 +1,110 @@ +(footprint "resistor_res0603__39c83d2b18" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -1.375 0) + (layer "F.SilkS") + (uuid "3aab4b50-22c1-4325-9393-2d6fd9de33fa") + (effects + (font + (size 0.8 0.8) + (thickness 0.15) + ) + ) + ) + (property "Value" "4.7kΩ" + (at 0 3 0) + (layer "F.Fab") + (hide yes) + (uuid "b12d5093-deea-4ae7-8661-a44c0360bb78") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "97e49887-d6c5-41c8-8551-8686b8fd4f95") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "b3a96416-0c95-450b-a20c-0e87d762f870") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Supplier Part Number" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "2a6a704b-76c9-4f37-97dd-04e267686fe4") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start -0.237258 -0.5225) + (end 0.237258 -0.5225) + (stroke + (width 0.12) + (type default) + ) + (layer "F.SilkS") + (uuid "fd164550-deb5-4fbe-8fb1-37319f4bc3e0") + ) + (fp_line + (start -0.237258 0.5225) + (end 0.237258 0.5225) + (stroke + (width 0.12) + (type default) + ) + (layer "F.SilkS") + (uuid "234164d8-be58-4986-b665-e155618de464") + ) + (fp_rect + (start -1.48 -0.73) + (end 1.48 0.73) + (stroke + (width 0.05) + (type default) + ) + (fill no) + (layer "F.CrtYd") + (uuid "34ee8932-2394-4a4a-89bc-bee9e468f86d") + ) + (pad "1" smd rect + (at -0.825 0) + (size 0.8 0.95) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "672b30bc-257d-46f3-9b43-83102a3cf2ae") + ) + (pad "2" smd rect + (at 0.825 0) + (size 0.8 0.95) + (layers "F.Cu" "F.Mask" "F.Paste") + (uuid "d87ee792-b7c9-4d3b-9b08-887bae9b48ef") + ) + (embedded_fonts no) +) diff --git a/hardware/courant/deliverables/RadianMain.pretty/smtpad_circle_diameter1mm__18e3aa3a2a.kicad_mod b/hardware/courant/deliverables/RadianMain.pretty/smtpad_circle_diameter1mm__18e3aa3a2a.kicad_mod new file mode 100644 index 0000000..da6511b --- /dev/null +++ b/hardware/courant/deliverables/RadianMain.pretty/smtpad_circle_diameter1mm__18e3aa3a2a.kicad_mod @@ -0,0 +1,57 @@ +(footprint "smtpad_circle_diameter1mm__18e3aa3a2a" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 0 0) + (layer "F.SilkS") + (uuid "73974bb2-bdee-4f5f-9152-def10ea9d4c9") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "" + (at 0 0 0) + (layer "F.Fab") + (uuid "d9cddb42-d99c-47d9-a27e-df4eb37b6c5a") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "5fe9d41a-fb5b-4f3c-91a2-69536774397c") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "a7697dc9-a574-49d1-8022-ccf066fed153") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (pad "1" smd circle + (at 0 0) + (size 1 1) + (layers "F.Cu" "F.Mask") + (solder_mask_margin 1) + (uuid "19f818dd-bf4b-42bd-86ce-1fce38fe44db") + ) + (embedded_fonts no) +) diff --git a/hardware/courant/deliverables/courant-bom.csv b/hardware/courant/deliverables/courant-bom.csv new file mode 100644 index 0000000..f79cf17 --- /dev/null +++ b/hardware/courant/deliverables/courant-bom.csv @@ -0,0 +1,55 @@ +Reference(s),Qty,Value,Footprint,Side,Manufacturer,MPN,LCSC,Notes +"C101,C102,C106,C107,C108,C109,C112,C114,C115,C118,C119,C121,C124,C125,C126,C127,C136",17,100nF,RadianMain:C_0201_0603Metric_D,bottom,CCTC,TCC0201X5R104K100ZT,C5142565,10 V X5R. JLC extended library: one setup fee for the whole array +"C11,C21,C31,C146,C150,C151,C152,C161,C162,C166,C170,C172,C190,C195,C200",15,100nF,RadianMain:C_0603_1608Metric_Radian,top,Samsung,CL10B104KB8NNNC,C1591,50 V X7R +"R12,R22,R32,R103,R104,R105,R106,R121,R130,R143,R144,R145,R146,R169",14,10kΩ,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-0710KL,C98220,thick film 1% +"R131,R132,R133,R140,R141,R142,R147,R148,R149,R150,R190,R191,R192",13,1kΩ,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-071KL,,thick film 1% +"C100,C103,C104,C110,C113,C116,C120,C122,C128",9,100nF,RadianMain:C_0201_0603Metric_C,bottom,CCTC,TCC0201X5R104K100ZT,C5142565,10 V X5R. JLC extended library: one setup fee for the whole array +"C105,C123,C130,C131,C132,C133,C134,C135",8,100nF,RadianMain:C_0201_0603Metric_E,bottom,CCTC,TCC0201X5R104K100ZT,C5142565,10 V X5R. JLC extended library: one setup fee for the whole array +"C174,C175,C176,C180,C181,C182,C193,C194",8,10nF,RadianMain:C_0603_1608Metric_Radian,top,Murata,GRM1885C1H103JA01D,C85973,"50 V C0G -- ADC anti-alias, C0G for low voltage coefficient" +"R110,R114,R115,R122,R123,R124,R125",7,33Ω,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-0733RL,,thick film 1% +"R100,R101,R102,R111,R112,R113",6,4.7kΩ,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-074K7L,,thick film 1% +"R11,R21,R31,R166",4,100kΩ,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-07100KL,,thick film 1% +"C10,C20,C30,C160",4,10uF,RadianMain:C_0805_2012Metric_B,top,Samsung,CL21A106KAYNNNE,C15850,"25 V X5R, JLC basic library" +"R160,R161,R163,R164",4,20kΩ,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RT0603BRD0720KL,C723637,"0.1%, 25 ppm/C thin film -- matched CV divider pair" +"C111,C117,C129",3,100nF,RadianMain:C_0201_0603Metric_A,bottom,CCTC,TCC0201X5R104K100ZT,C5142565,10 V X5R. JLC extended library: one setup fee for the whole array +"C201,C202,C203",3,10nF,RadianMain:C_0603_1608Metric_Radian,bottom,Murata,GRM1885C1H103JA01D,C85973,"50 V C0G -- ADC anti-alias, C0G for low voltage coefficient" +"C191,C192,C196",3,1nF,RadianMain:C_0603_1608Metric_Radian,top,Murata,GRM1885C1H102JA01D,,"50 V C0G, same series as the 10 nF" +"C165,C171,C173",3,1uF,RadianMain:C_0603_1608Metric_Radian,top,Samsung,CL10B105KB8NQNC,C5199872,50 V X7R +"L1,L2,L3",3,1µH,RadianMain:Changjiang_FNR4030S1R0MT,top,Changjiang Electronics,FNR4030S1R0MT,C167865,"4x4 mm shielded, 18 mOhm, 5.7 A sat -- must exceed the TPS62130's 3 A plus ripple" +"C13,C23,C33",3,22uF,RadianMain:C_0805_2012Metric_B,top,Samsung,CL21A226MAQNNNE,C45783,"25 V X5R, JLC basic library -- switcher output" +"C12,C22,C32",3,22uF,RadianMain:C_0805_2012Metric_A,top,Samsung,CL21A226MAQNNNE,C45783,"25 V X5R, JLC basic library -- switcher output" +"C14,C24,C34",3,3.3nF,RadianMain:C_0603_1608Metric_Radian,top,Murata,GRM1885C1H332JA01D,,50 V C0G -- switcher soft-start +"C1,C140,C141",3,47uF,RadianMain:C_1210_3225Metric_A,top,Murata,GRM32ER61C476KE15L,C77101,16 V X5R -- bulk input +"D10,D11,D12",3,BAT54S,RadianMain:Nexperia_BAT54S_215_SOT23,top,Nexperia,"BAT54S,215",,"Nexperia BAT54S,215; SOT-23 dual Schottky diode" +"U11,U12,U13",3,TPS62130ARGTR,RadianMain:TPS62130ARGTR_WQFN16,top,Texas Instruments,TPS62130ARGTR,,"3 A buck, QFN-16 with exposed pad" +"R162,R165",2,100Ω,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-07100RL,,thick film 1% +"C167,C168",2,2.2nF,RadianMain:C_0603_1608Metric_Radian,top,Murata,GRM1885C1H222JA01D,,"50 V C0G, same series" +"C163,C164",2,2.2uF,RadianMain:C_0603_1608Metric_Radian,top,Samsung,CL10A225KO8NNNC,C23630,"16 V X5R, JLC basic library" +"C143,C144",2,4.7uF,RadianMain:C_0805_2012Metric_B,top,Yageo,CC0805KKX7R8BB475,C354262,25 V X7R +"R126,R127",2,470Ω,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-07470RL,,thick film 1% +"J17,J18",2,IPT1-110-06-L-D,RadianMain:Samtec_IPT1_110_06_L_D,top,Samtec,IPT1-110-06-L-D,,2x10 2.54 mm vertical through-hole terminal strip; mates IPS1-110-01-L-D. Fully-mated PCB gap 19.99 mm; 20.45 mm max. +C137,1,100nF,RadianMain:C_0201_0603Metric_B,bottom,CCTC,TCC0201X5R104K100ZT,C5142565,10 V X5R. JLC extended library: one setup fee for the whole array +R20,1,124kΩ,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-07124KL,,thick film 1% +D20,1,1N4148W,RadianMain:Diodes_1N4148W_7_F_SOD123,top,Diodes Incorporated,1N4148W-7-F,,Diodes Incorporated 1N4148W-7-F; SOD-123 fast switching diode +"J4,J3",2,22-23-2021,RadianMain:Molex_22_23_2021_RowX,top,Molex,22-23-2021,,KK 254 vertical friction-lock. Harness side: housing 22-01-3027 + 2 x 08-55-0102 crimp terminals +J1,1,22-23-2021,RadianMain:Molex_22_23_2021_RowY,top,Molex,22-23-2021,,KK 254 vertical friction-lock. Harness side: housing 22-01-3027 + 2 x 08-55-0102 crimp terminals +J2,1,22-23-2061,RadianMain:Molex_22_23_2061,top,Molex,22-23-2061,,KK 254 vertical friction-lock. Harness side: housing 22-01-3067 + 6 x 08-55-0102 crimp terminals +R120,1,1Ω,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-071RL,,thick film 1% +R181,1,2.2kΩ,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-072K2L,,thick film 1% +R180,1,220Ω,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-07220RL,,thick film 1% +R10,1,24.9kΩ,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-0724K9L,C137761,thick film 1% +R30,1,316kΩ,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-07316KL,,thick film 1% +R167,1,33kΩ,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-0733KL,,thick film 1% +C145,1,4.7uF,RadianMain:C_0805_2012Metric_A,top,Yageo,CC0805KKX7R8BB475,C354262,25 V X7R +R168,1,40.2kΩ,RadianMain:R_0603_1608Metric_Radian,top,Yageo,RC0603FR-0740K2L,,thick film 1% +C142,1,47uF,RadianMain:C_1210_3225Metric_B,top,Murata,GRM32ER61C476KE15L,C77101,16 V X5R -- bulk input +Y1,1,ASE-100.000MHZ-LC-T,RadianMain:Abracon_ASE_3225_4Pin,top,Abracon,ASE-100.000MHZ-LC-T,,100 MHz system oscillator +Y2,1,ASE-12.288MHZ-LC-T,RadianMain:Abracon_ASE_3225_4Pin,top,Abracon,ASE-12.288MHZ-LC-T,,12.288 MHz audio master clock +U8,1,H11L1M,RadianMain:H11L1M_DIP6,top,onsemi,H11L1M,,"Schmitt optocoupler, MIDI input" +U4,1,MCP3208-CI/SL,RadianMain:MCP3208_CI_SL_SOIC16,top,Microchip,MCP3208-CI/SL,,8-ch 12-bit SPI ADC +U6,1,MCP6002-I/SN,RadianMain:MCP6002_I_SN_SOIC8,top,Microchip,MCP6002-I/SN,,"dual op-amp, CV buffer" +U7,1,MCP6561T-E/OT,RadianMain:MCP6561T_E_OT_SOT23_5,top,Microchip,MCP6561T-E/OT,,"comparator, gate input" +U3,1,PCM5102APWR,RadianMain:PCM5102APWR_TSSOP20,top,Texas Instruments,PCM5102APWR,,stereo audio DAC +U5,1,REF3125AIDBZR,RadianMain:REF3125AIDBZR_SOT23,top,Texas Instruments,REF3125AIDBZR,,2.5 V reference +U2,1,W25Q64JVSSIQ,RadianMain:W25Q64JVSSIQ_SOIC8_208mil,top,Winbond,W25Q64JVSSIQ,,64 Mbit SPI flash +U1,1,XC7A50T-1FTG256I,RadianMain:XC7A50T_1FTG256I_FTG256,top,AMD/Xilinx,XC7A50T-1FTG256I,C3272410,"FPGA, 52160 logic cells, industrial temp" diff --git a/hardware/courant/deliverables/courant-eurorack.md b/hardware/courant/deliverables/courant-eurorack.md new file mode 100644 index 0000000..37f8f39 --- /dev/null +++ b/hardware/courant/deliverables/courant-eurorack.md @@ -0,0 +1,97 @@ +# Courant Rev A — Eurorack status + +Everything below is measured against the board as routed, not against an +intention. Where a change is needed the values are computed, not estimated. + +| | Status | +| --- | --- | +| Mechanical | **done** — RADIAN Rev F.1 gives a 40 HP panel, DXF through-cuts, STLs and a desktop dock | +| Gate input | **works as built** | +| Power | **works if the case supplies +5 V** — no board change, see below | +| Pitch/mod CV | **partial** — 0–5 V only; one resistor per channel fixes bipolar | +| Audio level | **line, not modular** — the one item needing new circuitry | + +## Gate — no change + +R166/R167 divide by 0.2481 against a comparator reference of +2.5 × 10/50.2 = 0.498 V, so the rising threshold at the jack is **2.01 V**. The +BAT54S only conducts above (3.3 + 0.3)/0.2481 ≈ **14.5 V** at the jack. Both +5 V and 10 V Eurorack gates are inside that with room to spare. + +## Power — probably no change either + +The Doepfer 16-pin bus carries **+5 V**, not only ±12 V. J1 needs +5 V and GND +and nothing else, so an adapter cable from the bus header to J1's 2-pin KK 254 +housing is sufficient — **no board modification**. + +`design.ts` specifies "5 V / 3 A", which would be beyond most Eurorack +5 V +rails, but that is headroom, not draw. Estimating from the actual load: + +``` +VCCINT 1.0 V ~0.5 A 0.50 W +VCCAUX 1.8 V ~50 mA 0.09 W +VCCO 3.3 V + codec, ADC, flash 0.65 W + out 1.24 W + in, at ~85% buck 1.5 W = about 0.30 A at 5 V +``` + +**~300 mA is comfortable for a typical +5 V rail.** Treat it as an estimate +until a real board is measured — that is the single number that settles this. + +Two things the adapter cable must carry, because the board has neither: a +**fuse** and **reverse-polarity protection**. A series Schottky costs 0.3 V of +the 5 V headroom, which the 3–17 V TPS62130 input range absorbs without +complaint. + +Do **not** feed +12 V to J1. The regulators would tolerate it, but R12/R22 pull +the power-good pins to that rail and drive the next regulator's EN input, whose +absolute maximum has not been checked here, and C1 is a 16 V part. + +## Pitch and mod CV — one resistor per channel + +As built: R160 20 k from the jack, R161 20 k to ground, ÷2 into a 0–2.5 V ADC. +That is **0–5 V unipolar, 40 kΩ input impedance**, five octaves at 1 V/oct. +Negative input clamps at −0.6 V. + +**For ±5 V bipolar** — add one resistor per channel from `VREF25` to the +existing divider node. R160 and R161 are unchanged: + +``` +R_offset = 10 kΩ (VREF25 -> the R160/R161 junction) + + -5 V in -> 0.000 V at the ADC + 0 V in -> 1.250 V + +5 V in -> 2.500 V + +input impedance 26.7 kΩ; VREF25 load 125 uA per channel +``` + +Exact, with no change to the buffer or the clamps. The REF3125 sources 10 mA, +so 250 µA for both channels is nothing. + +**For 0–10 V unipolar** instead, change R160 from 20 k to **60.4 kΩ** (E96): +ratio 0.2488, full scale at 10.05 V, input impedance 80.4 kΩ. + +Both are BOM changes on existing footprints — the bipolar option needs two new +0603 placements, which is local placement and a few millimetres of track, not +a re-route. + +## Audio — the one real addition + +The PCM5102A gives about 2.1 Vrms (5.9 Vpp). Eurorack runs ~10 Vpp, so the +board is **4.5 dB quiet**. Closing that needs a gain of 1.69 and a supply that +can swing to ±5 V; the board has only 3.3 V. That means a bipolar rail or a +charge pump and an output stage — genuinely new circuitry, unlike everything +else on this page. + +Worth asking whether it matters. Plenty of Eurorack modules output line level +and are simply turned up. If modular level is a requirement, it belongs in +Rev B alongside the CV change. + +## What this adds up to + +Nothing here touches the FPGA, the ball field or the routed copper. The +mechanical design exists. Gate works. Power works with a cable, if the case has ++5 V. CV is one resistor per channel away from bipolar. Only the output level +would need a new circuit block, and only if you want modular level rather than +line level. diff --git a/hardware/courant/deliverables/courant-netlist.txt b/hardware/courant/deliverables/courant-netlist.txt new file mode 100644 index 0000000..051ff77 --- /dev/null +++ b/hardware/courant/deliverables/courant-netlist.txt @@ -0,0 +1,819 @@ +Current repaired native board: courant.kicad_pcb +102 nets + +A3V3 (6) + C160.1 + C161.1 + C162.1 + R120.2 + U3.1 + U3.8 + +CLK100_RAW (2) + R114.1 + Y1.3 + +DAC_CAPM (2) + C163.2 + U3.4 + +DAC_CAPP (2) + C163.1 + U3.2 + +DAC_L (2) + R126.1 + U3.6 + +DAC_LDO (2) + C165.1 + U3.18 + +DAC_R (2) + R127.1 + U3.7 + +DAC_VNEG (2) + C164.1 + U3.5 + +DONE (2) + R101.1 + U1.122 + +ENC_A_RAW (2) + J18.4 + R140.1 + +ENC_B_RAW (2) + J18.5 + R141.1 + +ENC_SW_RAW (2) + J18.6 + R142.1 + +FB1 (3) + R10.2 + R11.1 + U11.5 + +FB2 (3) + R20.2 + R21.1 + U12.5 + +FB3 (3) + R30.2 + R31.1 + U13.5 + +FLASH_CLK (2) + R110.2 + U2.6 + +FLASH_CLK_RAW (2) + R110.1 + U1.72 + +FLASH_CS (3) + R111.1 + U1.172 + U2.1 + +FLASH_HOLD (3) + R113.1 + U1.160 + U2.7 + +FLASH_MISO (2) + U1.142 + U2.2 + +FLASH_MOSI (2) + U1.141 + U2.5 + +FLASH_WP (3) + R112.1 + U1.159 + U2.3 + +GATE_DIV (5) + C196.1 + D12.3 + R166.2 + R167.1 + U7.3 + +GATE_IN (2) + J17.15 + R166.1 + +GATE_REF (3) + R168.2 + R169.1 + U7.4 + +GND (190) + C1.2 + C10.2 + C100.2 + C101.2 + C102.2 + C103.2 + C104.2 + C105.2 + C106.2 + C107.2 + C108.2 + C109.2 + C11.2 + C110.2 + C111.2 + C112.2 + C113.2 + C114.2 + C115.2 + C116.2 + C117.2 + C118.2 + C119.2 + C12.2 + C120.2 + C121.2 + C122.2 + C123.2 + C124.2 + C125.2 + C126.2 + C127.2 + C128.2 + C129.2 + C13.2 + C130.2 + C131.2 + C132.2 + C133.2 + C134.2 + C135.2 + C136.2 + C137.2 + C14.2 + C140.2 + C141.2 + C142.2 + C143.2 + C144.2 + C145.2 + C146.2 + C150.2 + C151.2 + C152.2 + C160.2 + C161.2 + C162.2 + C164.2 + C165.2 + C166.2 + C167.2 + C168.2 + C170.2 + C171.2 + C172.2 + C173.2 + C174.2 + C175.2 + C176.2 + C180.2 + C181.2 + C182.2 + C190.2 + C191.2 + C192.2 + C193.2 + C194.2 + C195.2 + C196.2 + C20.2 + C200.2 + C201.2 + C202.2 + C203.2 + C21.2 + C22.2 + C23.2 + C24.2 + C30.2 + C31.2 + C32.2 + C33.2 + C34.2 + D10.1 + D11.1 + D12.1 + J1.2 + J17.1 + J17.12 + J17.16 + J17.18 + J17.20 + J17.5 + J18.1 + J18.12 + J18.3 + J2.2 + J3.2 + J4.2 + R105.2 + R11.2 + R121.2 + R146.2 + R161.2 + R164.2 + R167.2 + R169.2 + R21.2 + R31.2 + U1.1 + U1.103 + U1.105 + U1.109 + U1.11 + U1.118 + U1.119 + U1.120 + U1.135 + U1.136 + U1.137 + U1.139 + U1.148 + U1.150 + U1.158 + U1.161 + U1.171 + U1.184 + U1.186 + U1.187 + U1.197 + U1.207 + U1.210 + U1.220 + U1.233 + U1.24 + U1.246 + U1.256 + U1.37 + U1.47 + U1.50 + U1.60 + U1.73 + U1.86 + U1.88 + U1.90 + U1.96 + U1.99 + U11.15 + U11.16 + U11.17 + U11.6 + U11.7 + U11.8 + U12.15 + U12.16 + U12.17 + U12.6 + U12.7 + U12.8 + U13.15 + U13.16 + U13.17 + U13.6 + U13.7 + U13.8 + U2.4 + U3.10 + U3.11 + U3.16 + U3.19 + U3.3 + U3.9 + U4.14 + U4.9 + U5.3 + U6.4 + U7.2 + U8.5 + Y1.2 + Y2.2 + +I2S_BCLK (2) + R123.2 + U3.13 + +I2S_DATA (2) + R125.2 + U3.14 + +I2S_LRCLK (2) + R124.2 + U3.15 + +I2S_MCLK (2) + R122.2 + U3.12 + +INIT_B (2) + R100.1 + U1.154 + +JTAG_TCK (4) + J18.17 + J2.3 + R105.1 + U1.167 + +JTAG_TDI (4) + J18.19 + J2.5 + R104.1 + U1.199 + +JTAG_TDO (3) + J18.18 + J2.4 + U1.200 + +JTAG_TMS (4) + J18.20 + J2.6 + R103.1 + U1.183 + +LED0_A (2) + J18.8 + R147.2 + +LED1_A (2) + J18.9 + R148.2 + +LED2_A (2) + J18.10 + R149.2 + +LED3_A (2) + J18.11 + R150.2 + +LINE_L (3) + C167.1 + J17.17 + R126.2 + +LINE_R (3) + C168.1 + J17.19 + R127.2 + +MCLK_RAW (2) + R115.1 + Y2.3 + +MIDI4 (2) + J18.13 + R180.1 + +MIDI5 (3) + D20.1 + J18.14 + U8.2 + +MIDI_A (3) + D20.2 + R180.2 + U8.1 + +MOD_ADC (3) + C194.1 + R165.2 + U4.5 + +MOD_BUF (3) + R165.1 + U6.6 + U6.7 + +MOD_DIV (5) + C192.1 + D11.3 + R163.2 + R164.1 + U6.5 + +MOD_IN (2) + J17.14 + R163.1 + +PG1 (3) + R12.1 + U11.4 + U12.13 + +PG18 (3) + R22.1 + U12.4 + U13.13 + +PITCH_ADC (3) + C193.1 + R162.2 + U4.4 + +PITCH_BUF (3) + R162.1 + U6.1 + U6.2 + +PITCH_DIV (5) + C191.1 + D10.3 + R160.2 + R161.1 + U6.3 + +PITCH_IN (2) + J17.13 + R160.1 + +POT_DECAY (3) + C175.1 + R132.2 + U4.2 + +POT_DECAY_RAW (2) + J17.7 + R132.1 + +POT_DELAY (3) + C202.1 + R191.2 + U4.7 + +POT_DELAY_RAW (2) + J17.10 + R191.1 + +POT_DRIVE (3) + C201.1 + R190.2 + U4.6 + +POT_DRIVE_RAW (2) + J17.9 + R190.1 + +POT_PITCH (3) + C174.1 + R131.2 + U4.1 + +POT_PITCH_RAW (2) + J17.6 + R131.1 + +POT_REVERB (3) + C203.1 + R192.2 + U4.8 + +POT_REVERB_RAW (2) + J17.11 + R192.1 + +POT_TIMBRE (3) + C176.1 + R133.2 + U4.3 + +POT_TIMBRE_RAW (2) + J17.8 + R133.1 + +PROGRAM_B (5) + J18.15 + J3.1 + R32.1 + U1.169 + U13.4 + +PUDC_B (2) + R102.1 + U1.175 + +SS1 (2) + C14.1 + U11.9 + +SS2 (2) + C24.1 + U12.9 + +SS3 (2) + C34.1 + U13.9 + +SW1 (4) + L1.1 + U11.1 + U11.2 + U11.3 + +SW2 (4) + L2.1 + U12.1 + U12.2 + U12.3 + +SW3 (4) + L3.1 + U13.1 + U13.2 + U13.3 + +V1 (25) + C100.1 + C101.1 + C102.1 + C103.1 + C104.1 + C105.1 + C106.1 + C107.1 + C108.1 + C12.1 + C13.1 + C140.1 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a/hardware/courant/deliverables/courant-panel-hardware.md b/hardware/courant/deliverables/courant-panel-hardware.md new file mode 100644 index 0000000..6828fef --- /dev/null +++ b/hardware/courant/deliverables/courant-panel-hardware.md @@ -0,0 +1,46 @@ +# Courant / RADIAN — current panel hardware + +The old Rev-A cable-harness panel interface is retired. Mainboard edge headers +J5 through J15 have been removed from the canonical PCB and are no longer part +of the BOM, fabrication outputs, or product assembly. + +The current panel is a PCB assembly that plugs directly onto the mainboard: + +- mainboard J17 ↔ panel J100 +- mainboard J18 ↔ panel J101 +- Samtec IPT1-110-06-L-D ↔ IPS1-110-01-L-D +- 40 physical contacts total +- 19.99 mm fully-mated PCB spacing; ~20.0 mm structural support target + +The shared electrical/mechanical source of truth is +`../../stack/panel-stack.json`; `../../stack/direct-stack-validation.json` +records the current 40/40 pin and mechanical checks. + +## Panel controls + +The panel PCB carries TENSION, DECAY and CHAOS plus DRIVE, DELAY and REVERB, +the push encoder, MODE switch, four LEDs, five 3.5 mm jacks, Eurorack power, +and its panel-side Samtec sockets. The three primary controls use larger knobs; +the FX row uses smaller knobs. +## Connections that still use short leads + +Only genuinely off-board/chassis functions need wiring: + +- Same Sky **SDS-50J** MIDI DIN → short 2-wire lead → exact Molex **22-27-2021** J306; +- Switchcraft **722A** 12 V chassis inlet → short 2-wire lead → exact Molex **22-27-2021** J201; +- Eurorack bus ribbon → exact Wurth **61201021621** keyed J200. + +There is no per-function cable bundle between the panel PCB and mainboard. + +## Selected local service parts + +JP1 is Wurth **450301014042**, a real SPDT switch rather than a removable header/shunt: pin 1 common is `MOD_IN`, pin 2 is `MOD_BIPOLAR`, and pin 3 is `MOD_RAW`. Panel J202 is exact Molex **22-27-2061** for JTAG service. + +## Service access + +Mainboard J1–J4 remain service/debug interfaces. They are not panel +connections and are intentionally separate from the production J17/J18 stack. + +`courant-panel-interface.csv` is retained only as historical Rev-A reference; +do not use it as the current product interconnect. The current interconnect is +defined by `../../stack/panel-stack.json`. diff --git a/hardware/courant/deliverables/courant-panel-interface.csv b/hardware/courant/deliverables/courant-panel-interface.csv new file mode 100644 index 0000000..2e79cab --- /dev/null +++ b/hardware/courant/deliverables/courant-panel-interface.csv @@ -0,0 +1,46 @@ +Connector,Pin,Net,Purpose +J1,1,VIN5,"5 V DC input, externally fused" +J1,2,GND,"5 V DC input, externally fused" +J2,1,V3V3,"JTAG, to programmer" +J2,2,GND,"JTAG, to programmer" +J2,3,JTAG_TCK,"JTAG, to programmer" +J2,4,JTAG_TDO,"JTAG, to programmer" +J2,5,JTAG_TDI,"JTAG, to programmer" +J2,6,JTAG_TMS,"JTAG, to programmer" +J3,1,PROGRAM_B,"PROGRAM_B, momentary to GND forces reconfiguration" +J3,2,GND,"PROGRAM_B, momentary to GND forces reconfiguration" +J4,1,reset_n,"Reset, momentary to GND" +J4,2,GND,"Reset, momentary to GND" +J5,1,LINE_L,"Stereo line out, to panel jacks" +J5,2,GND,"Stereo line out, to panel jacks" +J5,3,LINE_R,"Stereo line out, to panel jacks" +J6,1,VREF25,"Pitch potentiometer, panel mounted" +J6,2,POT_PITCH_RAW,"Pitch potentiometer, panel mounted" +J6,3,GND,"Pitch potentiometer, panel mounted" +J7,1,VREF25,"Decay potentiometer, panel mounted" +J7,2,POT_DECAY_RAW,"Decay potentiometer, panel mounted" +J7,3,GND,"Decay potentiometer, panel mounted" +J8,1,VREF25,"Timbre potentiometer, panel mounted" +J8,2,POT_TIMBRE_RAW,"Timbre potentiometer, panel mounted" +J8,3,GND,"Timbre potentiometer, panel mounted" +J9,1,ENC_A_RAW,"Rotary encoder with switch, panel mounted" +J9,2,GND,"Rotary encoder with switch, panel mounted" +J9,3,ENC_B_RAW,"Rotary encoder with switch, panel mounted" +J9,4,ENC_SW_RAW,"Rotary encoder with switch, panel mounted" +J9,5,GND,"Rotary encoder with switch, panel mounted" +J10,1,V3V3,"Mode selector switch, panel mounted" +J10,2,cv_select,"Mode selector switch, panel mounted" +J10,3,GND,"Mode selector switch, panel mounted" +J11,1,GND,"Status LEDs x4, anodes -- series resistors are on-board" +J11,2,LED0_A,"Status LEDs x4, anodes -- series resistors are on-board" +J11,3,LED1_A,"Status LEDs x4, anodes -- series resistors are on-board" +J11,4,LED2_A,"Status LEDs x4, anodes -- series resistors are on-board" +J11,5,LED3_A,"Status LEDs x4, anodes -- series resistors are on-board" +J12,1,PITCH_IN,"Pitch CV input jack, 0-5 V" +J12,2,GND,"Pitch CV input jack, 0-5 V" +J13,1,MOD_IN,"Mod CV input jack, 0-5 V" +J13,2,GND,"Mod CV input jack, 0-5 V" +J14,1,GATE_IN,Gate input jack +J14,2,GND,Gate input jack +J15,1,MIDI4,"MIDI DIN socket, pins 4 and 5" +J15,2,MIDI5,"MIDI DIN socket, pins 4 and 5" diff --git a/hardware/courant/deliverables/courant-schematic.svg b/hardware/courant/deliverables/courant-schematic.svg new file mode 100644 index 0000000..9463079 --- /dev/null +++ b/hardware/courant/deliverables/courant-schematic.svg @@ -0,0 +1,3096 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +VIN5 +VIN5 +VIN5 +VIN5 +VIN5 +VIN5 +VIN5 +VIN5 +VIN5 +VIN5 +VIN5 +VIN5 +VIN5 +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +GND +PG1 +SS1 +V1 +V1 +V1 +V1 +V1 +V1 +V1 +V1 +V1 +V1 +V1 +V1 +V1 +V1 +V1 +V1 +V1 +V1 +V1 +SS2 +SS2 +V1V8 +V1V8 +V1V8 +V1V8 +V1V8 +V1V8 +V1V8 +V1V8 +V1V8 +V1V8 +V1V8 +V1V8 +V1V8 +SS3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +V3V3 +led2 +led3 +DAC_CAPP +DAC_CAPM +DAC_VNEG +DAC_VNEG +VREF25 +VREF25 +VREF25 +VREF25 +VREF25 +VREF25 +VREF25 +5V INPUT +J1 +TPS62130ARGTR +U11 +TPS62130ARGTR +U12 +TPS62130ARGTR +U13 +XC7A50T-1FTG256I +U1 +JTAG: VREF GND TCK TDO TDI TMS +J2 +PROGRAM / GND +J3 +RESET / GND +J4 +W25Q64JVSSIQ +U2 +ASE-100.000MHZ-LC-T +Y1 +ASE-12.288MHZ-LC-T +Y2 +PCM5102APWR +U3 +STEREO LINE OUT L/G/R +J5 +MCP3208-CI/SL +U4 +REF3125AIDBZR +U5 +POT_PITCH: REF/WIPER/GND +J6 +POT_DECAY: REF/WIPER/GND +J7 +POT_TIMBRE: REF/WIPER/GND +J8 +ENCODER A/GND/B/SW/GND +J9 +MODE: 3V3/CV_SEL/GND +J10 +STATUS: GND/VOICE0..3 +J11 +MCP6002-I/SN +U6 +PITCH CV / GND +J12 +BAT54S +D10 +MOD CV / GND +J13 +BAT54S +D11 +GATE / GND +J14 +BAT54S +D12 +MCP6561T-E/OT +U7 +MIDI DIN4 / DIN5 +J15 +H11L1M +U8 +SW1 +SW1 +SW1 +SW1 +PG1 +PG1 +FB1 +FB1 +SW2 +SW2 +SW2 +SW2 +PG18 +PG18 +PG18 +FB2 +FB2 +SW3 +SW3 +SW3 +SW3 +PROGRAM_B +PROGRAM_B +PROGRAM_B +PROGRAM_B +FB3 +FB3 +JTAG_TCK +JTAG_TCK +JTAG_TCK +JTAG_TDI +JTAG_TDI +JTAG_TDI +JTAG_TMS +JTAG_TMS +FLASH_WP +FLASH_WP +FLASH_WP +FLASH_HOLD +FLASH_HOLD +FLASH_HOLD +FLASH_CS +FLASH_CS +FLASH_CS +dac_unmute +dac_unmute +dac_unmute +enc_btn_n +enc_btn_n +enc_btn_n +cv_select +cv_select +cv_select +midi_rx +midi_rx +midi_rx +reset_n +reset_n +reset_n +reset_n +enc_b +enc_b +enc_b +enc_a +enc_a +enc_a +adc_cs_n +adc_cs_n +adc_cs_n +A3V3 +A3V3 +A3V3 +A3V3 +A3V3 +LINE_L +LINE_L +LINE_L +LINE_R +LINE_R +LINE_R +POT_PITCH +POT_PITCH +POT_DECAY +POT_DECAY +POT_TIMBRE +POT_TIMBRE +PITCH_ADC +PITCH_ADC +MOD_ADC +MOD_ADC +PITCH_BUF +PITCH_BUF +PITCH_BUF +PITCH_DIV +PITCH_DIV +PITCH_DIV +PITCH_DIV +PITCH_DIV +MOD_DIV +MOD_DIV +MOD_DIV +MOD_DIV +MOD_BUF +MOD_BUF +MOD_BUF +GATE_DIV +GATE_DIV +GATE_DIV +GATE_DIV +GATE_DIV +GATE_REF +GATE_REF +MIDI5 +MIDI5 +MIDI5 +MIDI_A +MIDI_A +SS1 +SS3 +DONE +DONE +FLASH_CLK_RAW +FLASH_CLK_RAW +INIT_B +INIT_B +JTAG_TDO +JTAG_TDO +FLASH_MOSI +FLASH_MOSI +FLASH_MISO +FLASH_MISO +PUDC_B +PUDC_B +dac_mclk +dac_mclk +dac_bclk +dac_bclk +dac_lrclk +dac_lrclk +dac_data +dac_data +gate +gate +led1 +led1 +led0 +led0 +led2 +led3 +adc_miso +adc_miso +adc_mosi +adc_mosi +adc_sclk +adc_sclk +audio_mclk_in +audio_mclk_in +clk100 +clk100 +FLASH_CLK +FLASH_CLK +CLK100_RAW +CLK100_RAW +MCLK_RAW +MCLK_RAW +DAC_CAPP +DAC_CAPM +DAC_L +DAC_L +DAC_R +DAC_R +I2S_MCLK +I2S_MCLK +I2S_BCLK +I2S_BCLK +I2S_DATA +I2S_DATA +I2S_LRCLK +I2S_LRCLK +DAC_LDO +DAC_LDO +POT_PITCH_RAW +POT_PITCH_RAW +POT_DECAY_RAW +POT_DECAY_RAW +POT_TIMBRE_RAW +POT_TIMBRE_RAW +ENC_A_RAW +ENC_A_RAW +ENC_B_RAW +ENC_B_RAW +ENC_SW_RAW +ENC_SW_RAW +LED0_A +LED0_A +LED1_A +LED1_A +LED2_A +LED2_A +LED3_A +LED3_A +PITCH_IN +PITCH_IN +MOD_IN +MOD_IN +GATE_IN +GATE_IN +MIDI4 +MIDI4 + +Courant Rev A — schematic — 183 components, 532 nets drawn + \ No newline at end of file diff --git a/hardware/courant/deliverables/courant-source-design.ts b/hardware/courant/deliverables/courant-source-design.ts new file mode 100644 index 0000000..8b2da2c --- /dev/null +++ b/hardware/courant/deliverables/courant-source-design.ts @@ -0,0 +1,255 @@ +import pins from "./fpga-pins.json" +import { ftg256, soic8w208, qfn16, osc3225, inductor, type LandPattern } from "./footprints" + +export type Part = { + name: string; value: string; block: string; x: number; y: number; + kind: "chip" | "connector" | "resistor" | "capacitor" | "diode" | "led" | "inductor"; + rotation?: number; + footprint: string | LandPattern; nets: Record; tolerance?: string; + labels?: Record; nc?: string[]; layer?: "top" | "bottom"; +} +export const parts: Part[]=[] +let block="power" +const add=(name:string,value:string,x:number,y:number,footprint:string|LandPattern,nets:Record,labels?:Record,nc?:string[])=>{ + parts.push({name,value,x,y,footprint,nets,labels,nc,block,kind:"chip"}) +} +const passive=(kind:Part["kind"],name:string,value:string,x:number,y:number,a:string,b:string,footprint:string|LandPattern="0603",layer:"top"|"bottom"="top",tolerance?:string,rotation=0)=>{ + parts.push({kind,name,value,x,y,nets:{pin1:a,pin2:b},footprint,block,layer,tolerance,rotation}) +} +const r=(name:string,value:string,x:number,y:number,a:string,b:string,tolerance?:string)=>passive("resistor",name,value,x,y,a,b,"0603","top",tolerance) +const c=(name:string,value:string,x:number,y:number,a:string,b="GND",footprint="0603",layer:"top"|"bottom"="top",rotation=0)=>passive("capacitor",name,value,x,y,a,b,footprint,layer,undefined,rotation) +const j=(name:string,value:string,x:number,y:number,nets:string[],rotation=0)=>{ + add(name,value,x,y,`pinrow${nets.length}_p2.54mm`,Object.fromEntries(nets.map((n,i)=>[`pin${i+1}`,n]))) + Object.assign(parts[parts.length-1],{kind:"connector",rotation}) +} + +// Regulated 5 V / 3 A input, externally fused supply. Pin 1 = +5 V. +j("J1","5V INPUT",-70,35,["VIN5","GND"],90) +c("C1","47uF",-62,35,"VIN5","GND","1210") +// TPS62130A's PG is actively low while disabled: cascade 1V -> 1V8 -> 3V3. +/** Grounded thermal vias dropped into the TPS62130A exposed pads. */ +export const thermalVias: {name:string;x:number;y:number}[]=[] +const rails=[ + // 24.9k, not 25k: 25.0k is on no E-series grid and is not a stocked 1% + // part. 0.8 V x (1 + 24.9/100) = 0.9992 V, which is nearer 1.000 V than the + // 1% resistors can hold anyway. + {id:1,y:23,out:"V1",en:"VIN5",pg:"PG1",top:"24.9k",bottom:"100k"}, + {id:2,y:0,out:"V1V8",en:"PG1",pg:"PG18",top:"124k",bottom:"100k"}, + {id:3,y:-23,out:"V3V3",en:"PG18",pg:"PROGRAM_B",top:"316k",bottom:"100k"}, +] +for(const rail of rails){ + const {id,y,out,en,pg}=rail,n=10*id + add(`U${10+id}`,"TPS62130ARGTR",-57,y,qfn16,{ + pin1:`SW${id}`,pin2:`SW${id}`,pin3:`SW${id}`,pin4:pg,pin5:`FB${id}`, + pin6:"GND",pin7:"GND",pin8:"GND",pin9:`SS${id}`,pin10:"VIN5",pin11:"VIN5",pin12:"VIN5", + pin13:en,pin14:out,pin15:"GND",pin16:"GND",pin17:"GND", + }) + passive("inductor",`L${id}`,"1uH",-63,y,`SW${id}`,out,inductor) + c(`C${n}`,"10uF",-56,y+4,"VIN5","GND","0805") + c(`C${n+1}`,"100nF",-60,y+4,"VIN5") + c(`C${n+2}`,"22uF",-69,y,out,"GND","0805") + c(`C${n+3}`,"22uF",-69,y-3,out,"GND","0805") + c(`C${n+4}`,"3.3nF",-53,y+2,`SS${id}`) + r(`R${n}`,rail.top,-54,y-4,out,`FB${id}`,"1%") + r(`R${n+1}`,rail.bottom,-58,y-4,`FB${id}`,"GND","1%") + r(`R${n+2}`,"10k",-51,y-1,pg,id===3?"V3V3":"VIN5") + // Grounded thermal vias in the exposed pad, carrying the switcher's heat into + // the inner ground planes. TI's RGT0016C pad is 1.68 mm square (SLVSAG7F + // section 12), which fits a 2x2 array on a 0.84 mm pitch: the outer pad edge + // lands at 0.72 mm, inside the 0.84 mm thermal pad, and the via pads clear + // each other by 0.24 mm. Four 0.3 mm vias rather than nine small ones is + // deliberate -- below about four vias the barrel diameter, not the count, + // dominates the pad-to-plane resistance. + for(const [vx,vy] of [[-0.42,-0.42],[0.42,-0.42],[-0.42,0.42],[0.42,0.42]]) + thermalVias.push({name:`TV${id}${thermalVias.length%4+1}`,x:-57+vx,y:y+vy}) +} + +block="fpga" +export const io: Record={ + D4:"clk100", E3:"audio_mclk_in", // both clock-capable; second oscillator below + A3:"adc_sclk", B4:"adc_mosi", A4:"adc_miso", A5:"adc_cs_n", + A7:"enc_a", B7:"enc_b", A8:"enc_btn_n", A9:"cv_select", + A10:"gate", B9:"midi_rx", B10:"reset_n", + A12:"led0", B12:"led1", A13:"led2", A14:"led3", + T7:"dac_mclk", T8:"dac_bclk", T9:"dac_lrclk", T10:"dac_data", T12:"dac_unmute", +} +const fixed:Record={ + H10:"DONE", E8:"FLASH_CLK_RAW", J13:"FLASH_MOSI",J14:"FLASH_MISO",L12:"FLASH_CS", + K15:"FLASH_WP",K16:"FLASH_HOLD",L15:"PUDC_B", + L7:"JTAG_TCK",N7:"JTAG_TDI",N8:"JTAG_TDO",M7:"JTAG_TMS", + M9:"V3V3",M10:"GND",M11:"GND",K10:"INIT_B",L9:"PROGRAM_B",E7:"V3V3", + G7:"GND",G8:"V1V8",J8:"GND",J7:"GND",F8:"GND",H7:"GND",H8:"GND", +} +export const fpgaNets:Record={} +for(const p of pins){ + const supply=p.function==="GND"?"GND":p.function==="VCCINT"||p.function==="VCCBRAM"?"V1": + p.function==="VCCAUX"?"V1V8":p.function.startsWith("VCCO_")?"V3V3":undefined + if(supply||fixed[p.ball]||io[p.ball]) fpgaNets[p.ball]=supply||fixed[p.ball]||io[p.ball] +} +add("U1","XC7A50T-1FTG256I",0,5,ftg256,fpgaNets, + Object.fromEntries(pins.map(p=>[p.ball,`${p.ball}_${p.function}`])),pins.filter(p=>!fpgaNets[p.ball]).map(p=>p.ball)) +// Decouplers on the back, under the BGA. Each is a separate, physical capacitor. +// +// The 0201 land, the half-pitch diagonal offset and the 45 degree rotation are +// one constraint, not three choices. A dog-bone escape via needs 0.275 mm of +// barrel plus 0.15 mm of clearance, and the diagonal slot it sits in is only +// 0.707 mm from four balls of 0.25 mm radius -- 0.032 mm of slack before +// anything else is placed at all. A capacitor centred on a ball aims both of +// its lands at that ball's four slots and blocks every one of them: the 0402 +// array this replaces blocked ten of the twenty slots the last five +// connections needed, which is why no router could finish them. Centred on a +// *slot* and turned 45 degrees, each capacitor consumes exactly one slot and +// leaves its neighbours 0.528 mm clear against the 0.425 mm requirement. +const pdn=[...Array(9).fill("V1"),...Array(5).fill("V1V8"),...Array(24).fill("V3V3")] +pdn.forEach((net,i)=>c(`C${100+i}`,"100nF",-7+(i%6)*3,12-Math.floor(i/6)*3,net,"GND","0201","bottom",45)) +for(const [i,net] of ["V1","V1V8","V3V3"].entries()){ + c(`C${140+i}`,"47uF",-17+i*6,-8,net,"GND","1210") + c(`C${143+i}`,"4.7uF",-17+i*6,-12,net,"GND","0805") +} +r("R100","4.7k",12,-9,"INIT_B","V3V3") +r("R101","4.7k",12,-12,"DONE","V3V3") +r("R102","4.7k",12,-15,"PUDC_B","V3V3") +j("J2","JTAG: VREF GND TCK TDO TDI TMS",8,-40,["V3V3","GND","JTAG_TCK","JTAG_TDO","JTAG_TDI","JTAG_TMS"],0) +r("R103","10k",4,-30,"JTAG_TMS","V3V3") +r("R104","10k",8,-30,"JTAG_TDI","V3V3") +r("R105","10k",12,-30,"JTAG_TCK","GND") +j("J3","PROGRAM / GND",23,-40,["PROGRAM_B","GND"],0) // 23, not 27: clears U4's courtyard +j("J4","RESET / GND",-10,-40,["reset_n","GND"],0) +r("R106","10k",-12,-32,"reset_n","V3V3") +c("C146","100nF",-16,-32,"reset_n") + +block="configuration" +add("U2","W25Q64JVSSIQ",23,-22,soic8w208,{ + pin1:"FLASH_CS",pin2:"FLASH_MISO",pin3:"FLASH_WP",pin4:"GND", + pin5:"FLASH_MOSI",pin6:"FLASH_CLK",pin7:"FLASH_HOLD",pin8:"V3V3", +}) +c("C150","100nF",23,-15,"V3V3") +// At (11,-2.5), not (14,-22): this is series damping for the configuration +// clock, and damping works at the source. CCLK leaves the FPGA on ball E8, so +// the resistor sits 16 mm from the driver and lets the long run to U2 be the +// damped side. It was the other way round -- 9 mm from the flash, 32 mm from +// the FPGA -- which puts the resistor at the far end of the line it is meant +// to damp. +r("R110","33",11,-2.5,"FLASH_CLK_RAW","FLASH_CLK") +for(const [i,net] of ["FLASH_CS","FLASH_WP","FLASH_HOLD"].entries())r(`R${111+i}`,"4.7k",18+i*4,-30,net,"V3V3") +// Separate 100 MHz system / 12.288 MHz audio sources avoid fractional MMCM audio error. +add("Y1","ASE-100.000MHZ-LC-T",-20,19,osc3225,{pin1:"V3V3",pin2:"GND",pin3:"CLK100_RAW",pin4:"V3V3"}) +r("R114","33",-15,19,"CLK100_RAW","clk100") +c("C151","100nF",-24,19,"V3V3") +add("Y2","ASE-12.288MHZ-LC-T",-20,26,osc3225,{pin1:"V3V3",pin2:"GND",pin3:"MCLK_RAW",pin4:"V3V3"}) +r("R115","33",-15,26,"MCLK_RAW","audio_mclk_in") +c("C152","100nF",-24,26,"V3V3") + +block="audio" +add("U3","PCM5102APWR",49,13,"tssop20_p0.65mm",{ + pin1:"A3V3",pin2:"DAC_CAPP",pin3:"GND",pin4:"DAC_CAPM",pin5:"DAC_VNEG", + pin6:"DAC_L",pin7:"DAC_R",pin8:"A3V3",pin9:"GND",pin10:"GND",pin11:"GND", + pin12:"I2S_MCLK",pin13:"I2S_BCLK",pin14:"I2S_DATA",pin15:"I2S_LRCLK",pin16:"GND", + pin17:"dac_unmute",pin18:"DAC_LDO",pin19:"GND",pin20:"V3V3", +}) +// 3.3 V analog power: passive RC isolation, not an LDO that would lose headroom. +r("R120","1",39,23,"V3V3","A3V3") +c("C160","10uF",44,23,"A3V3","GND","0805") +c("C161","100nF",48,23,"A3V3") +c("C162","100nF",44,18,"A3V3") +c("C163","2.2uF",42,14,"DAC_CAPP","DAC_CAPM") +c("C164","2.2uF",42,9,"DAC_VNEG") +c("C165","1uF",55,18,"DAC_LDO") +c("C166","100nF",55,23,"V3V3") +r("R121","10k",55,8,"dac_unmute","GND") +for(const [i,pair] of [["dac_mclk","I2S_MCLK"],["dac_bclk","I2S_BCLK"],["dac_lrclk","I2S_LRCLK"],["dac_data","I2S_DATA"]].entries())r(`R${122+i}`,"33",13,9-i*3,pair[0],pair[1]) +r("R126","470",59,12,"DAC_L","LINE_L") +r("R127","470",59,4,"DAC_R","LINE_R") +c("C167","2.2nF",64,12,"LINE_L") +c("C168","2.2nF",64,4,"LINE_R") +j("J5","STEREO LINE OUT L/G/R",71,8,["LINE_L","GND","LINE_R"],270) + +block="controls" +// The ADC and its reference live in the analog corner, next to the CV front +// end, not beside the switchers. They were 26 mm (U5) and 40 mm (U4) from L1-L3 +// switching at 2.5 MHz, while their signals came 45-64 mm across the board from +// the CV conditioning and the panel; that is backwards. A 12-bit conversion +// against 2.5 V has a 610 uV LSB, so the analog side is the side to keep short. +// U4 is rotated 270 so its analog inputs (pins 1-5) face the CV block above it +// and its SPI (pins 10-13) faces away, down and back toward the FPGA: the long +// run is now the digital one, which is the run that can afford to be long. +add("U4","MCP3208-CI/SL",35,-39,"soic16_p1.27mm",{ + pin1:"POT_PITCH",pin2:"POT_DECAY",pin3:"POT_TIMBRE",pin4:"PITCH_ADC",pin5:"MOD_ADC", + pin6:"GND",pin7:"GND",pin8:"GND",pin9:"GND",pin10:"adc_cs_n",pin11:"adc_mosi", + pin12:"adc_miso",pin13:"adc_sclk",pin14:"GND",pin15:"VREF25",pin16:"V3V3", +}) +Object.assign(parts[parts.length-1],{rotation:270}) +// Supply and reference decoupling on U4's other side, by pins 15 and 16. +c("C170","100nF",39,-44,"V3V3") +c("C171","1uF",35.5,-44,"VREF25") +r("R130","10k",32,-44,"adc_cs_n","V3V3") +// REF3125: VIN=1, OUT=2, GND=3, per TI SOT23 DBZ pinout. +add("U5","REF3125AIDBZR",33.5,-23,"sot23",{pin1:"V3V3",pin2:"VREF25",pin3:"GND"}) +c("C172","100nF",33.5,-26,"V3V3") +c("C173","1uF",30,-26,"VREF25") +// The 1k stays at the panel header and the 10nF goes to the ADC pin, so the +// long wiper run sits *inside* the RC instead of downstream of it: whatever the +// trace picks up crossing the board is shunted at U4's input rather than +// arriving at its sampling capacitor. Same reasoning for the CV pair below. +const potFilter=[[43.5,-34.5],[40,-34.5],[36.5,-34.5]] +for(const [i,net] of ["POT_PITCH","POT_DECAY","POT_TIMBRE"].entries()){ + j(`J${6+i}`,`${net}: REF/WIPER/GND`,-36+i*18,40,["VREF25",`${net}_RAW`,"GND"],0) + r(`R${131+i}`,"1k",-36+i*18,34,`${net}_RAW`,net) + c(`C${174+i}`,"10nF",potFilter[i][0],potFilter[i][1],net) +} +j("J9","ENCODER A/GND/B/SW/GND",21,40,["ENC_A_RAW","GND","ENC_B_RAW","ENC_SW_RAW","GND"],0) +for(const [i,pair] of [["ENC_A_RAW","enc_a"],["ENC_B_RAW","enc_b"],["ENC_SW_RAW","enc_btn_n"]].entries()){ + r(`R${140+i}`,"1k",17+i*5,31,pair[0],pair[1]) + r(`R${143+i}`,"10k",17+i*5,27,pair[1],"V3V3") + c(`C${180+i}`,"10nF",17+i*5,23,pair[1]) +} +j("J10","MODE: 3V3/CV_SEL/GND",45,40,["V3V3","cv_select","GND"],0) +r("R146","10k",42,32,"cv_select","GND") +// The panel-side nets are `_A` (the LED anode beyond the series resistor), not +// `LED0`: `led0` and `LED0` are distinct nets here and in KiCad, but Specctra +// folds net names to one case, so the DSN handoff merged each pair and the +// router shorted straight across R147-R150. Nothing may differ by case alone; +// scripts/check.ts enforces it. +j("J11","STATUS: GND/VOICE0..3",64,40,["GND","LED0_A","LED1_A","LED2_A","LED3_A"],0) +for(let i=0;i<4;i++)r(`R${147+i}`,"1k",59+i*4,32,`led${i}`,`LED${i}_A`) + +block="cv" +// 0..5 V unipolar CV -> 0..2.5 V. 0.1% matched 20k dividers, input rail clamps. +add("U6","MCP6002-I/SN",43,-21,"soic8_p1.27mm",{ + pin1:"PITCH_BUF",pin2:"PITCH_BUF",pin3:"PITCH_DIV",pin4:"GND", + pin5:"MOD_DIV",pin6:"MOD_BUF",pin7:"MOD_BUF",pin8:"V3V3", +}) +c("C190","100nF",43,-14,"V3V3") +for(const [i,net] of ["PITCH","MOD"].entries()){ + const y=-18-i*13 + j(`J${12+i}`,`${net} CV / GND`,72,y,[`${net}_IN`,"GND"],270) + r(`R${160+i*3}`,"20k",64,y,`${net}_IN`,`${net}_DIV`,"0.1%") + r(`R${161+i*3}`,"20k",59,y-4,`${net}_DIV`,"GND","0.1%") + add(`D${10+i}`,"BAT54S",54,y,"sot23",{pin1:"GND",pin2:"V3V3",pin3:`${net}_DIV`}) + c(`C${191+i}`,"1nF",59,y,`${net}_DIV`) + // Series resistor at the buffer, filter capacitor at the ADC (see above). + r(`R${162+i*3}`,"100",35,y,`${net}_BUF`,`${net}_ADC`) + c(`C${193+i}`,"10nF",[33,29.5][i],-34.5,`${net}_ADC`) +} +// Comparator with built-in hysteresis; rising threshold approx 2.02 V at jack. +j("J14","GATE / GND",71,-41,["GATE_IN","GND"],270) +r("R166","100k",61,-40,"GATE_IN","GATE_DIV","1%") +r("R167","33k",56,-43,"GATE_DIV","GND","1%") +add("D12","BAT54S",55,-38,"sot23",{pin1:"GND",pin2:"V3V3",pin3:"GATE_DIV"}) +r("R168","40.2k",43,-39,"VREF25","GATE_REF","1%") +r("R169","10k",43,-43,"GATE_REF","GND","1%") +add("U7","MCP6561T-E/OT",49,-39,"sot23_5",{pin1:"gate",pin2:"GND",pin3:"GATE_DIV",pin4:"GATE_REF",pin5:"V3V3"}) +c("C195","100nF",49,-44,"V3V3") +c("C196","1nF",61,-44,"GATE_DIV") + +block="midi" +// Isolated DIN input harness: pin 4 -> 220R -> anode; pin 5 -> cathode. +// No connection from DIN pin 2/shield to board ground. +j("J15","MIDI DIN4 / DIN5",-72,-40,["MIDI4","MIDI5"],90) +r("R180","220",-66,-35,"MIDI4","MIDI_A") +add("U8","H11L1M",-52,-39,"dip6",{pin1:"MIDI_A",pin2:"MIDI5",pin4:"midi_rx",pin5:"GND",pin6:"V3V3"},undefined,["pin3"]) +passive("diode","D20","1N4148W",-64,-40,"MIDI5","MIDI_A","sod123") +r("R181","2.2k",-45,-33,"midi_rx","V3V3") +c("C200","100nF",-45,-37,"V3V3") + +export const nets=[...new Set(parts.flatMap(p=>Object.values(p.nets)))].sort() diff --git a/hardware/courant/deliverables/courant.before_colored_actual_models_20260918T190457.kicad_pcb b/hardware/courant/deliverables/courant.before_colored_actual_models_20260918T190457.kicad_pcb new file mode 100644 index 0000000..bcbfeb4 --- /dev/null +++ b/hardware/courant/deliverables/courant.before_colored_actual_models_20260918T190457.kicad_pcb @@ -0,0 +1,72304 @@ +(kicad_pcb + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (general + (thickness 1.6) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (4 "In1.Cu" signal) + (6 "In2.Cu" signal) + (8 "In3.Cu" signal) + (10 "In4.Cu" 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"lib_footprint_mismatch": "warning", + "malformed_courtyard": "error", + "microvia_drill_out_of_range": "error", + "mirrored_text_on_front_layer": "warning", + "missing_courtyard": "ignore", + "missing_footprint": "warning", + "missing_tuning_profile": "warning", + "net_conflict": "warning", + "nonmirrored_text_on_back_layer": "warning", + "npth_inside_courtyard": "error", + "padstack": "warning", + "pth_inside_courtyard": "error", + "shorting_items": "error", + "silk_edge_clearance": "warning", + "silk_over_copper": "warning", + "silk_overlap": "warning", + "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_on_edge_cuts": "error", + "text_thickness": "warning", + "through_hole_pad_without_hole": "error", + "too_many_vias": "error", + "track_angle": "error", + "track_dangling": "warning", + "track_not_centered_on_via": "ignore", + "track_on_post_machined_layer": "error", + "track_segment_length": "error", + "track_width": "error", + "tracks_crossing": "error", + "tuning_profile_track_geometries": "ignore", + "unconnected_items": "error", + "unresolved_variable": "error", + "via_dangling": "warning", + "zones_intersect": "error" + }, + "rules": { + "max_error": 0.005, + "min_clearance": 0.15, + "min_connection": 0.0, + "min_copper_edge_clearance": 0.5, + "min_groove_width": 0.0, + "min_hole_clearance": 0.25, + "min_hole_to_hole": 0.25, + "min_microvia_diameter": 0.2, + "min_microvia_drill": 0.1, + "min_resolved_spokes": 2, + "min_silk_clearance": 0.0, + "min_text_height": 0.8, + "min_text_thickness": 0.08, + "min_through_hole_diameter": 0.25, + "min_track_width": 0.15, + "min_via_annular_width": 0.125, + "min_via_diameter": 0.5, + "solder_mask_to_copper_clearance": 0.0, + "use_height_for_length_calcs": true + }, + "teardrop_options": [ + { + "td_onpthpad": true, + "td_onroundshapesonly": false, + "td_onsmdpad": true, + "td_ontrackend": false, + "td_onvia": true + } + ], + "teardrop_parameters": [ + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], + "track_widths": [], + "tuning_pattern_settings": { + "diff_pair_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 1.0 + }, + "diff_pair_skew_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + }, + "single_track_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + } + }, + "via_dimensions": [], + "zones_allow_external_fillets": false + }, + "ipc2581": { + "bom_rev": "", + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "", + "sch_revision": "" + }, + "layer_pairs": [], + "layer_presets": [], + "viewports": [] + }, + "boards": [], + "component_class_settings": { + "assignments": [], + "meta": { + "version": 0 + }, + "sheet_component_classes": { + "enabled": false + } + }, + "cvpcb": { + "equivalence_files": [] + }, + "libraries": { + "pinned_footprint_libs": [], + "pinned_symbol_libs": [] + }, + "meta": { + "filename": "courant.routed.kicad_pro", + "version": 3 + }, + "net_settings": { + "classes": [ + { + "clearance": 0.15, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": -1, + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.15, + "tuning_profile": "", + "via_diameter": 0.55, + "via_drill": 0.25 + }, + { + "clearance": 0.15, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Ground", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": -1, + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.3, + "tuning_profile": "", + "via_diameter": 0.55, + "via_drill": 0.25 + }, + { + "clearance": 0.15, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Power", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": -1, + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.4, + "tuning_profile": "", + "via_diameter": 0.55, + "via_drill": 0.25 + } + ], + "meta": { + "version": 5 + }, + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [ + { + "netclass": "Ground", + "pattern": "GND" + }, + { + "netclass": "Power", + "pattern": "VIN5" + }, + { + "netclass": "Power", + "pattern": "V1" + }, + { + "netclass": "Power", + "pattern": "V1V8" + }, + { + "netclass": "Power", + "pattern": "V3V3" + }, + { + "netclass": "Power", + "pattern": "A3V3" + }, + { + "netclass": "Power", + "pattern": "SW1" + }, + { + "netclass": "Power", + "pattern": "SW2" + }, + { + "netclass": "Power", + "pattern": "SW3" + } + ] + }, + "pcbnew": { + "last_paths": { + "idf": "", + "netlist": "", + "plot": "", + "specctra_dsn": "", + "step": "", + "vrml": "" + }, + "page_layout_descr_file": "" + }, + "schematic": { + "bus_aliases": {}, + "legacy_lib_dir": "", + "legacy_lib_list": [], + "top_level_sheets": [ + { + "filename": "courant.routed.kicad_sch", + "name": "courant.routed", + "uuid": "00000000-0000-0000-0000-000000000000" + } + ] + }, + "sheets": [], + "text_variables": {}, + "tuning_profiles": { + "meta": { + "version": 0 + }, + "tuning_profiles_impedance_geometric": [] + } +} diff --git a/hardware/courant/deliverables/fp-lib-table b/hardware/courant/deliverables/fp-lib-table new file mode 100644 index 0000000..c4e79d3 --- /dev/null +++ b/hardware/courant/deliverables/fp-lib-table @@ -0,0 +1 @@ +(fp_lib_table (version 7) (lib (name "RadianMain") (type "KiCad") (uri "${KIPRJMOD}/RadianMain.pretty") (options "") (descr "Exact mainboard geometry snapshots; manufacturer sign-off still required"))) diff --git a/hardware/courant/deliverables/native_checks/drc.json b/hardware/courant/deliverables/native_checks/drc.json new file mode 100644 index 0000000..76dfafc --- /dev/null +++ b/hardware/courant/deliverables/native_checks/drc.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T16:43:34", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "courant.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/courant/deliverables/native_checks/exact_connector_drc.json b/hardware/courant/deliverables/native_checks/exact_connector_drc.json new file mode 100644 index 0000000..961d9f2 --- /dev/null +++ b/hardware/courant/deliverables/native_checks/exact_connector_drc.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-17T22:50:28", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "courant.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/courant/design.ts b/hardware/courant/design.ts new file mode 100644 index 0000000..99bb48e --- /dev/null +++ b/hardware/courant/design.ts @@ -0,0 +1,260 @@ +import pins from "./fpga-pins.json" +import { ftg256, soic8w208, qfn16, osc3225, inductor, stack2x10, cap0201, type LandPattern } from "./footprints" +import stack from "../stack/panel-stack.json" + +export type Part = { + name: string; value: string; block: string; x: number; y: number; + kind: "chip" | "connector" | "resistor" | "capacitor" | "diode" | "led" | "inductor"; + rotation?: number; + footprint: string | LandPattern; nets: Record; tolerance?: string; + labels?: Record; nc?: string[]; layer?: "top" | "bottom"; +} +export const parts: Part[]=[] +let block="power" +const add=(name:string,value:string,x:number,y:number,footprint:string|LandPattern,nets:Record,labels?:Record,nc?:string[])=>{ + parts.push({name,value,x,y,footprint,nets,labels,nc,block,kind:"chip"}) +} +const passive=(kind:Part["kind"],name:string,value:string,x:number,y:number,a:string,b:string,footprint:string|LandPattern="0603",layer:"top"|"bottom"="top",tolerance?:string,rotation=0)=>{ + parts.push({kind,name,value,x,y,nets:{pin1:a,pin2:b},footprint,block,layer,tolerance,rotation}) +} +const r=(name:string,value:string,x:number,y:number,a:string,b:string,tolerance?:string)=>passive("resistor",name,value,x,y,a,b,"0603","top",tolerance) +const c=(name:string,value:string,x:number,y:number,a:string,b="GND",footprint:string|LandPattern="0603",layer:"top"|"bottom"="top",rotation=0)=>passive("capacitor",name,value,x,y,a,b,footprint,layer,undefined,rotation) +const j=(name:string,value:string,x:number,y:number,nets:string[],rotation=0)=>{ + add(name,value,x,y,`pinrow${nets.length}_p2.54mm`,Object.fromEntries(nets.map((n,i)=>[`pin${i+1}`,n]))) + Object.assign(parts[parts.length-1],{kind:"connector",rotation}) +} + +// Regulated 5 V / 3 A input, externally fused supply. Pin 1 = +5 V. +c("C1","47uF",-62,35,"VIN5","GND","1210") +// TPS62130A's PG is actively low while disabled: cascade 1V -> 1V8 -> 3V3. +/** Grounded thermal vias dropped into the TPS62130A exposed pads. */ +export const thermalVias: {name:string;x:number;y:number}[]=[] +const rails=[ + // 24.9k, not 25k: 25.0k is on no E-series grid and is not a stocked 1% + // part. 0.8 V x (1 + 24.9/100) = 0.9992 V, which is nearer 1.000 V than the + // 1% resistors can hold anyway. + {id:1,y:23,out:"V1",en:"VIN5",pg:"PG1",top:"24.9k",bottom:"100k"}, + {id:2,y:0,out:"V1V8",en:"PG1",pg:"PG18",top:"124k",bottom:"100k"}, + {id:3,y:-23,out:"V3V3",en:"PG18",pg:"PROGRAM_B",top:"316k",bottom:"100k"}, +] +for(const rail of rails){ + const {id,y,out,en,pg}=rail,n=10*id + add(`U${10+id}`,"TPS62130ARGTR",-57,y,qfn16,{ + pin1:`SW${id}`,pin2:`SW${id}`,pin3:`SW${id}`,pin4:pg,pin5:`FB${id}`, + pin6:"GND",pin7:"GND",pin8:"GND",pin9:`SS${id}`,pin10:"VIN5",pin11:"VIN5",pin12:"VIN5", + pin13:en,pin14:out,pin15:"GND",pin16:"GND",pin17:"GND", + }) + passive("inductor",`L${id}`,"1uH",-63,y,`SW${id}`,out,inductor) + c(`C${n}`,"10uF",-56,y+4,"VIN5","GND","0805") + c(`C${n+1}`,"100nF",-60,y+4,"VIN5") + c(`C${n+2}`,"22uF",-69,y,out,"GND","0805") + c(`C${n+3}`,"22uF",-69,y-3,out,"GND","0805") + c(`C${n+4}`,"3.3nF",-53,y+2,`SS${id}`) + r(`R${n}`,rail.top,-54,y-4,out,`FB${id}`,"1%") + r(`R${n+1}`,rail.bottom,-58,y-4,`FB${id}`,"GND","1%") + r(`R${n+2}`,"10k",-51,y-1,pg,id===3?"V3V3":"VIN5") + // Grounded thermal vias in the exposed pad, carrying the switcher's heat into + // the inner ground planes. TI's RGT0016C pad is 1.68 mm square (SLVSAG7F + // section 12), which fits a 2x2 array on a 0.84 mm pitch: the outer pad edge + // lands at 0.72 mm, inside the 0.84 mm thermal pad, and the via pads clear + // each other by 0.24 mm. Four 0.3 mm vias rather than nine small ones is + // deliberate -- below about four vias the barrel diameter, not the count, + // dominates the pad-to-plane resistance. + for(const [vx,vy] of [[-0.42,-0.42],[0.42,-0.42],[-0.42,0.42],[0.42,0.42]]) + thermalVias.push({name:`TV${id}${thermalVias.length%4+1}`,x:-57+vx,y:y+vy}) +} + +block="fpga" +export const io: Record={ + D4:"clk100", E3:"audio_mclk_in", // both clock-capable; second oscillator below + A3:"adc_sclk", B4:"adc_mosi", A4:"adc_miso", A5:"adc_cs_n", + A7:"enc_a", B7:"enc_b", A8:"enc_btn_n", A9:"cv_select", + A10:"gate", B9:"midi_rx", B10:"reset_n", + A12:"led0", B12:"led1", A13:"led2", A14:"led3", + T7:"dac_mclk", T8:"dac_bclk", T9:"dac_lrclk", T10:"dac_data", T12:"dac_unmute", +} +const fixed:Record={ + H10:"DONE", E8:"FLASH_CLK_RAW", J13:"FLASH_MOSI",J14:"FLASH_MISO",L12:"FLASH_CS", + K15:"FLASH_WP",K16:"FLASH_HOLD",L15:"PUDC_B", + L7:"JTAG_TCK",N7:"JTAG_TDI",N8:"JTAG_TDO",M7:"JTAG_TMS", + M9:"V3V3",M10:"GND",M11:"GND",K10:"INIT_B",L9:"PROGRAM_B",E7:"V3V3", + G7:"GND",G8:"V1V8",J8:"GND",J7:"GND",F8:"GND",H7:"GND",H8:"GND", +} +export const fpgaNets:Record={} +for(const p of pins){ + const supply=p.function==="GND"?"GND":p.function==="VCCINT"||p.function==="VCCBRAM"?"V1": + p.function==="VCCAUX"?"V1V8":p.function.startsWith("VCCO_")?"V3V3":undefined + if(supply||fixed[p.ball]||io[p.ball]) fpgaNets[p.ball]=supply||fixed[p.ball]||io[p.ball] +} +add("U1","XC7A50T-1FTG256I",0,5,ftg256,fpgaNets, + Object.fromEntries(pins.map(p=>[p.ball,`${p.ball}_${p.function}`])),pins.filter(p=>!fpgaNets[p.ball]).map(p=>p.ball)) +// Decouplers on the back, under the BGA. Each is a separate, physical capacitor. +// +// The 0201 land, the half-pitch diagonal offset and the 45 degree rotation are +// one constraint, not three choices. A dog-bone escape via needs 0.275 mm of +// barrel plus 0.15 mm of clearance, and the diagonal slot it sits in is only +// 0.707 mm from four balls of 0.25 mm radius -- 0.032 mm of slack before +// anything else is placed at all. A capacitor centred on a ball aims both of +// its lands at that ball's four slots and blocks every one of them: the 0402 +// array this replaces blocked ten of the twenty slots the last five +// connections needed, which is why no router could finish them. Centred on a +// *slot* and turned 45 degrees, each capacitor consumes exactly one slot and +// leaves its neighbours 0.528 mm clear against the 0.425 mm requirement. +const pdn=[...Array(9).fill("V1"),...Array(5).fill("V1V8"),...Array(24).fill("V3V3")] +pdn.forEach((net,i)=>c(`C${100+i}`,"100nF",-7+(i%6)*3,12-Math.floor(i/6)*3,net,"GND",cap0201,"bottom",45)) +for(const [i,net] of ["V1","V1V8","V3V3"].entries()){ + c(`C${140+i}`,"47uF",-17+i*6,-8,net,"GND","1210") + c(`C${143+i}`,"4.7uF",-17+i*6,-12,net,"GND","0805") +} +r("R100","4.7k",12,-9,"INIT_B","V3V3") +r("R101","4.7k",12,-12,"DONE","V3V3") +r("R102","4.7k",12,-15,"PUDC_B","V3V3") +r("R103","10k",4,-30,"JTAG_TMS","V3V3") +r("R104","10k",8,-30,"JTAG_TDI","V3V3") +r("R105","10k",12,-30,"JTAG_TCK","GND") +r("R106","10k",-12,-32,"reset_n","V3V3") +c("C146","100nF",-16,-32,"reset_n") + +block="configuration" +add("U2","W25Q64JVSSIQ",23,-22,soic8w208,{ + pin1:"FLASH_CS",pin2:"FLASH_MISO",pin3:"FLASH_WP",pin4:"GND", + pin5:"FLASH_MOSI",pin6:"FLASH_CLK",pin7:"FLASH_HOLD",pin8:"V3V3", +}) +c("C150","100nF",23,-15,"V3V3") +// At (11,-2.5), not (14,-22): this is series damping for the configuration +// clock, and damping works at the source. CCLK leaves the FPGA on ball E8, so +// the resistor sits 16 mm from the driver and lets the long run to U2 be the +// damped side. It was the other way round -- 9 mm from the flash, 32 mm from +// the FPGA -- which puts the resistor at the far end of the line it is meant +// to damp. +r("R110","33",11,-2.5,"FLASH_CLK_RAW","FLASH_CLK") +for(const [i,net] of ["FLASH_CS","FLASH_WP","FLASH_HOLD"].entries())r(`R${111+i}`,"4.7k",18+i*4,-30,net,"V3V3") +// Separate 100 MHz system / 12.288 MHz audio sources avoid fractional MMCM audio error. +add("Y1","ASE-100.000MHZ-LC-T",-20,19,osc3225,{pin1:"V3V3",pin2:"GND",pin3:"CLK100_RAW",pin4:"V3V3"}) +r("R114","33",-15,19,"CLK100_RAW","clk100") +c("C151","100nF",-24,19,"V3V3") +add("Y2","ASE-12.288MHZ-LC-T",-20,26,osc3225,{pin1:"V3V3",pin2:"GND",pin3:"MCLK_RAW",pin4:"V3V3"}) +r("R115","33",-15,26,"MCLK_RAW","audio_mclk_in") +c("C152","100nF",-24,26,"V3V3") + +block="audio" +add("U3","PCM5102APWR",49,13,"tssop20_p0.65mm",{ + pin1:"A3V3",pin2:"DAC_CAPP",pin3:"GND",pin4:"DAC_CAPM",pin5:"DAC_VNEG", + pin6:"DAC_L",pin7:"DAC_R",pin8:"A3V3",pin9:"GND",pin10:"GND",pin11:"GND", + pin12:"I2S_MCLK",pin13:"I2S_BCLK",pin14:"I2S_DATA",pin15:"I2S_LRCLK",pin16:"GND", + pin17:"dac_unmute",pin18:"DAC_LDO",pin19:"GND",pin20:"V3V3", +}) +// 3.3 V analog power: passive RC isolation, not an LDO that would lose headroom. +r("R120","1",39,23,"V3V3","A3V3") +c("C160","10uF",44,23,"A3V3","GND","0805") +c("C161","100nF",48,23,"A3V3") +c("C162","100nF",44,18,"A3V3") +c("C163","2.2uF",42,14,"DAC_CAPP","DAC_CAPM") +c("C164","2.2uF",42,9,"DAC_VNEG") +c("C165","1uF",55,18,"DAC_LDO") +c("C166","100nF",55,23,"V3V3") +r("R121","10k",55,8,"dac_unmute","GND") +for(const [i,pair] of [["dac_mclk","I2S_MCLK"],["dac_bclk","I2S_BCLK"],["dac_lrclk","I2S_LRCLK"],["dac_data","I2S_DATA"]].entries())r(`R${122+i}`,"33",13,9-i*3,pair[0],pair[1]) +r("R126","470",59,12,"DAC_L","LINE_L") +r("R127","470",59,4,"DAC_R","LINE_R") +c("C167","2.2nF",64,12,"LINE_L") +c("C168","2.2nF",64,4,"LINE_R") + +block="controls" +// The ADC and its reference live in the analog corner, next to the CV front +// end, not beside the switchers. They were 26 mm (U5) and 40 mm (U4) from L1-L3 +// switching at 2.5 MHz, while their signals came 45-64 mm across the board from +// the CV conditioning and the panel; that is backwards. A 12-bit conversion +// against 2.5 V has a 610 uV LSB, so the analog side is the side to keep short. +// U4 is rotated 270 so its analog inputs (pins 1-5) face the CV block above it +// and its SPI (pins 10-13) faces away, down and back toward the FPGA: the long +// run is now the digital one, which is the run that can afford to be long. +add("U4","MCP3208-CI/SL",35,-39,"soic16_p1.27mm",{ + pin1:"POT_PITCH",pin2:"POT_DECAY",pin3:"POT_TIMBRE",pin4:"PITCH_ADC",pin5:"MOD_ADC", + pin6:"POT_DRIVE",pin7:"POT_DELAY",pin8:"POT_REVERB",pin9:"GND",pin10:"adc_cs_n",pin11:"adc_mosi", + pin12:"adc_miso",pin13:"adc_sclk",pin14:"GND",pin15:"VREF25",pin16:"V3V3", +}) +Object.assign(parts[parts.length-1],{rotation:270}) +// Supply and reference decoupling on U4's other side, by pins 15 and 16. +c("C170","100nF",39,-44,"V3V3") +c("C171","1uF",35.5,-44,"VREF25") +r("R130","10k",32,-44,"adc_cs_n","V3V3") +// REF3125: VIN=1, OUT=2, GND=3, per TI SOT23 DBZ pinout. +add("U5","REF3125AIDBZR",33.5,-23,"sot23",{pin1:"V3V3",pin2:"VREF25",pin3:"GND"}) +c("C172","100nF",33.5,-26,"V3V3") +c("C173","1uF",30,-26,"VREF25") +// The 1k stays at the panel header and the 10nF goes to the ADC pin, so the +// long wiper run sits *inside* the RC instead of downstream of it: whatever the +// trace picks up crossing the board is shunted at U4's input rather than +// arriving at its sampling capacitor. Same reasoning for the CV pair below. +const potFilter=[[43.5,-34.5],[40,-34.5],[36.5,-34.5]] +for(const [i,net] of ["POT_PITCH","POT_DECAY","POT_TIMBRE"].entries()){ + r(`R${131+i}`,"1k",-36+i*18,34,`${net}_RAW`,net) + c(`C${174+i}`,"10nF",potFilter[i][0],potFilter[i][1],net) +} +// Three dedicated effect-pot channels enter through direct-stack connector A and each gets its own ADC RC filter. +for(const [i,net] of ["POT_DRIVE","POT_DELAY","POT_REVERB"].entries()){ + r(`R${190+i}`,"1kΩ",64,-4-i*3,`${net}_RAW`,net) + c(`C${201+i}`,"10nF",30-i*3,-34.5,net,"GND","0603","bottom") +} +for(const [i,pair] of [["ENC_A_RAW","enc_a"],["ENC_B_RAW","enc_b"],["ENC_SW_RAW","enc_btn_n"]].entries()){ + r(`R${140+i}`,"1k",17+i*5,31,pair[0],pair[1]) + r(`R${143+i}`,"10k",17+i*5,27,pair[1],"V3V3") + c(`C${180+i}`,"10nF",17+i*5,23,pair[1]) +} +r("R146","10k",42,32,"cv_select","GND") +// The panel-side nets are `_A` (the LED anode beyond the series resistor), not +// `LED0`: `led0` and `LED0` are distinct nets here and in KiCad, but Specctra +// folds net names to one case, so the DSN handoff merged each pair and the +// router shorted straight across R147-R150. Nothing may differ by case alone; +// scripts/check.ts enforces it. +for(let i=0;i<4;i++)r(`R${147+i}`,"1k",59+i*4,32,`led${i}`,`LED${i}_A`) + +block="cv" +// 0..5 V unipolar CV -> 0..2.5 V. 0.1% matched 20k dividers, input rail clamps. +add("U6","MCP6002-I/SN",43,-21,"soic8_p1.27mm",{ + pin1:"PITCH_BUF",pin2:"PITCH_BUF",pin3:"PITCH_DIV",pin4:"GND", + pin5:"MOD_DIV",pin6:"MOD_BUF",pin7:"MOD_BUF",pin8:"V3V3", +}) +c("C190","100nF",43,-14,"V3V3") +for(const [i,net] of ["PITCH","MOD"].entries()){ + const y=-18-i*13 + r(`R${160+i*3}`,"20k",64,y,`${net}_IN`,`${net}_DIV`,"0.1%") + r(`R${161+i*3}`,"20k",59,y-4,`${net}_DIV`,"GND","0.1%") + add(`D${10+i}`,"BAT54S",54,y,"sot23",{pin1:"GND",pin2:"V3V3",pin3:`${net}_DIV`}) + c(`C${191+i}`,"1nF",59,y,`${net}_DIV`) + // Series resistor at the buffer, filter capacitor at the ADC (see above). + r(`R${162+i*3}`,"100",35,y,`${net}_BUF`,`${net}_ADC`) + c(`C${193+i}`,"10nF",[33,29.5][i],-34.5,`${net}_ADC`) +} +// Comparator with built-in hysteresis; rising threshold approx 2.02 V at jack. +r("R166","100k",61,-40,"GATE_IN","GATE_DIV","1%") +r("R167","33k",56,-43,"GATE_DIV","GND","1%") +add("D12","BAT54S",55,-38,"sot23",{pin1:"GND",pin2:"V3V3",pin3:"GATE_DIV"}) +r("R168","40.2k",43,-39,"VREF25","GATE_REF","1%") +r("R169","10k",43,-43,"GATE_REF","GND","1%") +add("U7","MCP6561T-E/OT",49,-39,"sot23_5",{pin1:"gate",pin2:"GND",pin3:"GATE_DIV",pin4:"GATE_REF",pin5:"V3V3"}) +c("C195","100nF",49,-44,"V3V3") +c("C196","1nF",61,-44,"GATE_DIV") + +block="midi" +// Isolated DIN input harness: pin 4 -> 220R -> anode; pin 5 -> cathode. +// No connection from DIN pin 2/shield to board ground. +r("R180","220",-66,-35,"MIDI4","MIDI_A") +add("U8","H11L1M",-52,-39,"dip6",{pin1:"MIDI_A",pin2:"MIDI5",pin4:"midi_rx",pin5:"GND",pin6:"V3V3"},undefined,["pin3"]) +passive("diode","D20","1N4148W",-64,-40,"MIDI5","MIDI_A","sod123") +r("R181","2.2k",-45,-33,"midi_rx","V3V3") +c("C200","100nF",-45,-37,"V3V3") + + +// Direct panel/mainboard mezzanine interface. Both boards consume the same +// hardware/stack/panel-stack.json contract; the panel mirrors footprint X on +// its bottom side so equal logical pin numbers occupy equal product-space XY. +for(const con of stack.connectors){ + const signals=con.signals as string[] + add(con.main_ref,stack.connector_footprint.main.mpn,con.main_xy_mm.x,con.main_xy_mm.y,stack2x10, + Object.fromEntries(signals.map((n,i)=>[`pin${i+1}`,n]))) + Object.assign(parts[parts.length-1],{kind:"connector",rotation:con.rotation_deg}) +} + +export const nets=[...new Set(parts.flatMap(p=>Object.values(p.nets)))].sort() diff --git a/hardware/courant/footprints.tsx b/hardware/courant/footprints.tsx new file mode 100644 index 0000000..721e532 --- /dev/null +++ b/hardware/courant/footprints.tsx @@ -0,0 +1,101 @@ +import type { ReactElement } from "react" + +/** + * Custom land patterns, for packages @tscircuit/footprinter cannot express. + * Everything else uses a footprinter string directly (see design.ts). + * + * All coordinates are top view, millimetres. Pin 1 is upper left on ICs, + * matching footprinter's own convention for SOIC/TSSOP/QFN/SOT, so parts can + * move between a string and a pattern here without renumbering. + */ +export type Pad = { pin: string; x: number; y: number; w?: number; h?: number; hole?: number; diameter?: number } +export type LandPattern = { width: number; height: number; pads: Pad[]; courtyard?: boolean } +export function lands(p: LandPattern): ReactElement { + return + {p.pads.map(pad => pad.hole ? + : + pad.diameter ? : + )} + + {p.courtyard!==false && 2*Math.abs(q.x)+(q.w ?? q.diameter ?? 0)))+0.5} + height={Math.max(p.height, ...p.pads.map(q=>2*Math.abs(q.y)+(q.h ?? q.diameter ?? 0)))+0.5}/>} + +} + +/** XC7A35T-1FTG256C. 16x16 balls, 1.0 mm pitch, 17x17 mm body. + * Ball A1 is upper left; footprinter's bga256 numbers from the lower left, so + * this stays custom to keep `pin(row*16+col)` aligned with the AMD ball map. */ +export const fpgaRows="ABCDEFGHJKLMNPRT" +export const ftg256: LandPattern={width:17,height:17,pads:[...fpgaRows].flatMap((row,r)=> + Array.from({length:16},(_,c)=>({pin:`pin${r*16+c+1}`,x:c-7.5,y:7.5-r,diameter:0.5})))} + + +/** Exact 0201 decoupler land used under the BGA. tscircuit's generic 0201 + * footprint emits a rotated-bottom courtyard that its current overlap checker + * compares in the wrong coordinate frame, producing three impossible overlap + * reports between parts 6-8.5 mm apart. Pads match the native KiCad footprint + * exactly; courtyard checking remains authoritative in native KiCad DRC. */ +export const cap0201: LandPattern={width:1.12,height:0.7,courtyard:false,pads:[ + // Custom footprints are mirrored when placed on bottom; use the local signs + // below so the final product-space pin numbering matches the native KiCad + // 0201 footprint and tscircuit's former generic-footprinter result. + {pin:"pin1",x:-0.33,y:0,w:0.46,h:0.40}, + {pin:"pin2",x:0.33,y:0,w:0.46,h:0.40}, +]} + +/** W25Q64JVSSIQ: 8-pin SOIC 208-mil (Winbond package code SS, datasheet 10.1). + * H 7.70/7.90/8.10 span, E1 5.23 body, e 1.27, b 0.35/0.42/0.48, L 0.50/0.65/0.80. + * IPC-7351 nominal gull-wing fillets (toe 0.35, heel 0.35, side 0.03): + * Z = 8.10+0.70 = 8.80, G = (7.70-1.60)-0.70 = 5.40, so pads are + * (Z-G)/2 = 1.70 long on a (Z+G)/2 = 7.10 mm centre span. + * footprinter's `soic8_wmm_p1.27mm` silently ignores the width modifier and + * returns the 150-mil pattern, so this one is spelled out. */ +export const soic8w208: LandPattern={width:5.23,height:5.28,pads:Array.from({length:8},(_,i)=>({ + pin:`pin${i+1}`, x:i<4 ? -3.55 : 3.55, + y:(i<4 ? 1.5-i : i-5.5)*1.27, + w:1.7,h:0.6, +}))} + +/** ASE-xxxMHZ-LC-T, 3.2 x 2.5 mm 4-pad oscillator. Pin 1 (enable) is lower + * left with the package dot, 2 = GND, 3 = OUT, 4 = VDD, counterclockwise. */ +export const osc3225: LandPattern={width:3.2,height:2.5,pads:[ + {pin:"pin1",x:-1.1,y:-0.8,w:1.2,h:1},{pin:"pin2",x:1.1,y:-0.8,w:1.2,h:1}, + {pin:"pin3",x:1.1,y:0.8,w:1.2,h:1},{pin:"pin4",x:-1.1,y:0.8,w:1.2,h:1}, +]} + +/** TPS62130ARGTR, VQFN-16 RGT0016C: body 2.9/3.1, 16 leads 0.18-0.30 wide and + * 0.3-0.5 long reaching 1.5 mm from centre, exposed thermal pad 1.68 +/-0.07 + * (TI datasheet SLVSAG7F section 12). Pads span 1.10-1.80 from centre, leaving + * a 0.25 mm gap to the thermal pad. + * Not `qfn16_w3_h3_p0.5mm_thermalpad`: footprinter puts the signal pads' + * inner edges at 0.525 against a 1.75 mm thermal pad, overlapping them by + * 0.35 mm and shorting every pin to the pad. */ +export const qfn16: LandPattern={width:3,height:3,pads:[ + ...Array.from({length:16},(_,i)=>{ + const side=Math.floor(i/4),t=(i%4-1.5)*0.5 + return {pin:`pin${i+1}`,x:side===0?-1.45:side===1?t:side===2?1.45:-t, + y:side===0?-t:side===1?-1.45:side===2?t:1.45, + w:side%2?0.25:0.7,h:side%2?0.7:0.25} + }),{pin:"pin17",x:0,y:0,w:1.68,h:1.68}, +]} + +/** 4 x 4 mm shielded power inductor (1 uH, >= 3 A saturation). */ +export const inductor: LandPattern={width:4,height:4,pads:[ + {pin:"pin1",x:-1.7,y:0,w:1.3,h:3.7},{pin:"pin2",x:1.7,y:0,w:1.3,h:3.7}, +]} + +/** Samtec IPT1-110-06-L-D mainboard terminal strip. + * 2x10, 2.54 mm pitch/row spacing, .64 mm square posts. Samtec's recommended + * through-hole PCB layout calls for 1.02 mm drills. The body is nominally + * 5.08 mm wide and 25.91 mm long for 10 positions per row. */ +export const stack2x10: LandPattern={width:5.08,height:25.91,pads:Array.from({length:20},(_,i)=>({ + pin:`pin${i+1}`,x:i%2===0?-1.27:1.27,y:(4.5-Math.floor(i/2))*2.54,hole:1.02,diameter:1.8, +}))} diff --git a/hardware/courant/fpga-pins.json b/hardware/courant/fpga-pins.json new file mode 100644 index 0000000..34bbfa4 --- /dev/null +++ b/hardware/courant/fpga-pins.json @@ -0,0 +1,1282 @@ +[ + { + "ball": "H10", + "function": "DONE_0", + "bank": "0" + }, + { + "ball": "K8", + "function": "DXP_0", + "bank": "0" + }, + { + "ball": "G7", + "function": "GNDADC_0", + "bank": "0" + }, + { + "ball": "G8", + "function": "VCCADC_0", + "bank": "0" + }, + { + "ball": "J8", + "function": "VREFP_0", + "bank": "0" + }, + { + "ball": "J7", + "function": "VN_0", + "bank": "0" + }, + { + "ball": "F8", + "function": "VCCBATT_0", + "bank": "0" + }, + { + "ball": "L7", + "function": "TCK_0", + "bank": "0" + }, + { + "ball": "K7", + "function": "DXN_0", + "bank": "0" + }, + { + "ball": "H7", + "function": "VREFN_0", + "bank": "0" + }, + { + "ball": "H8", + "function": "VP_0", + "bank": "0" + }, + { + "ball": "E8", + "function": "CCLK_0", + "bank": "0" + }, + { + "ball": "M9", + "function": "M0_0", + "bank": "0" + }, + { + "ball": "M10", + "function": "M1_0", + "bank": "0" + }, + { + "ball": "K10", + "function": "INIT_B_0", + "bank": "0" + }, + { + "ball": "N7", + "function": "TDI_0", + "bank": "0" + }, + { + "ball": "N8", + "function": "TDO_0", + "bank": "0" + }, + { + "ball": "M11", + "function": "M2_0", + "bank": "0" + }, + { + "ball": "E7", + "function": "CFGBVS_0", + "bank": "0" + }, + { + "ball": "L9", + "function": "PROGRAM_B_0", + "bank": "0" + }, + { + "ball": "M7", + "function": "TMS_0", + "bank": "0" + }, + { + "ball": "K12", + "function": "IO_0_14", + "bank": "14" + }, + { + "ball": "J13", + "function": "IO_L1P_T0_D00_MOSI_14", + "bank": "14" + }, + { + "ball": "J14", + "function": "IO_L1N_T0_D01_DIN_14", + "bank": "14" + }, + { + "ball": "K15", + "function": "IO_L2P_T0_D02_14", + "bank": "14" + }, + { + "ball": "K16", + "function": "IO_L2N_T0_D03_14", + "bank": "14" + }, + { + "ball": "L15", + "function": "IO_L3P_T0_DQS_PUDC_B_14", + "bank": "14" + }, + { + "ball": "M15", + "function": "IO_L3N_T0_DQS_EMCCLK_14", + "bank": "14" + }, + { + "ball": "L14", + "function": "IO_L4P_T0_D04_14", + "bank": "14" + }, + { + "ball": "M14", + "function": "IO_L4N_T0_D05_14", + "bank": "14" + }, + { + "ball": "K13", + "function": "IO_L5P_T0_D06_14", + "bank": "14" + }, + { + "ball": "L13", + "function": "IO_L5N_T0_D07_14", + "bank": "14" + }, + { + "ball": "L12", + "function": "IO_L6P_T0_FCS_B_14", + "bank": "14" + }, + { + "ball": "M12", + "function": "IO_L6N_T0_D08_VREF_14", + "bank": "14" + }, + { + "ball": "M16", + "function": "IO_L7P_T1_D09_14", + "bank": "14" + }, + { + "ball": "N16", + "function": "IO_L7N_T1_D10_14", + "bank": "14" + }, + { + "ball": "P15", + "function": "IO_L8P_T1_D11_14", + "bank": "14" + }, + { + "ball": "P16", + "function": "IO_L8N_T1_D12_14", + "bank": "14" + }, + { + "ball": "R15", + "function": "IO_L9P_T1_DQS_14", + "bank": "14" + }, + { + "ball": "R16", + "function": "IO_L9N_T1_DQS_D13_14", + "bank": "14" + }, + { + "ball": "T14", + "function": "IO_L10P_T1_D14_14", + "bank": "14" + }, + { + "ball": "T15", + "function": "IO_L10N_T1_D15_14", + "bank": "14" + }, + { + "ball": "N13", + "function": "IO_L11P_T1_SRCC_14", + "bank": "14" + }, + { + "ball": "P13", + "function": "IO_L11N_T1_SRCC_14", + "bank": "14" + }, + { + "ball": "N14", + "function": "IO_L12P_T1_MRCC_14", + "bank": "14" + }, + { + "ball": "P14", + "function": "IO_L12N_T1_MRCC_14", + "bank": "14" + }, + { + "ball": "N11", + "function": "IO_L13P_T2_MRCC_14", + "bank": "14" + }, + { + "ball": "N12", + "function": "IO_L13N_T2_MRCC_14", + "bank": "14" + }, + { + "ball": "P10", + "function": "IO_L14P_T2_SRCC_14", + "bank": "14" + }, + { + "ball": "P11", + "function": "IO_L14N_T2_SRCC_14", + "bank": "14" + }, + { + "ball": "R12", + "function": "IO_L15P_T2_DQS_RDWR_B_14", + "bank": "14" + }, + { + "ball": "T12", + "function": "IO_L15N_T2_DQS_DOUT_CSO_B_14", + "bank": "14" + }, + { + "ball": "R13", + "function": "IO_L16P_T2_CSI_B_14", + "bank": "14" + }, + { + "ball": "T13", + "function": "IO_L16N_T2_A15_D31_14", + "bank": "14" + }, + { + "ball": "R10", + "function": "IO_L17P_T2_A14_D30_14", + "bank": "14" + }, + { + "ball": "R11", + "function": "IO_L17N_T2_A13_D29_14", + "bank": "14" + }, + { + "ball": "N9", + "function": "IO_L18P_T2_A12_D28_14", + "bank": "14" + }, + { + "ball": "P9", + "function": "IO_L18N_T2_A11_D27_14", + "bank": "14" + }, + { + "ball": "M6", + "function": "IO_L19P_T3_A10_D26_14", + "bank": "14" + }, + { + "ball": "N6", + "function": "IO_L19N_T3_A09_D25_VREF_14", + "bank": "14" + }, + { + "ball": "P8", + "function": "IO_L20P_T3_A08_D24_14", + "bank": "14" + }, + { + "ball": "R8", + "function": "IO_L20N_T3_A07_D23_14", + "bank": "14" + }, + { + "ball": "T7", + "function": "IO_L21P_T3_DQS_14", + "bank": "14" + }, + { + "ball": "T8", + "function": "IO_L21N_T3_DQS_A06_D22_14", + "bank": "14" + }, + { + "ball": "T9", + "function": "IO_L22P_T3_A05_D21_14", + "bank": "14" + }, + { + "ball": "T10", + "function": "IO_L22N_T3_A04_D20_14", + "bank": "14" + }, + { + "ball": "R5", + "function": "IO_L23P_T3_A03_D19_14", + "bank": "14" + }, + { + "ball": "T5", + "function": "IO_L23N_T3_A02_D18_14", + "bank": "14" + }, + { + "ball": "R6", + "function": "IO_L24P_T3_A01_D17_14", + "bank": "14" + }, + { + "ball": "R7", + "function": "IO_L24N_T3_A00_D16_14", + "bank": "14" + }, + { + "ball": "P6", + "function": "IO_25_14", + "bank": "14" + }, + { + "ball": "D10", + "function": "IO_0_15", + "bank": "15" + }, + { + "ball": "C8", + "function": "IO_L1P_T0_AD0P_15", + "bank": "15" + }, + { + "ball": "C9", + "function": "IO_L1N_T0_AD0N_15", + "bank": "15" + }, + { + "ball": "A8", + "function": "IO_L2P_T0_AD8P_15", + "bank": "15" + }, + { + "ball": "A9", + "function": "IO_L2N_T0_AD8N_15", + "bank": "15" + }, + { + "ball": "B9", + "function": "IO_L3P_T0_DQS_AD1P_15", + "bank": "15" + }, + { + "ball": "A10", + "function": "IO_L3N_T0_DQS_AD1N_15", + "bank": "15" + }, + { + "ball": "B10", + "function": "IO_L4P_T0_15", + "bank": "15" + }, + { + "ball": "B11", + "function": "IO_L4N_T0_15", + "bank": "15" + }, + { + "ball": "B12", + "function": "IO_L5P_T0_AD9P_15", + "bank": "15" + }, + { + "ball": "A12", + "function": "IO_L5N_T0_AD9N_15", + "bank": "15" + }, + { + "ball": "D8", + "function": "IO_L6P_T0_15", + "bank": "15" + }, + { + "ball": "D9", + "function": "IO_L6N_T0_VREF_15", + "bank": "15" + }, + { + "ball": "A13", + "function": "IO_L7P_T1_AD2P_15", + "bank": "15" + }, + { + "ball": "A14", + "function": "IO_L7N_T1_AD2N_15", + "bank": "15" + }, + { + "ball": "C14", + "function": "IO_L8P_T1_AD10P_15", + "bank": "15" + }, + { + "ball": "B14", + "function": "IO_L8N_T1_AD10N_15", + "bank": "15" + }, + { + "ball": "B15", + "function": "IO_L9P_T1_DQS_AD3P_15", + "bank": "15" + }, + { + "ball": "A15", + "function": "IO_L9N_T1_DQS_AD3N_15", + "bank": "15" + }, + { + "ball": "C16", + "function": "IO_L10P_T1_AD11P_15", + "bank": "15" + }, + { + "ball": "B16", + "function": "IO_L10N_T1_AD11N_15", + "bank": "15" + }, + { + "ball": "C11", + "function": "IO_L11P_T1_SRCC_15", + "bank": "15" + }, + { + "ball": "C12", + "function": "IO_L11N_T1_SRCC_15", + "bank": "15" + }, + { + "ball": "D13", + "function": "IO_L12P_T1_MRCC_15", + "bank": "15" + }, + { + "ball": "C13", + "function": "IO_L12N_T1_MRCC_15", + "bank": "15" + }, + { + "ball": "E12", + "function": "IO_L13P_T2_MRCC_15", + "bank": "15" + }, + { + "ball": "E13", + "function": "IO_L13N_T2_MRCC_15", + "bank": "15" + }, + { + "ball": "E11", + "function": "IO_L14P_T2_SRCC_15", + "bank": "15" + }, + { + "ball": "D11", + "function": "IO_L14N_T2_SRCC_15", + "bank": "15" + }, + { + "ball": "D14", + "function": "IO_L15P_T2_DQS_15", + "bank": "15" + }, + { + "ball": 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"verify": "npm run typecheck && npm run check && tsci check netlist courant.circuit.tsx && npm run build:unrouted", + "export": "bun scripts/export.ts", + "route": "python3 scripts/route.py", + "fab": "python3 scripts/fab.py" + }, + "devDependencies": { + "@types/react": "19.3.0", + "bun": "1.4.2", + "tscircuit": "0.0.2547", + "typescript": "5.9.3" + } +} diff --git a/hardware/courant/panel.circuit.tsx b/hardware/courant/panel.circuit.tsx new file mode 100644 index 0000000..dcccc80 --- /dev/null +++ b/hardware/courant/panel.circuit.tsx @@ -0,0 +1,71 @@ +import type { ReactElement } from "react" +import design from "../panel/tscircuit-design.json" + +type Pad = { + port:string; net:string|null; x:number; y:number; sx:number; sy:number; + drill:number|number[]|null; kind:string; shape:string +} +const Cutout:any="cutout" + +type PanelPart = { + ref:string; value:string; block:string; x:number; y:number; + side:"top"|"bottom"; rotation:number; body:number[]; pads:Pad[] +} + +function padElement(p:Pad, i:number):ReactElement { + const key=`${p.port}-${i}` + const hints=p.net ? [p.port] : undefined + if(p.kind==="smd") return + if(p.kind==="np_thru_hole") { + if(Array.isArray(p.drill)) return + return + } + if(Array.isArray(p.drill)) return + if(p.shape==="rect") return + return +} + +function footprint(part:PanelPart):ReactElement { + const electrical=part.pads.filter(p=>p.net) + const xmax=Math.max(part.body[0]/2,...part.pads.map(p=>Math.abs(p.x)+p.sx/2))+.25 + const ymax=Math.max(part.body[1]/2,...part.pads.map(p=>Math.abs(p.y)+p.sy/2))+.25 + return + {part.pads.map(padElement)} + + +} +function Part({part,index}:{part:PanelPart;index:number}) { + const electrical=part.pads.filter(p=>p.net) + const pinLabels=Object.fromEntries(electrical.map(p=>[p.port,p.port])) + const connections=Object.fromEntries(electrical.map(p=>[p.port,`net.${p.net}`])) + return +} + +const parts=design.parts as PanelPart[] +const nets=[...new Set(parts.flatMap(part=>part.pads.flatMap(p=>p.net?[p.net]:[])))].sort() + +export default function Panel() { + return + + {nets.map(name=>)} + {design.windows.map((points,i)=>)} + {design.mounts.map((m,i)=>)} + {parts.map((part,index)=>)} + + + +} diff --git a/hardware/courant/reference/xc7a35tftg256pkg.txt b/hardware/courant/reference/xc7a35tftg256pkg.txt new file mode 100644 index 0000000..80b3dbe --- /dev/null +++ b/hardware/courant/reference/xc7a35tftg256pkg.txt @@ -0,0 +1,261 @@ +Device/Package xc7a35tftg256 10/4/2013 09:35:44 + +Pin Pin Name Memory Byte Group Bank VCCAUX Group Super Logic Region I/O Type No-Connect +H10 DONE_0 NA 0 NA NA CONFIG NA +K8 DXP_0 NA 0 NA NA CONFIG NA +G7 GNDADC_0 NA 0 NA NA CONFIG NA +G8 VCCADC_0 NA 0 NA NA CONFIG NA +J8 VREFP_0 NA 0 NA NA CONFIG NA +J7 VN_0 NA 0 NA NA CONFIG NA +F8 VCCBATT_0 NA 0 NA NA CONFIG NA +L7 TCK_0 NA 0 NA NA CONFIG NA +K7 DXN_0 NA 0 NA NA CONFIG NA +H7 VREFN_0 NA 0 NA NA CONFIG NA +H8 VP_0 NA 0 NA NA CONFIG NA +E8 CCLK_0 NA 0 NA NA CONFIG NA +M9 M0_0 NA 0 NA NA CONFIG NA +M10 M1_0 NA 0 NA NA CONFIG NA +K10 INIT_B_0 NA 0 NA NA CONFIG NA +N7 TDI_0 NA 0 NA NA CONFIG NA +N8 TDO_0 NA 0 NA NA CONFIG NA +M11 M2_0 NA 0 NA NA CONFIG NA +E7 CFGBVS_0 NA 0 NA NA CONFIG NA +L9 PROGRAM_B_0 NA 0 NA NA CONFIG NA +M7 TMS_0 NA 0 NA NA CONFIG NA +K12 IO_0_14 NA 14 NA NA HR NA +J13 IO_L1P_T0_D00_MOSI_14 0 14 NA NA HR NA +J14 IO_L1N_T0_D01_DIN_14 0 14 NA NA HR NA +K15 IO_L2P_T0_D02_14 0 14 NA NA HR NA +K16 IO_L2N_T0_D03_14 0 14 NA NA HR NA +L15 IO_L3P_T0_DQS_PUDC_B_14 0 14 NA NA HR NA +M15 IO_L3N_T0_DQS_EMCCLK_14 0 14 NA NA HR NA +L14 IO_L4P_T0_D04_14 0 14 NA NA HR NA +M14 IO_L4N_T0_D05_14 0 14 NA NA HR NA +K13 IO_L5P_T0_D06_14 0 14 NA NA HR NA +L13 IO_L5N_T0_D07_14 0 14 NA NA HR NA +L12 IO_L6P_T0_FCS_B_14 0 14 NA NA HR NA +M12 IO_L6N_T0_D08_VREF_14 0 14 NA NA HR NA +M16 IO_L7P_T1_D09_14 1 14 NA NA HR NA +N16 IO_L7N_T1_D10_14 1 14 NA NA HR NA +P15 IO_L8P_T1_D11_14 1 14 NA NA HR NA +P16 IO_L8N_T1_D12_14 1 14 NA NA HR NA +R15 IO_L9P_T1_DQS_14 1 14 NA NA HR NA +R16 IO_L9N_T1_DQS_D13_14 1 14 NA NA HR NA +T14 IO_L10P_T1_D14_14 1 14 NA NA HR NA +T15 IO_L10N_T1_D15_14 1 14 NA NA HR NA +N13 IO_L11P_T1_SRCC_14 1 14 NA NA HR NA +P13 IO_L11N_T1_SRCC_14 1 14 NA NA HR NA +N14 IO_L12P_T1_MRCC_14 1 14 NA NA HR NA +P14 IO_L12N_T1_MRCC_14 1 14 NA NA HR NA +N11 IO_L13P_T2_MRCC_14 2 14 NA NA HR NA +N12 IO_L13N_T2_MRCC_14 2 14 NA NA HR NA +P10 IO_L14P_T2_SRCC_14 2 14 NA NA HR NA +P11 IO_L14N_T2_SRCC_14 2 14 NA NA HR NA +R12 IO_L15P_T2_DQS_RDWR_B_14 2 14 NA NA HR NA +T12 IO_L15N_T2_DQS_DOUT_CSO_B_14 2 14 NA NA HR NA +R13 IO_L16P_T2_CSI_B_14 2 14 NA NA HR NA +T13 IO_L16N_T2_A15_D31_14 2 14 NA NA HR NA +R10 IO_L17P_T2_A14_D30_14 2 14 NA NA HR NA +R11 IO_L17N_T2_A13_D29_14 2 14 NA NA HR NA +N9 IO_L18P_T2_A12_D28_14 2 14 NA NA HR NA +P9 IO_L18N_T2_A11_D27_14 2 14 NA NA HR NA +M6 IO_L19P_T3_A10_D26_14 3 14 NA NA HR NA +N6 IO_L19N_T3_A09_D25_VREF_14 3 14 NA NA HR NA +P8 IO_L20P_T3_A08_D24_14 3 14 NA NA HR NA +R8 IO_L20N_T3_A07_D23_14 3 14 NA NA HR NA +T7 IO_L21P_T3_DQS_14 3 14 NA NA HR NA +T8 IO_L21N_T3_DQS_A06_D22_14 3 14 NA NA HR NA +T9 IO_L22P_T3_A05_D21_14 3 14 NA NA HR NA +T10 IO_L22N_T3_A04_D20_14 3 14 NA NA HR NA +R5 IO_L23P_T3_A03_D19_14 3 14 NA NA HR NA +T5 IO_L23N_T3_A02_D18_14 3 14 NA NA HR NA +R6 IO_L24P_T3_A01_D17_14 3 14 NA NA HR NA +R7 IO_L24N_T3_A00_D16_14 3 14 NA NA HR NA +P6 IO_25_14 NA 14 NA NA HR NA +D10 IO_0_15 NA 15 NA NA HR NA +C8 IO_L1P_T0_AD0P_15 0 15 NA NA HR NA +C9 IO_L1N_T0_AD0N_15 0 15 NA NA HR NA +A8 IO_L2P_T0_AD8P_15 0 15 NA NA HR NA +A9 IO_L2N_T0_AD8N_15 0 15 NA NA HR NA +B9 IO_L3P_T0_DQS_AD1P_15 0 15 NA NA HR NA +A10 IO_L3N_T0_DQS_AD1N_15 0 15 NA NA HR NA +B10 IO_L4P_T0_15 0 15 NA NA HR NA +B11 IO_L4N_T0_15 0 15 NA NA HR NA +B12 IO_L5P_T0_AD9P_15 0 15 NA NA HR NA +A12 IO_L5N_T0_AD9N_15 0 15 NA NA HR NA +D8 IO_L6P_T0_15 0 15 NA NA HR NA +D9 IO_L6N_T0_VREF_15 0 15 NA NA HR NA +A13 IO_L7P_T1_AD2P_15 1 15 NA NA HR NA +A14 IO_L7N_T1_AD2N_15 1 15 NA NA HR NA +C14 IO_L8P_T1_AD10P_15 1 15 NA NA HR NA +B14 IO_L8N_T1_AD10N_15 1 15 NA NA HR NA +B15 IO_L9P_T1_DQS_AD3P_15 1 15 NA NA HR NA +A15 IO_L9N_T1_DQS_AD3N_15 1 15 NA NA HR NA +C16 IO_L10P_T1_AD11P_15 1 15 NA NA HR NA +B16 IO_L10N_T1_AD11N_15 1 15 NA NA HR NA +C11 IO_L11P_T1_SRCC_15 1 15 NA NA HR NA +C12 IO_L11N_T1_SRCC_15 1 15 NA NA HR NA +D13 IO_L12P_T1_MRCC_15 1 15 NA NA HR NA +C13 IO_L12N_T1_MRCC_15 1 15 NA NA HR NA +E12 IO_L13P_T2_MRCC_15 2 15 NA NA HR NA +E13 IO_L13N_T2_MRCC_15 2 15 NA NA HR NA +E11 IO_L14P_T2_SRCC_15 2 15 NA NA HR NA +D11 IO_L14N_T2_SRCC_15 2 15 NA NA HR NA +D14 IO_L15P_T2_DQS_15 2 15 NA NA HR NA +D15 IO_L15N_T2_DQS_ADV_B_15 2 15 NA NA HR NA +F12 IO_L16P_T2_A28_15 2 15 NA NA HR NA +F13 IO_L16N_T2_A27_15 2 15 NA NA HR NA +E16 IO_L17P_T2_A26_15 2 15 NA NA HR NA +D16 IO_L17N_T2_A25_15 2 15 NA NA HR NA +F15 IO_L18P_T2_A24_15 2 15 NA NA HR NA +E15 IO_L18N_T2_A23_15 2 15 NA NA HR NA +H11 IO_L19P_T3_A22_15 3 15 NA NA HR NA +G12 IO_L19N_T3_A21_VREF_15 3 15 NA NA HR NA +H12 IO_L20P_T3_A20_15 3 15 NA NA HR NA +H13 IO_L20N_T3_A19_15 3 15 NA NA HR NA +G14 IO_L21P_T3_DQS_15 3 15 NA NA HR NA +F14 IO_L21N_T3_DQS_A18_15 3 15 NA NA HR NA +H16 IO_L22P_T3_A17_15 3 15 NA NA HR NA +G16 IO_L22N_T3_A16_15 3 15 NA NA HR NA +J15 IO_L23P_T3_FOE_B_15 3 15 NA NA HR NA +J16 IO_L23N_T3_FWE_B_15 3 15 NA NA HR NA +H14 IO_L24P_T3_RS1_15 3 15 NA NA HR NA +G15 IO_L24N_T3_RS0_15 3 15 NA NA HR NA +G11 IO_25_15 NA 15 NA NA HR NA +L5 IO_0_34 NA 34 NA NA HR NA +L4 IO_L1P_T0_34 0 34 NA NA HR NA +M4 IO_L1N_T0_34 0 34 NA NA HR NA +M2 IO_L2P_T0_34 0 34 NA NA HR NA +M1 IO_L2N_T0_34 0 34 NA NA HR NA +N3 IO_L3P_T0_DQS_34 0 34 NA NA HR NA +N2 IO_L3N_T0_DQS_34 0 34 NA NA HR NA +N1 IO_L4P_T0_34 0 34 NA NA HR NA +P1 IO_L4N_T0_34 0 34 NA NA HR NA +P4 IO_L5P_T0_34 0 34 NA NA HR NA +P3 IO_L5N_T0_34 0 34 NA NA HR NA +M5 IO_L6P_T0_34 0 34 NA NA HR NA +N4 IO_L6N_T0_VREF_34 0 34 NA NA HR NA +R2 IO_L7P_T1_34 1 34 NA NA HR NA +R1 IO_L7N_T1_34 1 34 NA NA HR NA +R3 IO_L8P_T1_34 1 34 NA NA HR NA +T2 IO_L8N_T1_34 1 34 NA NA HR NA +T4 IO_L9P_T1_DQS_34 1 34 NA NA HR NA +T3 IO_L9N_T1_DQS_34 1 34 NA NA HR NA +P5 IO_L10P_T1_34 1 34 NA NA HR NA +E6 IO_0_35 NA 35 NA NA HR NA +B7 IO_L1P_T0_AD4P_35 0 35 NA NA HR NA +A7 IO_L1N_T0_AD4N_35 0 35 NA NA HR NA +B6 IO_L2P_T0_AD12P_35 0 35 NA NA HR NA +B5 IO_L2N_T0_AD12N_35 0 35 NA NA HR NA +A5 IO_L3P_T0_DQS_AD5P_35 0 35 NA NA HR NA +A4 IO_L3N_T0_DQS_AD5N_35 0 35 NA NA HR NA +B4 IO_L4P_T0_35 0 35 NA NA HR NA +A3 IO_L4N_T0_35 0 35 NA NA HR NA +C7 IO_L5P_T0_AD13P_35 0 35 NA NA HR NA +C6 IO_L5N_T0_AD13N_35 0 35 NA NA HR NA +D6 IO_L6P_T0_35 0 35 NA NA HR NA +D5 IO_L6N_T0_VREF_35 0 35 NA NA HR NA +C3 IO_L7P_T1_AD6P_35 1 35 NA NA HR NA +C2 IO_L7N_T1_AD6N_35 1 35 NA NA HR NA +B2 IO_L8P_T1_AD14P_35 1 35 NA NA HR NA +A2 IO_L8N_T1_AD14N_35 1 35 NA NA HR NA +C1 IO_L9P_T1_DQS_AD7P_35 1 35 NA NA HR NA +B1 IO_L9N_T1_DQS_AD7N_35 1 35 NA NA HR NA +E2 IO_L10P_T1_AD15P_35 1 35 NA NA HR NA +D1 IO_L10N_T1_AD15N_35 1 35 NA NA HR NA +E3 IO_L11P_T1_SRCC_35 1 35 NA NA HR NA +D3 IO_L11N_T1_SRCC_35 1 35 NA NA HR NA +D4 IO_L12P_T1_MRCC_35 1 35 NA NA HR NA +C4 IO_L12N_T1_MRCC_35 1 35 NA NA HR NA +F5 IO_L13P_T2_MRCC_35 2 35 NA NA HR NA +E5 IO_L13N_T2_MRCC_35 2 35 NA NA HR NA +F4 IO_L14P_T2_SRCC_35 2 35 NA NA HR NA +F3 IO_L14N_T2_SRCC_35 2 35 NA NA HR NA +F2 IO_L15P_T2_DQS_35 2 35 NA NA HR NA +E1 IO_L15N_T2_DQS_35 2 35 NA NA HR NA +G5 IO_L16P_T2_35 2 35 NA NA HR NA +G4 IO_L16N_T2_35 2 35 NA NA HR NA +G2 IO_L17P_T2_35 2 35 NA NA HR NA +G1 IO_L17N_T2_35 2 35 NA NA HR NA +H5 IO_L18P_T2_35 2 35 NA NA HR NA +H4 IO_L18N_T2_35 2 35 NA NA HR NA +J5 IO_L19P_T3_35 3 35 NA NA HR NA +J4 IO_L19N_T3_VREF_35 3 35 NA NA HR NA +H2 IO_L20P_T3_35 3 35 NA NA HR NA +H1 IO_L20N_T3_35 3 35 NA NA HR NA +J3 IO_L21P_T3_DQS_35 3 35 NA NA HR NA +H3 IO_L21N_T3_DQS_35 3 35 NA NA HR NA +K1 IO_L22P_T3_35 3 35 NA NA HR NA +J1 IO_L22N_T3_35 3 35 NA NA HR NA +L3 IO_L23P_T3_35 3 35 NA NA HR NA +L2 IO_L23N_T3_35 3 35 NA NA HR NA +K3 IO_L24P_T3_35 3 35 NA NA HR NA +K2 IO_L24N_T3_35 3 35 NA NA HR NA +K5 IO_25_35 NA 35 NA NA HR NA +A1 GND NA NA NA NA NA NA +A11 GND NA NA NA NA NA NA +B8 GND NA NA NA NA NA NA +C5 GND NA NA NA NA NA NA +C15 GND NA NA NA NA NA NA +D2 GND NA NA NA NA NA NA +D12 GND NA NA NA NA NA NA +E9 GND NA NA NA NA NA NA +F6 GND NA NA NA NA NA NA +F10 GND NA NA NA NA NA NA +F16 GND NA NA NA NA NA NA +G3 GND NA NA NA NA NA NA +G9 GND NA NA NA NA NA NA +G13 GND NA NA NA NA NA NA +H6 GND NA NA NA NA NA NA +J9 GND NA NA NA NA NA NA +J11 GND NA NA NA NA NA NA +K4 GND NA NA NA NA NA NA +K6 GND NA NA NA NA NA NA +K14 GND NA NA NA NA NA NA +L1 GND NA NA NA NA NA NA +L11 GND NA NA NA NA NA NA +M8 GND NA NA NA NA NA NA +N5 GND NA NA NA NA NA NA +N15 GND NA NA NA NA NA NA +P2 GND NA NA NA NA NA NA +P12 GND NA NA NA NA NA NA +R9 GND NA NA NA NA NA NA +T6 GND NA NA NA NA NA NA +T16 GND NA NA NA NA NA NA +F7 VCCINT NA NA NA NA NA NA +F9 VCCINT NA NA NA NA NA NA +G6 VCCINT NA NA NA NA NA NA +H9 VCCINT NA NA NA NA NA NA +J6 VCCINT NA NA NA NA NA NA +K9 VCCINT NA NA NA NA NA NA +L8 VCCINT NA NA NA NA NA NA +G10 VCCAUX NA NA NA NA NA NA +J10 VCCAUX NA NA NA NA NA NA +K11 VCCAUX NA NA NA NA NA NA +L10 VCCAUX NA NA NA NA NA NA +L6 VCCO_0 NA 0 NA NA NA NA +L16 VCCO_14 NA 14 NA NA NA NA +M13 VCCO_14 NA 14 NA NA NA NA +N10 VCCO_14 NA 14 NA NA NA NA +P7 VCCO_14 NA 14 NA NA NA NA +R14 VCCO_14 NA 14 NA NA NA NA +T11 VCCO_14 NA 14 NA NA NA NA +A16 VCCO_15 NA 15 NA NA NA NA +B13 VCCO_15 NA 15 NA NA NA NA +C10 VCCO_15 NA 15 NA NA NA NA +E14 VCCO_15 NA 15 NA NA NA NA +H15 VCCO_15 NA 15 NA NA NA NA +J12 VCCO_15 NA 15 NA NA NA NA +M3 VCCO_34 NA 34 NA NA NA NA +R4 VCCO_34 NA 34 NA NA NA NA +T1 VCCO_34 NA 34 NA NA NA NA +A6 VCCO_35 NA 35 NA NA NA NA +B3 VCCO_35 NA 35 NA NA NA NA +D7 VCCO_35 NA 35 NA NA NA NA +E4 VCCO_35 NA 35 NA NA NA NA +F1 VCCO_35 NA 35 NA NA NA NA +J2 VCCO_35 NA 35 NA NA NA NA +E10 VCCBRAM NA NA NA NA NA NA +F11 VCCBRAM NA NA NA NA NA NA + +Total Number of Pins, 256 diff --git a/hardware/courant/reference/xc7a50tftg256pkg.txt b/hardware/courant/reference/xc7a50tftg256pkg.txt new file mode 100644 index 0000000..1a54251 --- /dev/null +++ b/hardware/courant/reference/xc7a50tftg256pkg.txt @@ -0,0 +1,261 @@ +Device/Package xc7a50tftg256 10/4/2013 09:35:44 + +Pin Pin Name Memory Byte Group Bank VCCAUX Group Super Logic Region I/O Type No-Connect +H10 DONE_0 NA 0 NA NA CONFIG NA +K8 DXP_0 NA 0 NA NA CONFIG NA +G7 GNDADC_0 NA 0 NA NA CONFIG NA +G8 VCCADC_0 NA 0 NA NA CONFIG NA +J8 VREFP_0 NA 0 NA NA CONFIG NA +J7 VN_0 NA 0 NA NA CONFIG NA +F8 VCCBATT_0 NA 0 NA NA CONFIG NA +L7 TCK_0 NA 0 NA NA CONFIG NA +K7 DXN_0 NA 0 NA NA CONFIG NA +H7 VREFN_0 NA 0 NA NA CONFIG NA +H8 VP_0 NA 0 NA NA CONFIG NA +E8 CCLK_0 NA 0 NA NA CONFIG NA +M9 M0_0 NA 0 NA NA CONFIG NA +M10 M1_0 NA 0 NA NA CONFIG NA +K10 INIT_B_0 NA 0 NA NA CONFIG NA +N7 TDI_0 NA 0 NA NA CONFIG NA +N8 TDO_0 NA 0 NA NA CONFIG NA +M11 M2_0 NA 0 NA NA CONFIG NA +E7 CFGBVS_0 NA 0 NA NA CONFIG NA +L9 PROGRAM_B_0 NA 0 NA NA CONFIG NA +M7 TMS_0 NA 0 NA NA CONFIG NA +K12 IO_0_14 NA 14 NA NA HR NA +J13 IO_L1P_T0_D00_MOSI_14 0 14 NA NA HR NA +J14 IO_L1N_T0_D01_DIN_14 0 14 NA NA HR NA +K15 IO_L2P_T0_D02_14 0 14 NA NA HR NA +K16 IO_L2N_T0_D03_14 0 14 NA NA HR NA +L15 IO_L3P_T0_DQS_PUDC_B_14 0 14 NA NA HR NA +M15 IO_L3N_T0_DQS_EMCCLK_14 0 14 NA NA HR NA +L14 IO_L4P_T0_D04_14 0 14 NA NA HR NA +M14 IO_L4N_T0_D05_14 0 14 NA NA HR NA +K13 IO_L5P_T0_D06_14 0 14 NA NA HR NA +L13 IO_L5N_T0_D07_14 0 14 NA NA HR NA +L12 IO_L6P_T0_FCS_B_14 0 14 NA NA HR NA +M12 IO_L6N_T0_D08_VREF_14 0 14 NA NA HR NA +M16 IO_L7P_T1_D09_14 1 14 NA NA HR NA +N16 IO_L7N_T1_D10_14 1 14 NA NA HR NA +P15 IO_L8P_T1_D11_14 1 14 NA NA HR NA +P16 IO_L8N_T1_D12_14 1 14 NA NA HR NA +R15 IO_L9P_T1_DQS_14 1 14 NA NA HR NA +R16 IO_L9N_T1_DQS_D13_14 1 14 NA NA HR NA +T14 IO_L10P_T1_D14_14 1 14 NA NA HR NA +T15 IO_L10N_T1_D15_14 1 14 NA NA HR NA +N13 IO_L11P_T1_SRCC_14 1 14 NA NA HR NA +P13 IO_L11N_T1_SRCC_14 1 14 NA NA HR NA +N14 IO_L12P_T1_MRCC_14 1 14 NA NA HR NA +P14 IO_L12N_T1_MRCC_14 1 14 NA NA HR NA +N11 IO_L13P_T2_MRCC_14 2 14 NA NA HR NA +N12 IO_L13N_T2_MRCC_14 2 14 NA NA HR NA +P10 IO_L14P_T2_SRCC_14 2 14 NA NA HR NA +P11 IO_L14N_T2_SRCC_14 2 14 NA NA HR NA +R12 IO_L15P_T2_DQS_RDWR_B_14 2 14 NA NA HR NA +T12 IO_L15N_T2_DQS_DOUT_CSO_B_14 2 14 NA NA HR NA +R13 IO_L16P_T2_CSI_B_14 2 14 NA NA HR NA +T13 IO_L16N_T2_A15_D31_14 2 14 NA NA HR NA +R10 IO_L17P_T2_A14_D30_14 2 14 NA NA HR NA +R11 IO_L17N_T2_A13_D29_14 2 14 NA NA HR NA +N9 IO_L18P_T2_A12_D28_14 2 14 NA NA HR NA +P9 IO_L18N_T2_A11_D27_14 2 14 NA NA HR NA +M6 IO_L19P_T3_A10_D26_14 3 14 NA NA HR NA +N6 IO_L19N_T3_A09_D25_VREF_14 3 14 NA NA HR NA +P8 IO_L20P_T3_A08_D24_14 3 14 NA NA HR NA +R8 IO_L20N_T3_A07_D23_14 3 14 NA NA HR NA +T7 IO_L21P_T3_DQS_14 3 14 NA NA HR NA +T8 IO_L21N_T3_DQS_A06_D22_14 3 14 NA NA HR NA +T9 IO_L22P_T3_A05_D21_14 3 14 NA NA HR NA +T10 IO_L22N_T3_A04_D20_14 3 14 NA NA HR NA +R5 IO_L23P_T3_A03_D19_14 3 14 NA NA HR NA +T5 IO_L23N_T3_A02_D18_14 3 14 NA NA HR NA +R6 IO_L24P_T3_A01_D17_14 3 14 NA NA HR NA +R7 IO_L24N_T3_A00_D16_14 3 14 NA NA HR NA +P6 IO_25_14 NA 14 NA NA HR NA +D10 IO_0_15 NA 15 NA NA HR NA +C8 IO_L1P_T0_AD0P_15 0 15 NA NA HR NA +C9 IO_L1N_T0_AD0N_15 0 15 NA NA HR NA +A8 IO_L2P_T0_AD8P_15 0 15 NA NA HR NA +A9 IO_L2N_T0_AD8N_15 0 15 NA NA HR NA +B9 IO_L3P_T0_DQS_AD1P_15 0 15 NA NA HR NA +A10 IO_L3N_T0_DQS_AD1N_15 0 15 NA NA HR NA +B10 IO_L4P_T0_15 0 15 NA NA HR NA +B11 IO_L4N_T0_15 0 15 NA NA HR NA +B12 IO_L5P_T0_AD9P_15 0 15 NA NA HR NA +A12 IO_L5N_T0_AD9N_15 0 15 NA NA HR NA +D8 IO_L6P_T0_15 0 15 NA NA HR NA +D9 IO_L6N_T0_VREF_15 0 15 NA NA HR NA +A13 IO_L7P_T1_AD2P_15 1 15 NA NA HR NA +A14 IO_L7N_T1_AD2N_15 1 15 NA NA HR NA +C14 IO_L8P_T1_AD10P_15 1 15 NA NA HR NA +B14 IO_L8N_T1_AD10N_15 1 15 NA NA HR NA +B15 IO_L9P_T1_DQS_AD3P_15 1 15 NA NA HR NA +A15 IO_L9N_T1_DQS_AD3N_15 1 15 NA NA HR NA +C16 IO_L10P_T1_AD11P_15 1 15 NA NA HR NA +B16 IO_L10N_T1_AD11N_15 1 15 NA NA HR NA +C11 IO_L11P_T1_SRCC_15 1 15 NA NA HR NA +C12 IO_L11N_T1_SRCC_15 1 15 NA NA HR NA +D13 IO_L12P_T1_MRCC_15 1 15 NA NA HR NA +C13 IO_L12N_T1_MRCC_15 1 15 NA NA HR NA +E12 IO_L13P_T2_MRCC_15 2 15 NA NA HR NA +E13 IO_L13N_T2_MRCC_15 2 15 NA NA HR NA +E11 IO_L14P_T2_SRCC_15 2 15 NA NA HR NA +D11 IO_L14N_T2_SRCC_15 2 15 NA NA HR NA +D14 IO_L15P_T2_DQS_15 2 15 NA NA HR NA +D15 IO_L15N_T2_DQS_ADV_B_15 2 15 NA NA HR NA +F12 IO_L16P_T2_A28_15 2 15 NA NA HR NA +F13 IO_L16N_T2_A27_15 2 15 NA NA HR NA +E16 IO_L17P_T2_A26_15 2 15 NA NA HR NA +D16 IO_L17N_T2_A25_15 2 15 NA NA HR NA +F15 IO_L18P_T2_A24_15 2 15 NA NA HR NA +E15 IO_L18N_T2_A23_15 2 15 NA NA HR NA +H11 IO_L19P_T3_A22_15 3 15 NA NA HR NA +G12 IO_L19N_T3_A21_VREF_15 3 15 NA NA HR NA +H12 IO_L20P_T3_A20_15 3 15 NA NA HR NA +H13 IO_L20N_T3_A19_15 3 15 NA NA HR NA +G14 IO_L21P_T3_DQS_15 3 15 NA NA HR NA +F14 IO_L21N_T3_DQS_A18_15 3 15 NA NA HR NA +H16 IO_L22P_T3_A17_15 3 15 NA NA HR NA +G16 IO_L22N_T3_A16_15 3 15 NA NA HR NA +J15 IO_L23P_T3_FOE_B_15 3 15 NA NA HR NA +J16 IO_L23N_T3_FWE_B_15 3 15 NA NA HR NA +H14 IO_L24P_T3_RS1_15 3 15 NA NA HR NA +G15 IO_L24N_T3_RS0_15 3 15 NA NA HR NA +G11 IO_25_15 NA 15 NA NA HR NA +L5 IO_0_34 NA 34 NA NA HR NA +L4 IO_L1P_T0_34 0 34 NA NA HR NA +M4 IO_L1N_T0_34 0 34 NA NA HR NA +M2 IO_L2P_T0_34 0 34 NA NA HR NA +M1 IO_L2N_T0_34 0 34 NA NA HR NA +N3 IO_L3P_T0_DQS_34 0 34 NA NA HR NA +N2 IO_L3N_T0_DQS_34 0 34 NA NA HR NA +N1 IO_L4P_T0_34 0 34 NA NA HR NA +P1 IO_L4N_T0_34 0 34 NA NA HR NA +P4 IO_L5P_T0_34 0 34 NA NA HR NA +P3 IO_L5N_T0_34 0 34 NA NA HR NA +M5 IO_L6P_T0_34 0 34 NA NA HR NA +N4 IO_L6N_T0_VREF_34 0 34 NA NA HR NA +R2 IO_L7P_T1_34 1 34 NA NA HR NA +R1 IO_L7N_T1_34 1 34 NA NA HR NA +R3 IO_L8P_T1_34 1 34 NA NA HR NA +T2 IO_L8N_T1_34 1 34 NA NA HR NA +T4 IO_L9P_T1_DQS_34 1 34 NA NA HR NA +T3 IO_L9N_T1_DQS_34 1 34 NA NA HR NA +P5 IO_L10P_T1_34 1 34 NA NA HR NA +E6 IO_0_35 NA 35 NA NA HR NA +B7 IO_L1P_T0_AD4P_35 0 35 NA NA HR NA +A7 IO_L1N_T0_AD4N_35 0 35 NA NA HR NA +B6 IO_L2P_T0_AD12P_35 0 35 NA NA HR NA +B5 IO_L2N_T0_AD12N_35 0 35 NA NA HR NA +A5 IO_L3P_T0_DQS_AD5P_35 0 35 NA NA HR NA +A4 IO_L3N_T0_DQS_AD5N_35 0 35 NA NA HR NA +B4 IO_L4P_T0_35 0 35 NA NA HR NA +A3 IO_L4N_T0_35 0 35 NA NA HR NA +C7 IO_L5P_T0_AD13P_35 0 35 NA NA HR NA +C6 IO_L5N_T0_AD13N_35 0 35 NA NA HR NA +D6 IO_L6P_T0_35 0 35 NA NA HR NA +D5 IO_L6N_T0_VREF_35 0 35 NA NA HR NA +C3 IO_L7P_T1_AD6P_35 1 35 NA NA HR NA +C2 IO_L7N_T1_AD6N_35 1 35 NA NA HR NA +B2 IO_L8P_T1_AD14P_35 1 35 NA NA HR NA +A2 IO_L8N_T1_AD14N_35 1 35 NA NA HR NA +C1 IO_L9P_T1_DQS_AD7P_35 1 35 NA NA HR NA +B1 IO_L9N_T1_DQS_AD7N_35 1 35 NA NA HR NA +E2 IO_L10P_T1_AD15P_35 1 35 NA NA HR NA +D1 IO_L10N_T1_AD15N_35 1 35 NA NA HR NA +E3 IO_L11P_T1_SRCC_35 1 35 NA NA HR NA +D3 IO_L11N_T1_SRCC_35 1 35 NA NA HR NA +D4 IO_L12P_T1_MRCC_35 1 35 NA NA HR NA +C4 IO_L12N_T1_MRCC_35 1 35 NA NA HR NA +F5 IO_L13P_T2_MRCC_35 2 35 NA NA HR NA +E5 IO_L13N_T2_MRCC_35 2 35 NA NA HR NA +F4 IO_L14P_T2_SRCC_35 2 35 NA NA HR NA +F3 IO_L14N_T2_SRCC_35 2 35 NA NA HR NA +F2 IO_L15P_T2_DQS_35 2 35 NA NA HR NA +E1 IO_L15N_T2_DQS_35 2 35 NA NA HR NA +G5 IO_L16P_T2_35 2 35 NA NA HR NA +G4 IO_L16N_T2_35 2 35 NA NA HR NA +G2 IO_L17P_T2_35 2 35 NA NA HR NA +G1 IO_L17N_T2_35 2 35 NA NA HR NA +H5 IO_L18P_T2_35 2 35 NA NA HR NA +H4 IO_L18N_T2_35 2 35 NA NA HR NA +J5 IO_L19P_T3_35 3 35 NA NA HR NA +J4 IO_L19N_T3_VREF_35 3 35 NA NA HR NA +H2 IO_L20P_T3_35 3 35 NA NA HR NA +H1 IO_L20N_T3_35 3 35 NA NA HR NA +J3 IO_L21P_T3_DQS_35 3 35 NA NA HR NA +H3 IO_L21N_T3_DQS_35 3 35 NA NA HR NA +K1 IO_L22P_T3_35 3 35 NA NA HR NA +J1 IO_L22N_T3_35 3 35 NA NA HR NA +L3 IO_L23P_T3_35 3 35 NA NA HR NA +L2 IO_L23N_T3_35 3 35 NA NA HR NA +K3 IO_L24P_T3_35 3 35 NA NA HR NA +K2 IO_L24N_T3_35 3 35 NA NA HR NA +K5 IO_25_35 NA 35 NA NA HR NA +A1 GND NA NA NA NA NA NA +A11 GND NA NA NA NA NA NA +B8 GND NA NA NA NA NA NA +C5 GND NA NA NA NA NA NA +C15 GND NA NA NA NA NA NA +D2 GND NA NA NA NA NA NA +D12 GND NA NA NA NA NA NA +E9 GND NA NA NA NA NA NA +F6 GND NA NA NA NA NA NA +F10 GND NA NA NA NA NA NA +F16 GND NA NA NA NA NA NA +G3 GND NA NA NA NA NA NA +G9 GND NA NA NA NA NA NA +G13 GND NA NA NA NA NA NA +H6 GND NA NA NA NA NA NA +J9 GND NA NA NA NA NA NA +J11 GND NA NA NA NA NA NA +K4 GND NA NA NA NA NA NA +K6 GND NA NA NA NA NA NA +K14 GND NA NA NA NA NA NA +L1 GND NA NA NA NA NA NA +L11 GND NA NA NA NA NA NA +M8 GND NA NA NA NA NA NA +N5 GND NA NA NA NA NA NA +N15 GND NA NA NA NA NA NA +P2 GND NA NA NA NA NA NA +P12 GND NA NA NA NA NA NA +R9 GND NA NA NA NA NA NA +T6 GND NA NA NA NA NA NA +T16 GND NA NA NA NA NA NA +F7 VCCINT NA NA NA NA NA NA +F9 VCCINT NA NA NA NA NA NA +G6 VCCINT NA NA NA NA NA NA +H9 VCCINT NA NA NA NA NA NA +J6 VCCINT NA NA NA NA NA NA +K9 VCCINT NA NA NA NA NA NA +L8 VCCINT NA NA NA NA NA NA +G10 VCCAUX NA NA NA NA NA NA +J10 VCCAUX NA NA NA NA NA NA +K11 VCCAUX NA NA NA NA NA NA +L10 VCCAUX NA NA NA NA NA NA +L6 VCCO_0 NA 0 NA NA NA NA +L16 VCCO_14 NA 14 NA NA NA NA +M13 VCCO_14 NA 14 NA NA NA NA +N10 VCCO_14 NA 14 NA NA NA NA +P7 VCCO_14 NA 14 NA NA NA NA +R14 VCCO_14 NA 14 NA NA NA NA +T11 VCCO_14 NA 14 NA NA NA NA +A16 VCCO_15 NA 15 NA NA NA NA +B13 VCCO_15 NA 15 NA NA NA NA +C10 VCCO_15 NA 15 NA NA NA NA +E14 VCCO_15 NA 15 NA NA NA NA +H15 VCCO_15 NA 15 NA NA NA NA +J12 VCCO_15 NA 15 NA NA NA NA +M3 VCCO_34 NA 34 NA NA NA NA +R4 VCCO_34 NA 34 NA NA NA NA +T1 VCCO_34 NA 34 NA NA NA NA +A6 VCCO_35 NA 35 NA NA NA NA +B3 VCCO_35 NA 35 NA NA NA NA +D7 VCCO_35 NA 35 NA NA NA NA +E4 VCCO_35 NA 35 NA NA NA NA +F1 VCCO_35 NA 35 NA NA NA NA +J2 VCCO_35 NA 35 NA NA NA NA +E10 VCCBRAM NA NA NA NA NA NA +F11 VCCBRAM NA NA NA NA NA NA + +Total Number of Pins, 256 diff --git a/hardware/courant/reports/mainboard_exact_parts.json b/hardware/courant/reports/mainboard_exact_parts.json new file mode 100644 index 0000000..57f874a --- /dev/null +++ b/hardware/courant/reports/mainboard_exact_parts.json @@ -0,0 +1,51 @@ +{ + "status": "PASS", + "board": "courant/deliverables/courant.kicad_pcb", + "board_sha256": "92e66042479df826fed7b9fa62116f5fa4a31a84fc075922198cf18b91b7c6c5", + "bom_rows_after_regeneration": 54, + "bom_placements": 180, + "manufacturer_mpn_coverage": "180/180", + "visible_3d_model_coverage": "180/180", + "active_generator_aliases": [], + "native_drc": { + "violations": 0, + "unconnected_items": 0 + }, + "routing_preservation": { + "tracks_vias_identical_to_pre_reconciliation": true, + "footprint_positions_orientations_sides_identical": true, + "pad_positions_sizes_nets_layers_identical": true, + "intentional_change": "J1-J4 Molex KK-254 finished-hole drills 1.00 -> 1.02 mm; connector courtyards and metadata/models corrected" + }, + "key_parts": { + "U1": "AMD/Xilinx XC7A50T-1FTG256I", + "U5": "Texas Instruments REF3125AIDBZR", + "Y1": "Abracon ASE-100.000MHZ-LC-T", + "Y2": "Abracon ASE-12.288MHZ-LC-T", + "L1-L3": "Changjiang Electronics FNR4030S1R0MT", + "D10-D12": "Nexperia BAT54S,215", + "D20": "Diodes Incorporated 1N4148W-7-F", + "J1/J3/J4": "Molex 22-23-2021", + "J2": "Molex 22-23-2061", + "J17/J18": "Samtec IPT1-110-06-L-D" + }, + "direct_stack": { + "status": "PASS", + "matched": 40, + "checked": 40 + }, + "case_cad": { + "panel_component_vs_mainboard_clashes": [], + "changed_enclosure_unintended_intersections": [], + "pcb_gap_mm": 19.99 + }, + "model_notes": { + "Molex_J1-J4": "drawing-derived reference solids; Molex vendor STEP download was not available during this pass", + "Samtec_J17-J18": "drawing-derived reference solids", + "other_BOM_parts": "project-local exact or package-accurate STEP models" + }, + "release_gate": "Physical first article still required for solderability, connector fit/retention, thermal/power/fault and functional qualification.", + "model_corrections": { + "U8": "H11L1M model pin-center aligned: standard DIP model shifted -3.81,+2.54 mm in STEP coordinates; KiCad Y inversion yields exact six-pad match. Placed U8 STEP body center 48.000,-139.009 mm vs footprint 48.000,-139.000 mm." + } +} diff --git a/hardware/courant/reports/native/drc-after-header-removal-stage1.json b/hardware/courant/reports/native/drc-after-header-removal-stage1.json new file mode 100644 index 0000000..ad46385 --- /dev/null +++ b/hardware/courant/reports/native/drc-after-header-removal-stage1.json @@ -0,0 +1,308 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T04:07:18", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "courant.kicad_pcb", + "unconnected_items": [], + "violations": [ + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [cv_select] on F.Cu, length 5.4094 mm", + "pos": { + "x": 145.0, + "y": 60.0 + }, + "uuid": "d81d4d51-ee9f-4662-b994-465fd758ee7d" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [ENC_SW_RAW] on F.Cu, length 6.9917 mm", + "pos": { + "x": 123.54, + "y": 60.0 + }, + "uuid": "c613be8d-4633-44c4-989d-e135ae36ea58" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [VREF25] on In2.Cu, length 0.9767 mm", + "pos": { + "x": 61.46, + "y": 60.0 + }, + "uuid": "60f48f4c-a09e-41e9-9f40-520ffc8791e1" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [POT_DECAY_RAW] on F.Cu, length 5.8017 mm", + "pos": { + "x": 82.0, + "y": 60.0 + }, + "uuid": "2420a937-8ae4-4b40-ab2c-bb682daa8932" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [MIDI5] on In2.Cu, length 2.0932 mm", + "pos": { + "x": 29.4803, + "y": 140.21 + }, + "uuid": "4d7850ca-ba31-4f5e-bec1-13602ba25cac" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [LINE_L] on In2.Cu, length 0.9770 mm", + "pos": { + "x": 171.0, + "y": 89.46 + }, + "uuid": "1a0c52b1-68e0-4f8b-a310-4632a58ef9b5" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [ENC_A_RAW] on F.Cu, length 0.9767 mm", + "pos": { + "x": 115.92, + "y": 60.0 + }, + "uuid": "1df5410d-3bb9-44c1-9cac-ecce0baebca4" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [ENC_B_RAW] on F.Cu, length 8.1233 mm", + "pos": { + "x": 121.0, + "y": 60.0 + }, + "uuid": "11d071cc-36e9-4b5c-ba9f-a3e6bdab2750" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [PITCH_IN] on F.Cu, length 7.1630 mm", + "pos": { + "x": 172.0, + "y": 116.73 + }, + "uuid": "d6fab9ab-cabc-46ea-ad42-049448d1eeb7" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [LINE_R] on In2.Cu, length 0.7778 mm", + "pos": { + "x": 171.0, + "y": 94.54 + }, + "uuid": "e12a802a-a7c5-4014-8a13-4b1efdd1a1f1" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [MOD_IN] on F.Cu, length 7.1630 mm", + "pos": { + "x": 172.0, + "y": 129.73 + }, + "uuid": "4fb08a80-a65d-42d1-aae5-5eb96acd240a" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [GATE_IN] on F.Cu, length 0.9770 mm", + "pos": { + "x": 171.0, + "y": 139.73 + }, + "uuid": "d1ac5d6b-1e14-42d4-8f7a-207c6e9e2326" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [LED1_A] on F.Cu, length 0.2475 mm", + "pos": { + "x": 164.0, + "y": 60.0 + }, + "uuid": "2a1eee80-a41a-4d18-9499-35ac7cdfc697" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [POT_PITCH_RAW] on F.Cu, length 5.8017 mm", + "pos": { + "x": 64.0, + "y": 60.0 + }, + "uuid": "10047635-61f3-4a88-a364-32d02d35b7d7" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [LED0_A] on F.Cu, length 6.9917 mm", + "pos": { + "x": 161.46, + "y": 60.0 + }, + "uuid": "7acbfab2-50d7-4357-a200-459614694fa1" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [MIDI4] on F.Cu, length 0.9770 mm", + "pos": { + "x": 28.0, + "y": 141.27 + }, + "uuid": "a05cedd0-7928-449c-b2b6-06ce8429b7be" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [LED2_A] on F.Cu, length 0.9308 mm", + "pos": { + "x": 166.54, + "y": 60.0 + }, + "uuid": "8b6d1289-e20f-41b2-84b1-598865d79555" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [POT_TIMBRE_RAW] on F.Cu, length 5.8017 mm", + "pos": { + "x": 100.0, + "y": 60.0 + }, + "uuid": "e66ef71b-46b8-4f18-9d4a-7878d8396092" + } + ], + "severity": "warning", + "type": "track_dangling" + } + ] +} diff --git a/hardware/courant/reports/native/drc-after-header-removal.json b/hardware/courant/reports/native/drc-after-header-removal.json new file mode 100644 index 0000000..c9e408c --- /dev/null +++ b/hardware/courant/reports/native/drc-after-header-removal.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T04:10:01", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "courant.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/courant/reports/native/drc-current.json b/hardware/courant/reports/native/drc-current.json new file mode 100644 index 0000000..e4d6960 --- /dev/null +++ b/hardware/courant/reports/native/drc-current.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T04:00:27", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "courant.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/courant/reports/native/drc-exact-parts-final.json b/hardware/courant/reports/native/drc-exact-parts-final.json new file mode 100644 index 0000000..06b1ec9 --- /dev/null +++ b/hardware/courant/reports/native/drc-exact-parts-final.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T06:46:11", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "courant.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/courant/reports/native/drc-exact-parts.json b/hardware/courant/reports/native/drc-exact-parts.json new file mode 100644 index 0000000..0a06945 --- /dev/null +++ b/hardware/courant/reports/native/drc-exact-parts.json @@ -0,0 +1,6383 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T06:42:40", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + 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{ + "x": 180.0, + "y": 150.0 + }, + "uuid": "258a3cb7-4f08-4def-84b1-71795cdeb459" + } + ], + "severity": "warning", + "type": "silk_edge_clearance" + } + ] +} diff --git a/hardware/courant/reports/native/drc-final-colored-cad.json b/hardware/courant/reports/native/drc-final-colored-cad.json new file mode 100644 index 0000000..af1e97b --- /dev/null +++ b/hardware/courant/reports/native/drc-final-colored-cad.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T16:43:46", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "courant.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/courant/reports/native/drc-prune-legacy.json b/hardware/courant/reports/native/drc-prune-legacy.json new file mode 100644 index 0000000..03feb68 --- /dev/null +++ b/hardware/courant/reports/native/drc-prune-legacy.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T04:09:50", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "courant.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/courant/reports/native/drc-u8-corrected.json b/hardware/courant/reports/native/drc-u8-corrected.json new file mode 100644 index 0000000..a011523 --- /dev/null +++ b/hardware/courant/reports/native/drc-u8-corrected.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T16:31:36", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "courant.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/courant/reports/native/drc-u8-model-fix.json b/hardware/courant/reports/native/drc-u8-model-fix.json new file mode 100644 index 0000000..fefde78 --- /dev/null +++ b/hardware/courant/reports/native/drc-u8-model-fix.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T07:06:56", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "courant.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/courant/reports/native/drc-u8-pin-aligned.json b/hardware/courant/reports/native/drc-u8-pin-aligned.json new file mode 100644 index 0000000..6f02fef --- /dev/null +++ b/hardware/courant/reports/native/drc-u8-pin-aligned.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T16:33:03", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "courant.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/courant/reports/native/drc.command.json b/hardware/courant/reports/native/drc.command.json new file mode 100644 index 0000000..24cef39 --- /dev/null +++ b/hardware/courant/reports/native/drc.command.json @@ -0,0 +1,17 @@ +{ + "command": [ + "/home/ik/ChatGPT/RADIAN_Backplane_review_3ldc8m0x/tools/runtime/backplane-kicad-linux-x86_64-10.0.6/bin/kicad-cli", + "pcb", + "drc", + "--refill-zones", + "--all-track-errors", + "--severity-all", + "--exit-code-violations", + "--format", + "json", + "--output", + "/home/ik/ChatGPT/RADIAN_Release_Sync_20260916T015425Z/reports/published_main_drc.json", + "/home/ik/ChatGPT/Courant/hardware/courant/deliverables/courant.kicad_pcb" + ], + "exit_code": 0 +} \ No newline at end of file diff --git a/hardware/courant/reports/native/drc.json b/hardware/courant/reports/native/drc.json new file mode 100644 index 0000000..dfa90a6 --- /dev/null +++ b/hardware/courant/reports/native/drc.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T03:42:52", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "courant.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/courant/reports/native/drc.log b/hardware/courant/reports/native/drc.log new file mode 100644 index 0000000..2396d85 --- /dev/null +++ b/hardware/courant/reports/native/drc.log @@ -0,0 +1,4 @@ +Found 0 violations +Found 0 unconnected items +Saved DRC Report to /home/ik/ChatGPT/RADIAN_Release_Sync_20260916T015425Z/reports/published_main_drc.json + diff --git a/hardware/courant/reports/native/status.txt b/hardware/courant/reports/native/status.txt new file mode 100644 index 0000000..dac2f66 --- /dev/null +++ b/hardware/courant/reports/native/status.txt @@ -0,0 +1 @@ +DRC exit=0 diff --git a/hardware/courant/scripts/bga_escape.py b/hardware/courant/scripts/bga_escape.py new file mode 100644 index 0000000..14f7bb7 --- /dev/null +++ b/hardware/courant/scripts/bga_escape.py @@ -0,0 +1,430 @@ +#!/usr/bin/env python3 +""" +Escape the remaining BGA balls: free a slot if a capacitor is on it, then route. + +The connections the autorouter leaves on this board all start at a BGA ball +that has no usable escape. Three facts make them tractable, and missing any one +of them is what defeated earlier attempts here: + + * Only the four *adjacent* diagonal slots are reachable. A slot two pitches + away may be clear and still useless, because the straight line to it passes + through another ball. An earlier version returned exactly such a slot for + K10 and then could not understand why nothing worked. + + * The blocker is usually a capacitor, not a trace. The back-side decoupling + array sits on a 3 mm grid inside the ball field, and a 0402 pad is 0.64 mm + across against a 0.425 mm clearance requirement -- so a cap centred on a + ball blocks all four of its slots. No router can shove a component. Moving + it 0.3 mm frees two. + + * Below F.Cu there are no ball pads at all. U1's pads are top-layer only, so + once a via reaches In2 the 1.0 mm ball grid stops being an obstacle and + the 0.05 mm corridor problem disappears. Route out on an inner layer. + +Every change is checked by KiCad's DRC and rolled back unless the board +strictly improves. + + python3 scripts/bga_escape.py BOARD --out OUT +""" +from __future__ import annotations + +if __name__ == "__main__": + from pathlib import Path as _NativePath + if (_NativePath(__file__).resolve().parents[1]/"NATIVE_BASELINE.json").exists(): + raise SystemExit('Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.') + + +import argparse, heapq, json, math, os, shutil, subprocess, tempfile +from pathlib import Path +import numpy as np + + +def load_pcbnew(): + import importlib + saved, devnull = os.dup(2), os.open(os.devnull, os.O_WRONLY) + try: + os.dup2(devnull, 2) + return importlib.import_module("pcbnew") + finally: + os.dup2(saved, 2); os.close(saved); os.close(devnull) + + +pcbnew = load_pcbnew() +NM = 1_000_000 + + +def drc(path): + o = tempfile.mktemp(suffix=".json") + subprocess.run(["kicad-cli", "pcb", "drc", "--output", o, "--format", "json", + "--units", "mm", "--severity-error", "--refill-zones", path], + capture_output=True, text=True) + j = json.load(open(o)); os.unlink(o) + return len(j.get("violations", [])), len(j.get("unconnected_items", [])), j + + +def blockers(board, net, sx, sy, need): + """What stops a via at (sx, sy): (movable footprints, other obstructions).""" + fps, other = set(), 0 + for t in board.GetTracks(): + if t.GetNetCode() == net: + continue + if t.Type() == pcbnew.PCB_VIA_T: + p = t.GetPosition(); r = t.GetWidth(pcbnew.F_Cu) / 2 / 1e6 + if math.hypot(p.x/1e6 - sx, p.y/1e6 - sy) < r + need: + other += 1 + else: + a, e = t.GetStart(), t.GetEnd(); r = t.GetWidth() / 2 / 1e6 + x1, y1, x2, y2 = a.x/1e6, a.y/1e6, e.x/1e6, e.y/1e6 + dx, dy = x2-x1, y2-y1; L = dx*dx + dy*dy + tt = 0 if L == 0 else max(0, min(1, ((sx-x1)*dx + (sy-y1)*dy)/L)) + if math.hypot(sx-(x1+tt*dx), sy-(y1+tt*dy)) < r + need: + other += 1 + for fp in board.GetFootprints(): + for pad in fp.Pads(): + if pad.GetNetCode() == net: + continue + p = pad.GetPosition() + r = max(pad.GetSize().x, pad.GetSize().y) / 2 / 1e6 + if math.hypot(p.x/1e6 - sx, p.y/1e6 - sy) < r + need: + # A two-pad passive can be nudged; a BGA or IC cannot. + if fp.GetPadCount() <= 2: + fps.add(fp.GetReference()) + else: + other += 1 + return fps, other + + +def try_nudge(board, fpref, slot, need, limit=0.6, step=0.1): + """Smallest move of a two-pad part that clears `slot`, or None.""" + fp = next((f for f in board.GetFootprints() if f.GetReference() == fpref), None) + if fp is None: + return None + orig = fp.GetPosition() + best = None + n = int(limit / step) + for i in range(-n, n + 1): + for j in range(-n, n + 1): + if i == 0 and j == 0: + continue + dx, dy = i * step, j * step + if math.hypot(dx, dy) > limit: + continue + ok = True + for pad in fp.Pads(): + p = pad.GetPosition() + r = max(pad.GetSize().x, pad.GetSize().y) / 2 / 1e6 + if math.hypot(p.x/1e6 + dx - slot[0], p.y/1e6 + dy - slot[1]) < r + need: + ok = False; break + if ok: + d = math.hypot(dx, dy) + if best is None or d < best[0]: + best = (d, dx, dy) + return best + + +class Grid: + """Rasterised obstacles for the inner-layer run. No ball pads exist here.""" + + def __init__(self, step, layers, bbox): + self.step, self.layers = step, layers + self.idx = {ly: i for i, ly in enumerate(layers)} + self.x0, self.y0 = bbox[0], bbox[2] + self.w = int((bbox[1] - bbox[0]) / step) + 2 + self.h = int((bbox[3] - bbox[2]) / step) + 2 + + def cell(self, x, y): + return (int((x - self.x0) / self.step), int((y - self.y0) / self.step)) + + def mm(self, cx, cy): + return (self.x0 + cx * self.step, self.y0 + cy * self.step) + + def build(self, board, net, need): + b = np.zeros((len(self.layers), self.h, self.w), dtype=bool) + + def stamp(i, x, y, r): + cx, cy = self.cell(x, y) + rr = max(1, int(math.ceil(r / self.step))) + xl, xh = max(0, cx-rr), min(self.w, cx+rr+1) + yl, yh = max(0, cy-rr), min(self.h, cy+rr+1) + if xl < xh and yl < yh: + b[i, yl:yh, xl:xh] = True + + for t in board.GetTracks(): + if t.GetNetCode() == net: + continue + if t.Type() == pcbnew.PCB_VIA_T: + p = t.GetPosition(); r = t.GetWidth(pcbnew.F_Cu)/2/1e6 + need + for i in range(len(self.layers)): + stamp(i, p.x/1e6, p.y/1e6, r) + else: + if t.GetLayer() not in self.idx: + continue + i = self.idx[t.GetLayer()] + a, e = t.GetStart(), t.GetEnd(); r = t.GetWidth()/2/1e6 + need + n = max(1, int(math.hypot(e.x-a.x, e.y-a.y)/1e6/self.step)) + for k in range(n+1): + stamp(i, (a.x+(e.x-a.x)*k/n)/1e6, (a.y+(e.y-a.y)*k/n)/1e6, r) + for fp in board.GetFootprints(): + for pad in fp.Pads(): + if pad.GetNetCode() == net: + continue + p = pad.GetPosition() + r = max(pad.GetSize().x, pad.GetSize().y)/2/1e6 + need + for i, ly in enumerate(self.layers): + if pad.IsOnLayer(ly): + stamp(i, p.x/1e6, p.y/1e6, r) + return b + + +def astar(b, start, goals, via_cost, shape, via_ok=None): + """A* where a layer change is only allowed where a via can actually go. + + The subtle bug this exists to prevent: a through via spans every copper + layer, so changing layer at (x, y) needs (x, y) clear on *all* of them, not + just the one being moved to. Checking only the destination layer produces + routes that look fine and drop vias into other nets -- it put one 0.107 mm + from a V1 ball and shorted another to V3V3. + """ + nl, h, w = shape + gx = sum(g[1] for g in goals)/len(goals); gy = sum(g[2] for g in goals)/len(goals) + hf = lambda x, y: int(10*max(abs(x-gx), abs(y-gy)) + 4*min(abs(x-gx), abs(y-gy))) + INF = 1 << 30 + dist = {start: 0}; prev = {}; pq = [(hf(start[1], start[2]), 0, start)] + steps = [(dx, dy, 10 if not (dx and dy) else 14) + for dx in (-1, 0, 1) for dy in (-1, 0, 1) if dx or dy] + while pq: + _, d, cur = heapq.heappop(pq) + if d > dist.get(cur, INF): + continue + if cur in goals: + path = [cur] + while path[-1] in prev: + path.append(prev[path[-1]]) + return list(reversed(path)) + li, x, y = cur + for dx, dy, c in steps: + nx, ny = x+dx, y+dy + if not (0 <= nx < w and 0 <= ny < h) or b[li, ny, nx]: + continue + nd = d+c; nxt = (li, nx, ny) + if nd < dist.get(nxt, INF): + dist[nxt], prev[nxt] = nd, cur + heapq.heappush(pq, (nd+hf(nx, ny), nd, nxt)) + if via_ok is not None and not via_ok[y, x]: + continue + for nli in range(nl): + if nli == li or b[nli, y, x]: + continue + nd = d+via_cost; nxt = (nli, x, y) + if nd < dist.get(nxt, INF): + dist[nxt], prev[nxt] = nd, cur + heapq.heappush(pq, (nd+hf(x, y), nd, nxt)) + return None + + +def emit(board, g, path, net, width_nm, via_d, via_drill): + runs, cur = [], [path[0]] + for n in path[1:]: + if n[0] == cur[-1][0]: + cur.append(n) + else: + runs.append(cur); cur = [n] + runs.append(cur) + length = 0.0 + for run in runs: + pts = [run[0]] + for i in range(1, len(run)-1): + if (run[i][1]-run[i-1][1], run[i][2]-run[i-1][2]) != \ + (run[i+1][1]-run[i][1], run[i+1][2]-run[i][2]): + pts.append(run[i]) + if len(run) > 1: + pts.append(run[-1]) + for a, c in zip(pts, pts[1:]): + ax, ay = g.mm(a[1], a[2]); cx, cy = g.mm(c[1], c[2]) + t = pcbnew.PCB_TRACK(board) + t.SetStart(pcbnew.VECTOR2I(int(ax*NM), int(ay*NM))) + t.SetEnd(pcbnew.VECTOR2I(int(cx*NM), int(cy*NM))) + t.SetWidth(width_nm); t.SetLayer(g.layers[run[0][0]]) + t.SetNetCode(net); board.Add(t) + length += math.hypot(cx-ax, cy-ay) + for a, c in zip(runs, runs[1:]): + vx, vy = g.mm(a[-1][1], a[-1][2]) + v = pcbnew.PCB_VIA(board) + v.SetPosition(pcbnew.VECTOR2I(int(vx*NM), int(vy*NM))) + v.SetWidth(via_d); v.SetDrill(via_drill); v.SetNetCode(net) + v.SetViaType(pcbnew.VIATYPE_THROUGH); board.Add(v) + return length + + +def main(): + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("board"); ap.add_argument("--out", required=True) + ap.add_argument("--grid", type=float, default=0.1) + ap.add_argument("--clearance", type=float, default=0.16) + ap.add_argument("--width", type=float, default=0.15) + ap.add_argument("--via", type=float, default=0.55) + ap.add_argument("--drill", type=float, default=0.25) + ap.add_argument("--via-cost", type=int, default=300) + ap.add_argument("--margin", type=float, default=8.0) + ap.add_argument("--detour", type=float, default=3.0) + a = ap.parse_args() + + work = Path(a.out); shutil.copy(a.board, work) + pro = Path(a.board).with_suffix(".kicad_pro") + if pro.is_file(): + shutil.copy(pro, work.with_suffix(".kicad_pro")) + v0, u0, _ = drc(str(work)) + print(f" start {v0} violation(s), {u0} unconnected") + need = a.via/2 + a.clearance + moved, kept, failed = [], 0, 0 + + while True: + v_now, u_now, data = drc(str(work)) + progressed = False + for e in data.get("unconnected_items", []): + items = e.get("items", []) + if len(items) != 2: + continue + board = pcbnew.LoadBoard(str(work)) + idx = {t.m_Uuid.AsString(): t for t in board.GetTracks()} + for fp in board.GetFootprints(): + for pad in fp.Pads(): + idx[pad.m_Uuid.AsString()] = pad + ia, ib = idx.get(items[0]["uuid"]), idx.get(items[1]["uuid"]) + if ia is None or ib is None: + continue + if ib.Type() == pcbnew.PCB_PAD_T and ia.Type() != pcbnew.PCB_PAD_T: + ia, ib = ib, ia; items = [items[1], items[0]] + if ia.Type() != pcbnew.PCB_PAD_T: + continue + net, name = ia.GetNetCode(), ia.GetNetname() + ball = (items[0]["pos"]["x"], items[0]["pos"]["y"]) + dest = (items[1]["pos"]["x"], items[1]["pos"]["y"]) + direct = math.hypot(ball[0]-dest[0], ball[1]-dest[1]) + + # Only the four adjacent diagonal slots are reachable from a ball. + cands = [(ball[0]+dx, ball[1]+dy) + for dx in (-0.5, 0.5) for dy in (-0.5, 0.5)] + slot = nudge = None + for sx, sy in cands: + fps, other = blockers(board, net, sx, sy, need) + if other == 0 and not fps: + slot = (sx, sy); break + if slot is None: + for sx, sy in cands: + fps, other = blockers(board, net, sx, sy, need) + if other == 0 and len(fps) == 1: + ref = next(iter(fps)) + nd = try_nudge(board, ref, (sx, sy), need) + if nd: + slot, nudge = (sx, sy), (ref, nd[1], nd[2]); break + if slot is None: + failed += 1 + continue + + if nudge: + ref, dx, dy = nudge + fp = next(f for f in board.GetFootprints() if f.GetReference() == ref) + p = fp.GetPosition() + fp.SetPosition(pcbnew.VECTOR2I(int(p.x + dx*NM), int(p.y + dy*NM))) + + planes = {ly for z in board.Zones() + if z.GetNetname() in ("GND", "AGND", "DGND") + for ly in z.GetLayerSet().CuStack()} + own = {ly for z in board.Zones() if z.GetNetCode() == net + for ly in z.GetLayerSet().CuStack()} + layers = [ly for ly in board.GetEnabledLayers().CuStack() + if ly not in planes or ly in own] + xs = [ball[0], dest[0], slot[0]]; ys = [ball[1], dest[1], slot[1]] + bbox = (min(xs)-a.margin, max(xs)+a.margin, min(ys)-a.margin, max(ys)+a.margin) + g = Grid(a.grid, layers, bbox) + b = g.build(board, net, a.clearance + a.width/2) + start = (0,) + g.cell(*slot) + dl = ib.GetLayer() if ib.Type() == pcbnew.PCB_TRACE_T else pcbnew.F_Cu + if dl not in g.idx: + dl = pcbnew.F_Cu + # Aim at the whole destination item, not the one point DRC named. + # A trace can be joined anywhere along its length, and the reported + # endpoint is often walled in by the copper around it -- which looks + # exactly like "no route exists" when the trace is wide open 2 mm + # further along. + goals = set() + if ib.Type() == pcbnew.PCB_TRACE_T and ib.GetLayer() in g.idx: + gi = g.idx[ib.GetLayer()] + sa, se = ib.GetStart(), ib.GetEnd() + n = max(1, int(math.hypot(se.x-sa.x, se.y-sa.y)/1e6/g.step)) + for k in range(n+1): + goals.add((gi,) + g.cell((sa.x+(se.x-sa.x)*k/n)/1e6, + (sa.y+(se.y-sa.y)*k/n)/1e6)) + elif ib.Type() == pcbnew.PCB_VIA_T: + c = g.cell(ib.GetPosition().x/1e6, ib.GetPosition().y/1e6) + goals = {(i,) + c for i in range(len(layers))} + else: + goals = {(g.idx[dl],) + g.cell(*dest)} + goals = {gg for gg in goals + if 0 <= gg[1] < g.w and 0 <= gg[2] < g.h} + if not goals: + failed += 1 + continue + b[start[0], start[2], start[1]] = False + for gg in goals: + b[gg[0], gg[2], gg[1]] = False + via_ok = ~b.any(axis=0) + # The escape via sits at `start` by construction, and the goal is + # copper we are joining -- both are legal transition points even + # though the surrounding layers read as occupied. + via_ok[start[2], start[1]] = True + for gg in goals: + via_ok[gg[2], gg[1]] = True + path = astar(b, start, goals, a.via_cost, (len(layers), g.h, g.w), via_ok) + if path is None: + failed += 1 + continue + + v = pcbnew.PCB_VIA(board) + v.SetPosition(pcbnew.VECTOR2I(int(slot[0]*NM), int(slot[1]*NM))) + v.SetWidth(int(a.via*NM)); v.SetDrill(int(a.drill*NM)) + v.SetNetCode(net); v.SetViaType(pcbnew.VIATYPE_THROUGH); board.Add(v) + t = pcbnew.PCB_TRACK(board) + t.SetStart(pcbnew.VECTOR2I(int(ball[0]*NM), int(ball[1]*NM))) + t.SetEnd(pcbnew.VECTOR2I(int(slot[0]*NM), int(slot[1]*NM))) + t.SetWidth(int(a.width*NM)); t.SetLayer(pcbnew.F_Cu) + t.SetNetCode(net); board.Add(t) + length = emit(board, g, path, net, int(a.width*NM), + int(a.via*NM), int(a.drill*NM)) + if length > a.detour * max(direct, 1.0): + failed += 1 + continue + + pcbnew.ZONE_FILLER(board).Fill(board.Zones()); board.BuildConnectivity() + trial = tempfile.mktemp(suffix=".kicad_pcb") + if pro.is_file(): + shutil.copy(pro, Path(trial).with_suffix(".kicad_pro")) + pcbnew.SaveBoard(trial, board) + v1, u1, _ = drc(trial) + if v1 <= v_now and u1 < u_now: + shutil.move(trial, str(work)) + note = f", moved {nudge[0]} by ({nudge[1]:+.1f},{nudge[2]:+.1f}) mm" if nudge else "" + if nudge: + moved.append((nudge[0], nudge[1], nudge[2])) + print(f" ROUTED {name:14s} {length:5.1f} mm via ({slot[0]:.2f},{slot[1]:.2f})" + f"{note} -> {v1} viol, {u1} unconnected") + kept += 1; progressed = True + break + os.unlink(trial); failed += 1 + if not progressed: + break + + vf, uf, _ = drc(str(work)) + print(f"\n result {kept} routed, {failed} not") + print(f" {v0} -> {vf} violation(s), {u0} -> {uf} unconnected") + if moved: + print(" moved " + "; ".join(f"{r} by ({x:+.1f},{y:+.1f}) mm" for r, x, y in moved)) + print(" mirror these into design.ts") + print(f" wrote {work}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/bom.py b/hardware/courant/scripts/bom.py new file mode 100644 index 0000000..faf257f --- /dev/null +++ b/hardware/courant/scripts/bom.py @@ -0,0 +1,196 @@ +#!/usr/bin/env python3 +""" +Write the BOM with manufacturer part numbers, straight from the routed board. + +scripts/fab.py already emits a BOM, but it groups by value and footprint and +stops there, which is enough to check a board against itself and not enough to +order one. This adds the part numbers. + +Where the schematic value *is* the part number -- every IC, the regulators, the +oscillators, the diodes -- it is used directly and the LCSC code is given where +it was verified against stock. Where the value is a specification rather than a +part, as it is for every resistor and capacitor, no manufacturer is invented. +Those lines carry the requirement instead: value, package, and the rating that +actually constrains the choice. An assembler fills them from their own basic +library, and a made-up part number would only look authoritative while being +no more specific than the requirement it replaced. + +Two exceptions are called out because the choice is engineering, not stock +keeping: the 0201 decoupling array is an extended-library part that carries a +setup fee, and the switcher inductor has to survive the regulator's current. + + python3 scripts/bom.py BOARD --out OUT.csv +""" +from __future__ import annotations + +import argparse, csv, os, re, sys +from collections import defaultdict +from pathlib import Path + +sys.path.insert(0, str(Path(__file__).resolve().parent)) +from plane_escape import pcbnew + +# value -> (manufacturer, MPN, LCSC, note). The value is already the MPN. +PARTS = { + "XC7A50T-1FTG256I": ("AMD/Xilinx", "XC7A50T-1FTG256I", "C3272410", + "FPGA, 52160 logic cells, industrial temp"), + "TPS62130ARGTR": ("Texas Instruments", "TPS62130ARGTR", "", + "3 A buck, QFN-16 with exposed pad"), + "W25Q64JVSSIQ": ("Winbond", "W25Q64JVSSIQ", "", "64 Mbit SPI flash"), + "MCP3208-CI/SL": ("Microchip", "MCP3208-CI/SL", "", "8-ch 12-bit SPI ADC"), + "PCM5102APWR": ("Texas Instruments", "PCM5102APWR", "", "stereo audio DAC"), + "MCP6002-I/SN": ("Microchip", "MCP6002-I/SN", "", "dual op-amp, CV buffer"), + "MCP6561T-E/OT": ("Microchip", "MCP6561T-E/OT", "", "comparator, gate input"), + "REF3125AIDBZR": ("Texas Instruments", "REF3125AIDBZR", "", "2.5 V reference"), + "H11L1M": ("onsemi", "H11L1M", "", "Schmitt optocoupler, MIDI input"), + "IPT1-110-06-L-D": ("Samtec", "IPT1-110-06-L-D", "", + "2x10 2.54 mm vertical through-hole terminal strip; mates IPS1-110-01-L-D. Fully-mated PCB gap 19.99 mm; 20.45 mm max."), + "BAT54S": ("", "BAT54S", "", "dual Schottky, CV input clamp"), + "1N4148W": ("", "1N4148W", "", "signal diode"), + "ASE-100.000MHZ-LC-T": ("Abracon", "ASE-100.000MHZ-LC-T", "", + "100 MHz system oscillator"), + "ASE-12.288MHZ-LC-T": ("Abracon", "ASE-12.288MHZ-LC-T", "", + "12.288 MHz audio master clock"), + "1µH": ("cjiang", "FNR4030S1R0MT", "C167865", + "4x4 mm shielded, 18 mOhm, 5.7 A sat -- must exceed the " + "TPS62130's 3 A plus ripple"), +} + +# Passives, by (value, footprint). Every one of these was checked against +# live stock; nothing here is a plausible-looking part number that was never +# confirmed to exist. Where a family covers several values -- the Murata C0G +# run, the Yageo RC0603FR series -- one member was verified and the rest follow +# the manufacturer's own value coding, which is noted on the line. +PASSIVE = { + ("100nF","capacitor_cap0201"): ("CCTC","TCC0201X5R104K100ZT","C5142565", + "10 V X5R. JLC extended library: one setup fee for the whole array"), + ("100nF","capacitor_cap0603"): ("Samsung","CL10B104KB8NNNC","C1591","50 V X7R"), + ("10nF","capacitor_cap0603"): ("Murata","GRM1885C1H103JA01D","C85973", + "50 V C0G -- ADC anti-alias, C0G for low voltage coefficient"), + ("1nF","capacitor_cap0603"): ("Murata","GRM1885C1H102JA01D","", + "50 V C0G, same series as the 10 nF"), + ("2.2nF","capacitor_cap0603"): ("Murata","GRM1885C1H222JA01D","", + "50 V C0G, same series"), + ("3.3nF","capacitor_cap0603"): ("Murata","GRM1885C1H332JA01D","", + "50 V C0G -- switcher soft-start"), + ("1uF","capacitor_cap0603"): ("Samsung","CL10B105KB8NQNC","C5199872","50 V X7R"), + ("2.2uF","capacitor_cap0603"): ("Samsung","CL10A225KO8NNNC","C23630", + "16 V X5R, JLC basic library"), + ("4.7uF","capacitor_cap0805"): ("Yageo","CC0805KKX7R8BB475","C354262","25 V X7R"), + ("10uF","capacitor_cap0805"): ("Samsung","CL21A106KAYNNNE","C15850", + "25 V X5R, JLC basic library"), + ("22uF","capacitor_cap0805"): ("Samsung","CL21A226MAQNNNE","C45783", + "25 V X5R, JLC basic library -- switcher output"), + ("47uF","capacitor_cap1210"): ("Murata","GRM32ER61C476KE15L","C77101", + "16 V X5R -- bulk input"), +} + +# Yageo RC0603FR-07L, thick film 1%. RC0603FR-0710KL was confirmed in +# stock (C98220) and the rest follow Yageo's coding: R marks the decimal in +# sub-kilohm values, K in kilohms. +RES_CODE = { + "1Ω":"1R", "33Ω":"33R", "100Ω":"100R", "220Ω":"220R", "470Ω":"470R", + "1kΩ":"1K", "2.2kΩ":"2K2", "4.7kΩ":"4K7", "10kΩ":"10K", "24.9kΩ":"24K9", + "33kΩ":"33K", "40.2kΩ":"40K2", "100kΩ":"100K", "124kΩ":"124K", "316kΩ":"316K", +} +RES_LCSC = {"10kΩ":"C98220", "24.9kΩ":"C137761"} + +# The CV dividers are matched pairs, so they get thin film at 0.1% and +# 25 ppm/C rather than a tighter grade of the same thick film part: the +# tempco is what actually limits how well the two track each other. +# Molex KK 254: a latching, polarised 2.54 mm system, which is what a harness +# wants -- a plain pin header and a friction-fit socket comes loose and can be +# refitted one pin out. The board's 1.00 mm drills take the 0.64 mm square +# posts (0.90 mm across the diagonal). 22-23-2031 and 22-01-3037 were checked +# against stock; the others follow Molex's own circuit-count coding. +KK254 = {2: ("22-23-2021", "22-01-3027"), 3: ("22-23-2031", "22-01-3037"), + 5: ("22-23-2051", "22-01-3057"), 6: ("22-23-2061", "22-01-3067")} +KK254_TERMINAL = "08-55-0102" # 22-30 AWG, selective gold. NOT 08-50-0114, + # which is the obvious pick and is End of Life. + +PRECISION = { + "20kΩ": ("Yageo","RT0603BRD0720KL","C723637", + "0.1%, 25 ppm/C thin film -- matched CV divider pair"), +} + +SKIP_FP = ("hole_circle", "smtpad_circle", "Unknown") + + +def main(): + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("board"); ap.add_argument("--out", required=True) + a = ap.parse_args() + + board = pcbnew.LoadBoard(a.board) + groups = defaultdict(list) + for fp in board.GetFootprints(): + name = fp.GetFPIDAsString().split(":")[-1] + if any(name.startswith(s) for s in SKIP_FP) or not fp.GetValue(): + continue + side = "bottom" if fp.IsFlipped() else "top" + groups[(fp.GetValue(), name, side)].append(fp.GetReference()) + + def sort_key(r): + m = re.match(r"([A-Za-z]+)(\d+)", r) + return (m.group(1), int(m.group(2))) if m else (r, 0) + + rows = [] + for (value, fpname, side), refs in groups.items(): + refs.sort(key=sort_key) + # tscircuit/KiCad export appends a stable __ suffix to generated + # footprint names. Component selection is by the physical package family, + # not by that instance-library hash. + family = re.sub(r"__[0-9a-fA-F]{10}(?:::\d+)?$", "", fpname) + mfr = mpn = lcsc = note = "" + if value in PARTS: + mfr, mpn, lcsc, note = PARTS[value] + elif fpname == "Stack_2x10_P2.54": + # Fallback only for a stale native board. Current source sets the exact + # Samtec IPT1 MPN as the footprint value, so the PARTS table above wins. + mfr, mpn = "Samtec", "IPT1-110-06-L-D" + note = ("2x10 2.54 mm direct board-to-board terminal strip; mate with " + "IPS1-110-01-L-D on the panel. Fully-mated PCB gap 19.99 mm.") + value = "IPT1-110-06-L-D" + elif fpname.startswith("pinrow") or refs[0].startswith("J"): + n = len(list(board.FindFootprintByReference(refs[0]).Pads())) + hdr, hsg = KK254[n] + mfr, mpn = "Molex", hdr + note = (f"KK 254 vertical friction-lock. Harness side: housing " + f"{hsg} + {n} x {KK254_TERMINAL} crimp terminals") + value = f"1x{n:02d} header, 2.54 mm" + elif value in PRECISION: + mfr, mpn, lcsc, note = PRECISION[value] + elif (value, family) in PASSIVE: + mfr, mpn, lcsc, note = PASSIVE[(value, family)] + elif value in RES_CODE: + mfr, mpn = "Yageo", f"RC0603FR-07{RES_CODE[value]}L" + lcsc = RES_LCSC.get(value, "") + note = "thick film 1%" + else: + mpn = "UNRESOLVED" + note = "no part number assigned -- do not order without one" + rows.append({ + "Reference(s)": ",".join(refs), "Qty": len(refs), "Value": value, + "Footprint": fpname, "Side": side, "Manufacturer": mfr, + "MPN": mpn, "LCSC": lcsc, "Notes": note, + }) + rows.sort(key=lambda r: (-r["Qty"], r["Value"])) + + with open(a.out, "w", newline="") as f: + w = csv.DictWriter(f, fieldnames=list(rows[0].keys())) + w.writeheader(); w.writerows(rows) + named = sum(r["Qty"] for r in rows if r["MPN"] not in ("UNRESOLVED", "")) + total = sum(r["Qty"] for r in rows) + print(f" {len(rows)} line items, {total} placements") + gap = [r for r in rows if r["MPN"] == "UNRESOLVED"] + print(f" {named} of {total} placements have a manufacturer part number") + if gap: + print(" UNRESOLVED: " + ", ".join(f"{r['Value']} ({r['Footprint']})" + for r in gap)) + print(f" wrote {a.out}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/check.ts b/hardware/courant/scripts/check.ts new file mode 100644 index 0000000..fc24243 --- /dev/null +++ b/hardware/courant/scripts/check.ts @@ -0,0 +1,132 @@ +/** + * Board-specific electrical rule checks. + * + * These are the rules tscircuit cannot know: they are about the XC7A35T's + * package, its configuration straps, and this board's rail topology. + * Generic connectivity/DRC belongs to `tsci check netlist` and `tsci build`, + * which the `verify` script runs alongside this. + */ +import pins from "../fpga-pins.json" +import { parts, nets, io, fpgaNets, thermalVias } from "../design" + +const byBall = Object.fromEntries(pins.map((p) => [p.ball, p])) +const fails: string[] = [] +const warns: string[] = [] +const fail = (m: string) => fails.push(m) +const warn = (m: string) => warns.push(m) + +// ---------------------------------------------------------------- netlist --- +const pinsOfNet: Record = {} +for (const p of parts) + for (const [pin, net] of Object.entries(p.nets)) (pinsOfNet[net] ??= []).push(`${p.name}.${pin}`) + +for (const [net, conns] of Object.entries(pinsOfNet)) + if (conns.length < 2) fail(`net ${net} has a single connection (${conns[0]}); it drives nothing`) + +// Net names must stay distinct when case is ignored. tscircuit and KiCad treat +// `led0` and `LED0` as two nets; Specctra does not, so a DSN handoff silently +// merges them and the router shorts whatever sits between. This cost the four +// LED series resistors once already. +const byFold: Record = {} +for (const net of nets) (byFold[net.toLowerCase()] ??= []).push(net) +for (const [fold, group] of Object.entries(byFold)) + if (group.length > 1) + fail(`nets ${group.join(" and ")} differ only by case; Specctra folds them to "${fold}" and the router will short them together`) + +const refdes = parts.map((p) => p.name) +for (const name of new Set(refdes)) + if (refdes.filter((n) => n === name).length > 1) fail(`duplicate reference designator ${name}`) + +// ------------------------------------------------------------------- FPGA --- +// Every ball the design assigns must exist in AMD's package file, and no user +// signal may land on a dedicated configuration or supply ball. +for (const [ball, net] of Object.entries(fpgaNets)) { + const p = byBall[ball] + if (!p) { fail(`U1 ball ${ball} is not in the ftg256 package`); continue } + if (io[ball] && !p.function.startsWith("IO_")) + fail(`U1 ball ${ball} carries user signal ${net} but is a ${p.function} pin`) +} + +// Bank voltage: every user I/O sits in a bank whose VCCO this board ties to 3.3 V. +const bankOfIo = new Set(Object.keys(io).map((b) => byBall[b]?.bank)) +for (const bank of bankOfIo) { + const vcco = pins.filter((p) => p.function === `VCCO_${bank}`) + if (!vcco.length) { fail(`bank ${bank} is used but has no VCCO pin in the package`); continue } + for (const p of vcco) + if (fpgaNets[p.ball] !== "V3V3") + fail(`bank ${bank} carries 3.3 V LVCMOS I/O but ${p.ball} (${p.function}) is on ${fpgaNets[p.ball] ?? "no net"}`) +} + +// Clock *inputs* must land on clock-capable balls or they cannot drive the +// MMCM directly. The dac_*/adc_sclk clocks are FPGA outputs and may sit on any +// user I/O, so only the two oscillator inputs are checked here. +const clockInputs = ["clk100", "audio_mclk_in"] +for (const net of clockInputs) { + const ball = Object.keys(io).find((b) => io[b] === net) + if (!ball) { fail(`clock input ${net} is not assigned to a ball`); continue } + if (!/[MS]RCC/.test(byBall[ball]?.function ?? "")) + fail(`clock input ${net} is on ${ball} (${byBall[ball]?.function}), which is not clock-capable`) +} + +// Configuration straps, per UG470. M[2:0]=001 selects master SPI. +const strap: Record = { M9: "V3V3", M10: "GND", M11: "GND" } +for (const [ball, want] of Object.entries(strap)) + if (fpgaNets[ball] !== want) + fail(`mode pin ${ball} (${byBall[ball]?.function}) is ${fpgaNets[ball] ?? "floating"}, expected ${want} for master SPI`) +if (fpgaNets.E7 !== "V3V3") fail("CFGBVS (E7) must be tied to V3V3 for a 3.3 V config bank") +if (fpgaNets.G8 !== "V1V8") fail("VCCADC (G8) must be on the 1.8 V rail") +for (const ball of ["J8", "H7"]) + if (fpgaNets[ball] !== "GND") + fail(`${byBall[ball]?.function} (${ball}) must be grounded when the XADC is unused`) + +// Supplies: no power ball may be left unconnected. +for (const p of pins) { + const isSupply = p.function === "GND" || p.function.startsWith("VCC") + if (isSupply && !fpgaNets[p.ball] && p.function !== "VCCBATT_0") + fail(`U1 supply ball ${p.ball} (${p.function}) is not connected`) +} + +// ------------------------------------------------------------------ rails --- +// Each rail needs local bulk plus high-frequency decoupling. +const decoupling: Record = {} +for (const p of parts) + if (p.kind === "capacitor") + for (const net of Object.values(p.nets)) if (net !== "GND") decoupling[net] = (decoupling[net] ?? 0) + 1 +for (const rail of ["V1", "V1V8", "V3V3"]) { + const n = decoupling[rail] ?? 0 + // One per powered ball is the usual floor for a BGA of this size. + const balls = Object.entries(fpgaNets).filter(([, net]) => net === rail).length + if (n < balls) warn(`rail ${rail} has ${n} capacitors for ${balls} powered balls`) +} + +// Every net named like a rail must actually be produced by a regulator. +for (const rail of ["V1", "V1V8", "V3V3"]) + if (!parts.some((p) => p.value.startsWith("TPS62130") && Object.values(p.nets).includes(rail))) + fail(`rail ${rail} has no regulator output`) + +// Thermal vias must land inside the exposed pad they are cooling, and must not +// touch each other's barrels. Both are geometry the netlist cannot express and +// the router will not police: the vias are placed by hand in the board file, +// and a regulator that moves without them moving leaves four holes in open +// copper. +const EXPOSED_PAD = 1.68 // TPS62130A RGT0016C, SLVSAG7F section 12 +const VIA_OD = 0.6 +for (const v of thermalVias) { + const host = parts.find((p) => p.value.startsWith("TPS62130") + && Math.abs(p.x - v.x) <= EXPOSED_PAD / 2 && Math.abs(p.y - v.y) <= EXPOSED_PAD / 2) + if (!host) { fail(`thermal via ${v.name} is not inside any TPS62130A exposed pad`); continue } + const reach = Math.max(Math.abs(v.x - host.x), Math.abs(v.y - host.y)) + VIA_OD / 2 + if (reach > EXPOSED_PAD / 2) + fail(`thermal via ${v.name} overhangs ${host.name}'s exposed pad by ${(reach - EXPOSED_PAD / 2).toFixed(3)} mm`) +} +for (const [i, a] of thermalVias.entries()) + for (const b of thermalVias.slice(i + 1)) + if (Math.hypot(a.x - b.x, a.y - b.y) < VIA_OD) + fail(`thermal vias ${a.name} and ${b.name} overlap`) + +// ----------------------------------------------------------------- report --- +console.log(`${parts.length} parts, ${nets.length} nets, ${Object.keys(fpgaNets).length} FPGA balls assigned`) +for (const w of warns) console.log(` warn ${w}`) +for (const f of fails) console.log(` FAIL ${f}`) +console.log(fails.length ? `\n${fails.length} check(s) failed` : `\nall checks passed${warns.length ? ` (${warns.length} warning(s))` : ""}`) +process.exit(fails.length ? 1 : 0) diff --git a/hardware/courant/scripts/close.py b/hardware/courant/scripts/close.py new file mode 100644 index 0000000..1434818 --- /dev/null +++ b/hardware/courant/scripts/close.py @@ -0,0 +1,624 @@ +#!/usr/bin/env python3 +""" +Close the remaining connections with a real path search. + +Everything else in scripts/ places copper along a shape decided in advance -- +a straight line, an L, a 45 degree mitre. That is why they all failed on the +same handful of connections: what those need is a path that turns more than +twice, or that leaves a ball by one slot and arrives at another by a different +one. No amount of varying the search radius fixes a router that can only draw +three shapes. + +This rasterises the board into a grid and searches it properly. + +Two modes, because the two kinds of connection left are not the same problem: + + * A net with a plane -- GND on In1/In4, V3V3 on In3 -- does not need to reach + the other endpoint at all. It needs to reach any point where a via is + legal, because the via lands on the plane and the plane is the connection. + Searching to the named endpoint, which is what every earlier attempt did, + solves a harder problem than the board actually poses. + + * A net without one -- V1, V1V8, and the signals -- needs a genuine path + between two points, free to change layer wherever a via fits. + +Never routes on In1.Cu or In4.Cu: they are the ground planes, and a signal +crossing one cuts the return path under everything nearby. + + python3 scripts/close.py BOARD --out OUT [--step MM] [--net NET] +""" +from __future__ import annotations + +if __name__ == "__main__": + from pathlib import Path as _NativePath + if (_NativePath(__file__).resolve().parents[1]/"NATIVE_BASELINE.json").exists(): + raise SystemExit('Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.') + + +import argparse, heapq, math, os, re, shutil, sys, tempfile +from pathlib import Path + +import numpy as np + +sys.path.insert(0, str(Path(__file__).resolve().parent)) +from plane_escape import pcbnew, NM, drc, seg_dist as pe_seg_dist + +PLANE_NETS = {"GND", "V3V3"} +PLANES = {"In1.Cu", "In4.Cu", "In3.Cu"} + + +class Window: + """A rasterised patch of board, one bit-plane per routable copper layer.""" + + def __init__(self, x0, y0, x1, y1, step, layers): + self.step = step + self.x0, self.y0 = x0, y0 + self.nx = int((x1 - x0) / step) + 1 + self.ny = int((y1 - y0) / step) + 1 + self.layers = layers + self.xs = x0 + np.arange(self.nx) * step + self.ys = y0 + np.arange(self.ny) * step + + def cell(self, x, y): + return (int(round((y - self.y0) / self.step)), + int(round((x - self.x0) / self.step))) + + def mm(self, r, c): + return (self.x0 + c * self.step, self.y0 + r * self.step) + + def inside(self, r, c): + return 0 <= r < self.ny and 0 <= c < self.nx + + def _box(self, lo_x, lo_y, hi_x, hi_y): + c0 = max(0, int((lo_x - self.x0) / self.step)) + c1 = min(self.nx - 1, int((hi_x - self.x0) / self.step) + 1) + r0 = max(0, int((lo_y - self.y0) / self.step)) + r1 = min(self.ny - 1, int((hi_y - self.y0) / self.step) + 1) + return r0, r1, c0, c1 + + def disc(self, grid, x, y, r): + r0, r1, c0, c1 = self._box(x - r, y - r, x + r, y + r) + if r1 < r0 or c1 < c0: + return + dx = self.xs[c0:c1 + 1][None, :] - x + dy = self.ys[r0:r1 + 1][:, None] - y + grid[r0:r1 + 1, c0:c1 + 1] |= (dx * dx + dy * dy) <= r * r + + def segment(self, grid, ax, ay, bx, by, r): + r0, r1, c0, c1 = self._box(min(ax, bx) - r, min(ay, by) - r, + max(ax, bx) + r, max(ay, by) + r) + if r1 < r0 or c1 < c0: + return + X = self.xs[c0:c1 + 1][None, :] + Y = self.ys[r0:r1 + 1][:, None] + dx, dy = bx - ax, by - ay + L2 = dx * dx + dy * dy + if L2 < 1e-12: + d2 = (X - ax) ** 2 + (Y - ay) ** 2 + else: + t = np.clip(((X - ax) * dx + (Y - ay) * dy) / L2, 0.0, 1.0) + d2 = (X - (ax + t * dx)) ** 2 + (Y - (ay + t * dy)) ** 2 + grid[r0:r1 + 1, c0:c1 + 1] |= d2 <= r * r + + def rect(self, grid, x, y, hw, hh, deg, r): + reach = math.hypot(hw, hh) + r + r0, r1, c0, c1 = self._box(x - reach, y - reach, x + reach, y + reach) + if r1 < r0 or c1 < c0: + return + a = math.radians(deg) + ca, sa = math.cos(a), math.sin(a) + X = self.xs[c0:c1 + 1][None, :] - x + Y = self.ys[r0:r1 + 1][:, None] - y + u = np.abs(X * ca + Y * sa) - hw + v = np.abs(-X * sa + Y * ca) - hh + u = np.maximum(u, 0.0); v = np.maximum(v, 0.0) + grid[r0:r1 + 1, c0:c1 + 1] |= (u * u + v * v) <= r * r + + +def obstacles(board, win, netcode, clearance, trace_half, via_r): + """Bit-planes of where this net's copper may not go. + + Two different questions, so two different answers: a trace centre only has + to clear what is on its own layer (plus every through via), while a via + barrel has to clear everything on every layer at once. Conflating them is + how an earlier attempt here dropped a via 0.107 mm from a ball on a layer + it had not looked at. + """ + blocked = {li: np.zeros((win.ny, win.nx), bool) for li in range(len(win.layers))} + via_no = np.zeros((win.ny, win.nx), bool) + index = {l: i for i, l in enumerate(win.layers)} + + def paint(kind, args, layers, extent): + for l in layers: + i = index.get(l) + if i is None: + continue + getattr(win, kind)(blocked[i], *args, extent + clearance + trace_half) + getattr(win, kind)(via_no, *args, extent + clearance + via_r) + + for t in board.GetTracks(): + if t.GetNetCode() == netcode: + continue + if isinstance(t, pcbnew.PCB_VIA): + p = t.GetPosition() + paint("disc", (p.x / NM, p.y / NM), win.layers, + t.GetWidth(pcbnew.F_Cu) / 2 / NM) + else: + a, b = t.GetStart(), t.GetEnd() + paint("segment", (a.x / NM, a.y / NM, b.x / NM, b.y / NM), + [t.GetLayer()], t.GetWidth() / 2 / NM) + + for fp in board.GetFootprints(): + for pad in fp.Pads(): + if pad.GetNetCode() == netcode: + continue + on = [l for l in win.layers if pad.IsOnLayer(l)] + if not on: + continue + p, sz = pad.GetPosition(), pad.GetSize() + hw, hh = sz.x / 2 / NM, sz.y / 2 / NM + if pad.GetShape() == pcbnew.PAD_SHAPE_CIRCLE or abs(hw - hh) < 1e-9: + paint("disc", (p.x / NM, p.y / NM), on, max(hw, hh)) + else: + paint("rect", (p.x / NM, p.y / NM, hw, hh, + pad.GetOrientationDegrees()), on, 0.0) + return blocked, via_no + + +STEPS = [(-1, 0, 1.0), (1, 0, 1.0), (0, -1, 1.0), (0, 1, 1.0), + (-1, -1, 1.4142), (-1, 1, 1.4142), (1, -1, 1.4142), (1, 1, 1.4142)] + + +def search(win, blocked, via_ok, starts, goals, via_cost): + """A* over (layer, row, col); a layer change costs a via and needs one legal.""" + goal = set(goals) + gr, gc = next(iter(goal))[1], next(iter(goal))[2] + best = {} + heap = [] + for s in starts: + best[s] = 0.0 + heapq.heappush(heap, (0.0, 0.0, s, None)) + came = {} + while heap: + _, g, cur, prev = heapq.heappop(heap) + if cur in came: + continue + came[cur] = prev + if cur in goal: + path = [] + while cur is not None: + path.append(cur); cur = came[cur] + return path[::-1] + li, r, c = cur + for dr, dc, w in STEPS: + nr, nc = r + dr, c + dc + if not win.inside(nr, nc) or blocked[li][nr, nc]: + continue + nxt = (li, nr, nc) + ng = g + w * win.step + if ng < best.get(nxt, 1e18): + best[nxt] = ng + h = math.hypot(nr - gr, nc - gc) * win.step + heapq.heappush(heap, (ng + h, ng, nxt, cur)) + if via_ok[r, c]: + for lj in range(len(win.layers)): + if lj == li or blocked[lj][r, c]: + continue + nxt = (lj, r, c) + ng = g + via_cost + if ng < best.get(nxt, 1e18): + best[nxt] = ng + h = math.hypot(r - gr, c - gc) * win.step + heapq.heappush(heap, (ng + h, ng, nxt, cur)) + return None + + +def to_plane(win, blocked_layer, via_ok, start): + """Shortest walk on one layer to anywhere a via is legal. + + A net with a plane is connected the moment it reaches a via, wherever that + via happens to be -- the plane does the rest. + """ + li, sr, sc = start + best = {(sr, sc): 0.0} + came = {(sr, sc): None} + heap = [(0.0, (sr, sc))] + while heap: + g, (r, c) = heapq.heappop(heap) + if g > best.get((r, c), 1e18): + continue + if via_ok[r, c] and (r, c) != (sr, sc): + path = [] + cur = (r, c) + while cur is not None: + path.append((li, cur[0], cur[1])); cur = came[cur] + return path[::-1] + for dr, dc, w in STEPS: + nr, nc = r + dr, c + dc + if not win.inside(nr, nc) or blocked_layer[nr, nc]: + continue + ng = g + w * win.step + if ng < best.get((nr, nc), 1e18): + best[(nr, nc)] = ng + came[(nr, nc)] = (r, c) + heapq.heappush(heap, (ng, (nr, nc))) + return None + + +def simplify(points): + out = [points[0]] + for p in points[1:]: + if len(out) >= 2: + (x0, y0), (x1, y1), (x2, y2) = out[-2], out[-1], p + if abs((x1 - x0) * (y2 - y0) - (y1 - y0) * (x2 - x0)) < 1e-9: + out[-1] = p; continue + out.append(p) + return out + + +def emit(board, win, path, code, width, via_d, via_drill, head=None, tail=None): + added = [] + runs, cur = [], [path[0]] + for node in path[1:]: + if node[0] != cur[-1][0]: + runs.append(cur); cur = [node] + else: + cur.append(node) + runs.append(cur) + + for i, run in enumerate(runs): + li = run[0][0] + pts = [win.mm(r, c) for _, r, c in run] + if i == 0 and head is not None: + pts[0] = head + if i == len(runs) - 1 and tail is not None: + pts[-1] = tail + pts = simplify(pts) + for a, b in zip(pts, pts[1:]): + if math.dist(a, b) < 1e-6: + continue + t = pcbnew.PCB_TRACK(board) + t.SetStart(pcbnew.VECTOR2I(int(a[0] * NM), int(a[1] * NM))) + t.SetEnd(pcbnew.VECTOR2I(int(b[0] * NM), int(b[1] * NM))) + t.SetWidth(int(width * NM)); t.SetLayer(win.layers[li]) + t.SetNetCode(code); board.Add(t); added.append(t) + if i + 1 < len(runs): + x, y = win.mm(run[-1][1], run[-1][2]) + v = pcbnew.PCB_VIA(board) + v.SetPosition(pcbnew.VECTOR2I(int(x * NM), int(y * NM))) + v.SetWidth(int(via_d * NM)); v.SetDrill(int(via_drill * NM)) + v.SetNetCode(code); v.SetViaType(pcbnew.VIATYPE_THROUGH) + board.Add(v); added.append(v) + return added + + +def close_plane_orphans(board, win_args, pro, code_skip, a, verbose=True): + """Give anything a rip-up orphaned its own way back to its plane. + + Ripping GND or V3V3 out of a corridor is safe precisely because those nets + have a plane to fall into, but only if whatever the ripped copper was + carrying is actually given a via. This closes that loop so the rip and the + repair are judged together, not separately. + """ + # An unconnected pair has two ends. Healing one leaves the pair listed, so + # taking "the first plane-net item" every round heals the same end forever + # and never reaches the end that was actually orphaned. + healed, seen = 0, set() + for _ in range(24): + trial = tempfile.mktemp(suffix=".kicad_pcb") + if pro: + shutil.copy(pro, Path(trial).with_suffix(".kicad_pro")) + pcbnew.ZONE_FILLER(board).Fill(board.Zones()); board.BuildConnectivity() + pcbnew.SaveBoard(trial, board) + _, _, data = drc(trial) + os.unlink(trial) + todo = None + for e in data.get("unconnected_items", []): + for it in e.get("items", []): + m = re.search(r"\[([^\]]+)\]", it.get("description", "")) + if not m or m.group(1) not in PLANE_NETS: + continue + key = (m.group(1), round(it["pos"]["x"], 3), round(it["pos"]["y"], 3)) + if key in seen: + continue + seen.add(key) + todo = (m.group(1), it); break + if todo: + break + if not todo: + return healed + name, it = todo + code = board.GetNetsByName()[name].GetNetCode() + px, py = it["pos"]["x"], it["pos"]["y"] + routable = win_args + win = Window(px - a.margin, py - a.margin, px + a.margin, py + a.margin, + a.step, routable) + blocked, via_no = obstacles(board, win, code, a.clearance, + a.width / 2, a.via / 2) + r, c = win.cell(px, py) + ls = layers_of(board, it["uuid"], routable) + if not ls: + return healed + li = {l: i for i, l in enumerate(routable)}[ls[0]] + blocked[li][r, c] = False + path = to_plane(win, blocked[li], ~via_no, (li, r, c)) + if path is None: + return healed + emit(board, win, path, code, a.width, a.via, a.drill, head=(px, py)) + x, y = win.mm(path[-1][1], path[-1][2]) + v = pcbnew.PCB_VIA(board) + v.SetPosition(pcbnew.VECTOR2I(int(x * NM), int(y * NM))) + v.SetWidth(int(a.via * NM)); v.SetDrill(int(a.drill * NM)) + v.SetNetCode(code); v.SetViaType(pcbnew.VIATYPE_THROUGH) + board.Add(v) + board.BuildConnectivity() + healed += 1 + if verbose: + print(f" heal {name:5} at ({px:.2f}, {py:.2f}) -> plane via " + f"({x:.2f}, {y:.2f})") + return healed + + +def own_copper(board, win, netcode): + """Cells already occupied by this net, per layer. + + The DRC report names one item per side of a break and gives a single point + on it. Searching from that point is a needless restriction: any part of the + same island is an equally good place to start, and the reported point is + often the worst one. The escape via placed at a ball's slot is useless if + the search insists on setting off from the ball. + """ + mine = {li: np.zeros((win.ny, win.nx), bool) for li in range(len(win.layers))} + index = {l: i for i, l in enumerate(win.layers)} + for t in board.GetTracks(): + if t.GetNetCode() != netcode: + continue + if isinstance(t, pcbnew.PCB_VIA): + p = t.GetPosition() + for i in mine: + win.disc(mine[i], p.x / NM, p.y / NM, + t.GetWidth(pcbnew.F_Cu) / 2 / NM) + else: + i = index.get(t.GetLayer()) + if i is None: + continue + a, b = t.GetStart(), t.GetEnd() + win.segment(mine[i], a.x / NM, a.y / NM, b.x / NM, b.y / NM, + t.GetWidth() / 2 / NM) + for fp in board.GetFootprints(): + for pad in fp.Pads(): + if pad.GetNetCode() != netcode: + continue + p, sz = pad.GetPosition(), pad.GetSize() + for l in win.layers: + i = index.get(l) + if i is None or not pad.IsOnLayer(l): + continue + win.disc(mine[i], p.x / NM, p.y / NM, + min(sz.x, sz.y) / 2 / NM) + return mine + + +def island(win, mine, x, y, radius, other=None): + """Cells of this net's copper near (x, y) -- one side of the break. + + `other` is the endpoint on the far side. Cells nearer to it belong to that + side and are excluded: without the split, two endpoints closer together + than twice the radius share cells, the search starts where it is meant to + finish, and the zero-length path it returns connects nothing at all. + """ + out = [] + r0, c0 = win.cell(x, y) + span = int(radius / win.step) + for li, grid in mine.items(): + for r in range(max(0, r0 - span), min(win.ny, r0 + span + 1)): + for c in range(max(0, c0 - span), min(win.nx, c0 + span + 1)): + if not grid[r, c]: + continue + if math.hypot(r - r0, c - c0) * win.step > radius: + continue + if other is not None: + px, py = win.mm(r, c) + if math.dist((px, py), other) < math.dist((px, py), (x, y)): + continue + out.append((li, r, c)) + return out + + +def layers_of(board, uuid, routable): + for t in board.GetTracks(): + if t.m_Uuid.AsString() == uuid: + return list(routable) if isinstance(t, pcbnew.PCB_VIA) else \ + ([t.GetLayer()] if t.GetLayer() in routable else []) + for fp in board.GetFootprints(): + for pad in fp.Pads(): + if pad.m_Uuid.AsString() == uuid: + return [l for l in routable if pad.IsOnLayer(l)] + return [] + + +def main(): + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("board"); ap.add_argument("--out", required=True) + ap.add_argument("--net", action="append") + ap.add_argument("--step", type=float, default=0.05) + ap.add_argument("--margin", type=float, default=4.0) + ap.add_argument("--clearance", type=float, default=0.15) + ap.add_argument("--width", type=float, default=0.15) + ap.add_argument("--via", type=float, default=0.55) + ap.add_argument("--drill", type=float, default=0.25) + ap.add_argument("--via-cost", type=float, default=1.5) + ap.add_argument("--rip-planes", action="store_true", + help="when no path exists, move GND/V3V3 copper out of the " + "way and give it a via back to its plane") + ap.add_argument("--rip-radius", type=float, default=1.6) + ap.add_argument("--guard", type=float, default=0.75, + help="extra clearance, in grid steps, to keep diagonal " + "moves legal between cells that are each only just legal") + ap.add_argument("--island", type=float, default=3.0, + help="start and finish anywhere on the net's own copper " + "within this radius of each reported endpoint") + ap.add_argument("--long-step", type=float, default=0.1, + help="grid for spans over 12 mm; the default trades " + "resolution for a tractable search, which is too " + "coarse to thread a 1.0 mm ball field") + a = ap.parse_args() + + work = Path(a.out) + shutil.copy(a.board, work) + pro = Path(a.board).with_suffix(".kicad_pro") + pro = str(pro) if pro.is_file() else None + if pro: + shutil.copy(pro, work.with_suffix(".kicad_pro")) + + v0, u0, _ = drc(str(work)) + print(f" start {v0} violation(s), {u0} unconnected pair(s)\n") + + tries: dict = {} + while True: + v_now, u_now, data = drc(str(work)) + board = pcbnew.LoadBoard(str(work)) + routable = [l for l in board.GetEnabledLayers().CuStack() + if board.GetLayerName(l) not in ("In1.Cu", "In4.Cu")] + progressed = False + + for e in data.get("unconnected_items", []): + its = e.get("items", []) + if len(its) != 2: + continue + m = re.search(r"\[([^\]]+)\]", its[0].get("description", "")) + name = m.group(1) if m else None + if not name or (a.net and name not in a.net): + continue + code = board.GetNetsByName()[name].GetNetCode() + (ax, ay), (bx, by) = ((i["pos"]["x"], i["pos"]["y"]) for i in its) + la = layers_of(board, its[0]["uuid"], routable) + lb = layers_of(board, its[1]["uuid"], routable) + if not la or not lb: + continue + + span = math.dist((ax, ay), (bx, by)) + step = a.step if span < 12 else a.long_step + win = Window(min(ax, bx) - a.margin, min(ay, by) - a.margin, + max(ax, bx) + a.margin, max(ay, by) + a.margin, + step, routable) + # The mask marks a cell when its *centre* is too close. A diagonal + # step between two acceptable cells passes nearer than either of + # them, by up to about a step, so the grid is given a guard band or + # the path is legal by construction and illegal by DRC. + guard = a.clearance + step * a.guard + blocked, via_no = obstacles(board, win, code, guard, + a.width / 2, a.via / 2) + via_ok = ~via_no + ra, ca = win.cell(ax, ay) + rb, cb = win.cell(bx, by) + idx = {l: i for i, l in enumerate(routable)} + mine = own_copper(board, win, code) + starts = [(idx[l], ra, ca) for l in la] + goals = [(idx[l], rb, cb) for l in lb] + starts += island(win, mine, ax, ay, a.island, other=(bx, by)) + goals += island(win, mine, bx, by, a.island, other=(ax, ay)) + for li, r, c in starts + goals: + blocked[li][r, c] = False + + path = search(win, blocked, via_ok, starts, goals, a.via_cost) + mode = "route" + ripped = [] + if path is None and a.rip_planes and name not in PLANE_NETS: + # The corridors this net needs are held by GND and V3V3, which + # can be moved: they have a plane underneath and a via reaches + # it from anywhere. Nothing else on the board may be touched. + for t in list(board.GetTracks()): + if t.Type() != pcbnew.PCB_TRACE_T or t.GetNetCode() == code: + continue + if t.GetNetname() not in PLANE_NETS: + continue + s_, e_ = t.GetStart(), t.GetEnd() + near = min( + pe_seg_dist(ax, ay, s_.x / NM, s_.y / NM, e_.x / NM, e_.y / NM), + pe_seg_dist(bx, by, s_.x / NM, s_.y / NM, e_.x / NM, e_.y / NM)) + if near < a.rip_radius: + ripped.append(t) + for t in ripped: + board.RemoveNative(t) + if ripped: + board.BuildConnectivity() + blocked, via_no = obstacles(board, win, code, a.clearance, + a.width / 2, a.via / 2) + via_ok = ~via_no + for li, r, c in starts + goals: + blocked[li][r, c] = False + path = search(win, blocked, via_ok, starts, goals, a.via_cost) + if path is not None: + print(f" rip {len(ripped)} plane-backed trace(s) " + f"near {name}") + else: + board = pcbnew.LoadBoard(str(work)) + continue + if path is None and name in PLANE_NETS: + for li, r, c in starts: + path = to_plane(win, blocked[li], via_ok, (li, r, c)) + if path: + mode = "plane"; break + if path is None: + continue + + # No head/tail override. Every start and goal cell lies inside + # this net's own copper, so the path already begins and ends on it; + # dragging an end back to the point the DRC report happened to name + # detaches it from the island the search actually set out from. + added = emit(board, win, path, code, a.width, a.via, a.drill) + if mode == "plane": + x, y = win.mm(path[-1][1], path[-1][2]) + v = pcbnew.PCB_VIA(board) + v.SetPosition(pcbnew.VECTOR2I(int(x * NM), int(y * NM))) + v.SetWidth(int(a.via * NM)); v.SetDrill(int(a.drill * NM)) + v.SetNetCode(code); v.SetViaType(pcbnew.VIATYPE_THROUGH) + board.Add(v); added.append(v) + + if ripped: + close_plane_orphans(board, routable, pro, code, a) + pcbnew.ZONE_FILLER(board).Fill(board.Zones()); board.BuildConnectivity() + trial = tempfile.mktemp(suffix=".kicad_pcb") + if pro: + shutil.copy(pro, Path(trial).with_suffix(".kicad_pro")) + pcbnew.SaveBoard(trial, board) + v1, u1, d1 = drc(trial) + # Crossing In3.Cu cuts the V3V3 pour, which can orphan a pad that + # was reaching the plane through the part just severed. The total + # then stays level -- one pair closed, one opened -- and a gate that + # demands the count fall discards a route that worked. Accept a + # level trade when the pair actually aimed at is gone, and let the + # next pass close what the cut orphaned. + still = any(re.search(r"\[([^\]]+)\]", i.get("description", "") or "") + and re.search(r"\[([^\]]+)\]", + i.get("description", "")).group(1) == name + for e2 in d1.get("unconnected_items", []) + for i in e2.get("items", [])) + tries[name] = tries.get(name, 0) + 1 + if v1 <= v_now and (u1 < u_now or + (u1 == u_now and not still and tries[name] <= 3)): + shutil.move(trial, str(work)) + segs = sum(1 for t in added if t.Type() == pcbnew.PCB_TRACE_T) + vias = len(added) - segs + print(f" CLOSED {name:9} {span:5.2f} mm {mode:5} " + f"{segs} seg + {vias} via -> {v1} violation(s), " + f"{u1} unconnected") + progressed = True + break + os.unlink(trial) + print(f" rejected {name:9} {span:5.2f} mm {mode:5} " + f"({v1} violation(s), {u1} unconnected)") + board = pcbnew.LoadBoard(str(work)) + if not progressed: + break + + vf, uf, _ = drc(str(work)) + print(f"\n result {v0} -> {vf} violation(s), {u0} -> {uf} unconnected") + print(f" wrote {work}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/cost.py b/hardware/courant/scripts/cost.py new file mode 100644 index 0000000..da19fed --- /dev/null +++ b/hardware/courant/scripts/cost.py @@ -0,0 +1,108 @@ +#!/usr/bin/env python3 +""" +Cost the board from its own BOM. + +Unit prices marked `verified` were read from live JLCPCB/LCSC stock while this +was written. The rest are marked `est` and are the author's estimate; they are +small parts and the total is not sensitive to them, but they are labelled so +nobody mistakes a guess for a quote. + +Nothing here is a quotation. Board and assembly pricing is a model of JLCPCB's +published structure, not a cart total, and both move with panel utilisation, +lead time and whatever the assembler decides about a given part. + + python3 scripts/cost.py --bom deliverables/courant-bom.csv +""" +from __future__ import annotations + +import argparse, csv, re +from collections import defaultdict + +# MPN or (value, footprint) -> (unit price USD, verified?) +PRICE = { + "XC7A50T-1FTG256I": (67.01, True), "TPS62130ARGTR": (0.9245, True), + "PCM5102APWR": (1.4062, True), "MCP3208-CI/SL": (3.3283, True), + "FNR4030S1R0MT": (0.0567, True), + "TCC0201X5R104K100ZT": (0.0013, True), "CL10B104KB8NNNC": (0.0104, True), + "GRM1885C1H103JA01D": (0.0292, True), "CL10B105KB8NQNC": (0.0267, True), + "CL10A225KO8NNNC": (0.0189, True), "CC0805KKX7R8BB475": (0.0878, True), + "CL21A106KAYNNNE": (0.0844, True), "CL21A226MAQNNNE": (0.2432, True), + "GRM32ER61C476KE15L": (0.3003, True), "RC0603FR-0710KL": (0.0035, True), + "RC0603FR-0724K9L": (0.0061, True), "RT0603BRD0720KL": (0.0346, True), + "ASE-100.000MHZ-LC-T": (0.3086, True), "ASE-12.288MHZ-LC-T": (0.3086, True), + # estimates + "REF3125AIDBZR": (1.80, False), # genuine TI; an XBLW clone is $0.55 and + # is a poor trade on a voltage reference + "W25Q64JVSSIQ": (0.60, False), "MCP6002-I/SN": (0.35, False), + "MCP6561T-E/OT": (0.45, False), "H11L1M": (0.90, False), + "BAT54S": (0.04, False), "1N4148W": (0.01, False), + "GRM1885C1H102JA01D": (0.03, False), "GRM1885C1H222JA01D": (0.03, False), + "GRM1885C1H332JA01D": (0.03, False), +} +RES_DEFAULT = (0.005, False) # any other RC0603FR thick film +HEADER_DEFAULT = (0.10, False) # 2.54 mm pin header, per connector + +# JLCPCB structure, as a range. Low end assumes a good panel and no surprises. +PCB_5 = (90.0, 140.0) # 6-layer, 160.1 x 100.1 mm, minimum order 5 +STENCIL = (8.0, 15.0) +SETUP = (16.0, 30.0) # SMT setup, both sides +EXT_FEE = (2.5, 3.0) # per distinct extended-library part +PLACE = (0.11, 0.19) # per placement +BASIC = {"CL21A226MAQNNNE", "CL21A106KAYNNNE", "CL10A225KO8NNNC"} + + +def main(): + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("--bom", default="deliverables/courant-bom.csv") + ap.add_argument("--qty", type=int, nargs="*", default=[1, 2, 5, 10, 25]) + a = ap.parse_args() + + rows = list(csv.DictReader(open(a.bom))) + parts = 0.0 + unverified = 0.0 + placements = 0 + distinct_ext = set() + for r in rows: + qty = int(r["Qty"]); mpn = r["MPN"] + placements += qty + if mpn.startswith("1x") and "header" in mpn: + unit, ok = HEADER_DEFAULT + elif mpn in PRICE: + unit, ok = PRICE[mpn] + elif mpn.startswith("RC0603FR"): + unit, ok = RES_DEFAULT + else: + unit, ok = 0.05, False + parts += unit * qty + if not ok: + unverified += unit * qty + if mpn not in BASIC: + distinct_ext.add(mpn) + + print(f" {len(rows)} line items, {placements} placements") + print(f" parts per board ${parts:,.2f}" + f" (${parts - unverified:,.2f} verified, ${unverified:,.2f} estimated)") + print(f" distinct extended-library parts: {len(distinct_ext)}\n") + + fixed_lo = PCB_5[0] + STENCIL[0] + SETUP[0] + EXT_FEE[0] * len(distinct_ext) + fixed_hi = PCB_5[1] + STENCIL[1] + SETUP[1] + EXT_FEE[1] * len(distinct_ext) + print(f" one-time: PCB 5 pcs ${PCB_5[0]:.0f}-{PCB_5[1]:.0f}, stencil " + f"${STENCIL[0]:.0f}-{STENCIL[1]:.0f}, setup ${SETUP[0]:.0f}-{SETUP[1]:.0f}, " + f"{len(distinct_ext)} extended parts " + f"${EXT_FEE[0] * len(distinct_ext):.0f}-{EXT_FEE[1] * len(distinct_ext):.0f}") + print(f" = ${fixed_lo:,.0f} - ${fixed_hi:,.0f}\n") + + print(f" {'built':>6} {'total':>18} {'per board':>16}") + for q in a.qty: + extra_pcb = 0.0 if q <= 5 else (PCB_5[0] / 5) * (q - 5) + lo = fixed_lo + q * (parts + PLACE[0] * placements) + extra_pcb + hi = fixed_hi + q * (parts + PLACE[1] * placements) + extra_pcb * 1.6 + print(f" {q:>6} ${lo:>7,.0f} - ${hi:<7,.0f} ${lo / q:>6,.0f} - ${hi / q:<6,.0f}") + print("\n panel hardware adds about $16 per instrument " + "(see courant-panel-hardware.md)") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/export.ts b/hardware/courant/scripts/export.ts new file mode 100644 index 0000000..79f72f0 --- /dev/null +++ b/hardware/courant/scripts/export.ts @@ -0,0 +1,129 @@ +import { existsSync as nativeBaselineExists } from "node:fs"; +if (nativeBaselineExists(new URL("../NATIVE_BASELINE.json", import.meta.url))) throw new Error("Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json."); +/** + * Fabrication and toolchain outputs. + * + * Everything that is a standard circuit-json conversion is delegated to + * `tsci export`. The one artifact tscircuit cannot produce is the Vivado pin + * constraints file: it is the board's half of the contract with the RTL in + * `src/rtl/synth_top.vhd`, and it is generated here from the same `io` map the + * schematic uses so the two cannot drift apart. + */ +import { spawnSync } from "node:child_process" +import { mkdirSync, writeFileSync } from "node:fs" +import pins from "../fpga-pins.json" +import { io } from "../design" + +const OUT = "dist" +const ENTRY = "courant.circuit.tsx" +mkdirSync(OUT, { recursive: true }) + +// `kicad_pcb` is the handoff: `scripts/route.py` takes it from here, through +// Freerouting and back, and `scripts/fab.py` plots the Gerbers from the result. +// +// `specctra-dsn` is deliberately NOT in this list, even though tscircuit offers +// it. Its converter places every component `side: "front"` regardless of the +// layer it is on, which silently moves all 38 back-side BGA decoupling +// capacitors to the top of the board, and it throws outright on a pad with a +// null `pcb_component_id` -- which is what this board's three fiducials emit. +// KiCad writes the DSN instead, from the board below; see scripts/route.py. +// +// Gerbers are likewise not exported here. They are plotted from the *routed* +// board by scripts/fab.py, which refuses to run on an unrouted one: Gerbers +// with pads, mask and drills but no copper look exactly like fabrication data +// and are not. +const formats: [string, string][] = [ + ["circuit-json", "courant.circuit.json"], + ["readable-netlist", "courant.netlist.txt"], + ["schematic-svg", "courant.schematic.svg"], + ["pcb-svg", "courant.pcb.svg"], + ["kicad_pcb", "courant.kicad_pcb"], +] + +let failed = 0 +for (const [format, file] of formats) { + const r = spawnSync("tsci", ["export", ENTRY, "-f", format, "-o", `${OUT}/${file}`, "--disable-parts-engine"], { + stdio: "inherit", + }) + if (r.status !== 0) { console.error(` export ${format} failed`); failed++ } +} + +// ------------------------------------------------------- Vivado constraints --- +const byBall = Object.fromEntries(pins.map((p) => [p.ball, p])) +// Ports the RTL drives or samples directly, in synth_top.vhd's spelling. +const rename: Record = { + clk100: "clk100", audio_mclk_in: "mclk", midi_rx: "midi_rx", reset_n: "reset_n", + cv_select: "cv_sel", gate: "gate", + dac_mclk: "codec_mclk", dac_bclk: "codec_bclk", dac_lrclk: "codec_lrclk", + dac_data: "sd_tx", dac_unmute: "dac_unmute", + adc_sclk: "adc_sclk", adc_mosi: "adc_mosi", adc_miso: "adc_miso", adc_cs_n: "adc_cs_n", + enc_a: "enc_a", enc_b: "enc_b", enc_btn_n: "enc_btn_n", + led0: "active[0]", led1: "active[1]", led2: "active[2]", led3: "active[3]", +} +const lines = [ + "# courant_rev_a.xdc - pin constraints for the Courant standalone board (Rev A).", + "#", + "# GENERATED by hardware/courant/scripts/export.ts from the board's `io` map.", + "# Do not edit by hand: change design.ts and re-run `npm run export`.", + "#", + "# These are the board's pins. They constrain a board-level top wrapper for", + "# this PCB, analogous to syn/vivado/arty_synth.vhd for the Arty A7 -- that", + "# wrapper is not written yet, and it additionally needs an SPI master to read", + "# the MCP3208 into synth_top's pitch_cv / mod_cv / pot_* sample ports.", + "#", + "# Every bank in use has its VCCO tied to 3.3 V on the board, so all user I/O", + "# is LVCMOS33. Board net names are given in the trailing comment.", + "", + "#" + "=".repeat(78), + "# Clocks: separate 100 MHz system and 12.288 MHz audio oscillators, so the", + "# audio master clock carries no fractional-MMCM error.", + "#" + "=".repeat(78), +] +const clocks: Record = { clk100: 10.0, mclk: 81.38 } +for (const [ball, net] of Object.entries(io)) { + const port = rename[net] + if (!port) continue + if (!(port in clocks)) continue + lines.push( + `set_property -dict { PACKAGE_PIN ${ball} IOSTANDARD LVCMOS33 } [get_ports ${port}]`, + `create_clock -name ${port} -period ${clocks[port].toFixed(3)} [get_ports ${port}]`, + ) +} +const groups: [string, RegExp][] = [ + ["Audio codec (PCM5102A, FPGA is I2S master)", /^(codec_|sd_tx|dac_unmute)/], + ["Panel ADC (MCP3208 over SPI)", /^adc_/], + ["Panel controls and CV", /^(enc_|cv_sel|gate|reset_n)/], + ["MIDI in (opto-isolated, 31250 baud)", /^midi_/], + ["Voice activity LEDs", /^active/], +] +for (const [title, re] of groups) { + lines.push("", "#" + "=".repeat(78), `# ${title}`, "#" + "=".repeat(78)) + for (const [ball, net] of Object.entries(io)) { + const port = rename[net] + if (!port || port in clocks || !re.test(port)) continue + const p = byBall[ball] + lines.push( + `set_property -dict { PACKAGE_PIN ${ball} IOSTANDARD LVCMOS33 } [get_ports {${port}}] ;# ${net}, bank ${p.bank}`, + ) + } +} +lines.push( + "", + "#" + "=".repeat(78), + "# Asynchronous inputs. Each is synchronised in fabric before use; constrain", + "# them as false paths so they do not gate timing closure.", + "#" + "=".repeat(78), + "set_false_path -from [get_ports {enc_a enc_b enc_btn_n gate cv_sel midi_rx reset_n}]", + "", + "#" + "=".repeat(78), + "# Configuration: master SPI from the on-board W25Q64JV, 3.3 V config bank.", + "#" + "=".repeat(78), + "set_property CFGBVS VCCO [current_design]", + "set_property CONFIG_VOLTAGE 3.3 [current_design]", + "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]", + "set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]", + "", +) +writeFileSync(`${OUT}/courant_rev_a.xdc`, lines.join("\n")) +console.log(`wrote ${OUT}/courant_rev_a.xdc (${Object.keys(rename).length} ports)`) +process.exit(failed ? 1 : 0) diff --git a/hardware/courant/scripts/fab.py b/hardware/courant/scripts/fab.py new file mode 100644 index 0000000..23860cb --- /dev/null +++ b/hardware/courant/scripts/fab.py @@ -0,0 +1,196 @@ +#!/usr/bin/env python3 +""" +Design rule check and fabrication outputs for the routed board. + +Runs against `dist/courant.routed.kicad_pcb`, which `scripts/route.py` writes. +It refuses to run on the unrouted board on purpose: Gerbers plotted from a +board with no copper look exactly like fabrication data and are not, and that +is the one mistake in this directory that would cost real money. + + python3 scripts/fab.py # DRC, then Gerbers/drill/placement/BOM + python3 scripts/fab.py --drc-only + +Outputs land in dist/fab/. Requires KiCad 9+ (`kicad-cli` and `pcbnew`). +""" +from __future__ import annotations + +import argparse +import csv +import shutil +import subprocess +import sys +from pathlib import Path + +HERE = Path(__file__).resolve().parent +ROOT = HERE.parent +DIST = ROOT / "dist" +ROUTED = DIST / "courant.routed.kicad_pcb" +FAB = DIST / "fab" + +# Every copper layer plus the mask, paste, silkscreen and outline the fab needs. +LAYERS = ("F.Cu,In1.Cu,In2.Cu,In3.Cu,In4.Cu,B.Cu," + "F.Paste,B.Paste,F.SilkS,B.SilkS,F.Mask,B.Mask,Edge.Cuts") + + +def load_pcbnew(): + """Import KiCad's pcbnew module without its startup noise. + + Importing pcbnew outside the KiCad application prints a page of + `assert "m_choices.GetCount() > 0" failed in PROPERTY_ENUM()` to stderr + while it registers property enums it has no UI for. It is harmless and + there is no flag for it, so file descriptor 2 is closed over the import + only -- anything these scripts actually report still reaches the terminal. + """ + import importlib + import os as _os + saved = _os.dup(2) + devnull = _os.open(_os.devnull, _os.O_WRONLY) + try: + _os.dup2(devnull, 2) + return importlib.import_module("pcbnew") + finally: + _os.dup2(saved, 2) + _os.close(saved) + _os.close(devnull) + + +def die(msg: str) -> None: + print(f"fab: {msg}", file=sys.stderr) + raise SystemExit(1) + + +def run(*cmd: str) -> subprocess.CompletedProcess: + return subprocess.run([str(c) for c in cmd], capture_output=True, text=True) + + +def drc() -> int: + """Run KiCad's DRC and print the violation summary. + + Zones are refilled first: a stale pour would let a real clearance error + through, and the copper under the BGA is entirely pour. + """ + report = DIST / "courant.drc.rpt" + r = run("kicad-cli", "pcb", "drc", "--output", report, "--format", "report", + "--units", "mm", "--severity-error", "--severity-warning", + "--refill-zones", "--exit-code-violations", ROUTED) + text = report.read_text() if report.is_file() else r.stdout + counts = {} + for line in text.splitlines(): + line = line.strip() + for kind in ("violations", "unconnected items", "schematic parity"): + if line.startswith("** Found") and kind in line: + counts[kind] = int(line.split()[2]) + for kind, n in counts.items(): + print(f" drc {n} {kind}") + if not counts: + print(" drc " + (r.stdout.strip().splitlines() or ["no report"])[-1]) + print(f" wrote {report.relative_to(ROOT)}") + return r.returncode + + +def preview() -> None: + """Plot a top and bottom view of the routed board as SVG and PNG. + + Generated here rather than by hand so the pictures cannot drift from the + copper they claim to show. SVG is the artifact worth keeping -- it is + vector, so it zooms losslessly into the BGA escape -- and the PNG exists + only because most things that display an image will not render SVG. + """ + views = { + "courant-top": "F.Cu,In1.Cu,F.SilkS,F.Mask,Edge.Cuts", + "courant-bottom": "B.Cu,In4.Cu,B.SilkS,B.Mask,Edge.Cuts", + } + made = [] + for name, layers in views.items(): + svg = DIST / f"{name}.svg" + r = run("kicad-cli", "pcb", "export", "svg", "--mode-single", + "--exclude-drawing-sheet", "--fit-page-to-board", + "--page-size-mode", "2", "-l", layers, "-o", svg, ROUTED) + if r.returncode: + print(f" preview {name}.svg failed:\n{r.stdout}{r.stderr}") + continue + made.append(svg.name) + if shutil.which("magick"): + png = DIST / f"{name}.png" + if run("magick", "-density", "160", "-background", "white", svg, + "-flatten", "-resize", "2000x", png).returncode == 0: + made.append(png.name) + print(f" preview {', '.join(made) if made else 'none'}") + + +def bom() -> None: + """Write a flat BOM grouped by value and footprint, straight from the board. + + Generated from the routed board rather than from design.ts so that what is + ordered is what is on the copper. + """ + pcbnew = load_pcbnew() + board = pcbnew.LoadBoard(str(ROUTED)) + groups: dict[tuple[str, str], list[str]] = {} + for fp in board.GetFootprints(): + if not fp.GetReference(): + continue # mounting holes, thermal helpers and fiducials are not BOM parts + key = (fp.GetValue(), str(fp.GetFPID().GetLibItemName())) + groups.setdefault(key, []).append(fp.GetReference()) + out = FAB / "courant-bom.csv" + with out.open("w", newline="") as fh: + w = csv.writer(fh) + w.writerow(["Comment", "Designator", "Footprint", "Quantity"]) + for (value, footprint), refs in sorted(groups.items()): + refs.sort() + w.writerow([value, ",".join(refs), footprint, len(refs)]) + print(f" bom {len(groups)} line items, " + f"{sum(len(r) for r in groups.values())} placements") + + +def main() -> int: + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("--drc-only", action="store_true") + args = ap.parse_args() + + if not shutil.which("kicad-cli"): + die("kicad-cli not found; install KiCad 9 or newer.") + if not ROUTED.is_file(): + die(f"{ROUTED.relative_to(ROOT)} not found.\n" + "Route the board first: python3 scripts/route.py\n" + "Gerbers are not plotted from the unrouted board on purpose -- they " + "would carry pads, mask and drills but no copper.") + + status = drc() + if args.drc_only: + return status + if status: + die("Native DRC did not pass; existing fabrication outputs left untouched.") + + FAB.mkdir(parents=True, exist_ok=True) + for f in FAB.iterdir(): + f.unlink() + + r = run("kicad-cli", "pcb", "export", "gerbers", "-o", FAB, "--layers", LAYERS, + "--no-protel-ext", "--check-zones", "--subtract-soldermask", ROUTED) + if r.returncode: + die(f"gerber export failed:\n{r.stdout}{r.stderr}") + r = run("kicad-cli", "pcb", "export", "drill", "-o", FAB, "--format", "excellon", + "--excellon-separate-th", "--excellon-units", "mm", + "--generate-map", "--map-format", "gerberx2", ROUTED) + if r.returncode: + die(f"drill export failed:\n{r.stdout}{r.stderr}") + r = run("kicad-cli", "pcb", "export", "pos", "-o", FAB / "courant-pos.csv", + "--format", "csv", "--units", "mm", "--side", "both", ROUTED) + if r.returncode: + die(f"placement export failed:\n{r.stdout}{r.stderr}") + bom() + preview() + + files = sorted(FAB.iterdir()) + print(f" gerbers {len(files)} files in {FAB.relative_to(ROOT)}/") + archive = shutil.make_archive(str(DIST / "courant-fab"), "zip", FAB) + print(f" wrote {Path(archive).relative_to(ROOT)}") + if status: + print(" NOTE DRC reported violations; see dist/courant.drc.rpt") + return status + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/finish.py b/hardware/courant/scripts/finish.py new file mode 100644 index 0000000..3b39835 --- /dev/null +++ b/hardware/courant/scripts/finish.py @@ -0,0 +1,119 @@ +#!/usr/bin/env python3 +""" +Close what the router left open, and say what it could not. + +Run this on an imported routed board. It reports the residue by net, then +closes the part that is mechanical: a capacitor land on GND or V3V3 only has +to reach a plane, and In1/In4 and In3 cover the whole board, so the connection +is a short link to neighbouring copper of the same net or -- failing that -- a +via of its own. + +Link first, via second, deliberately. Vias are the scarce resource under a +1.0 mm BGA: 225 interior slots, less the 38 the capacitor array sits on, is +187 usable, against 36 signal escapes plus 76 power ball vias plus 76 +capacitor lands = 188 wanted. One via per land does not fit and strands +whichever lands are handled last, which is exactly what happened the first +time this was tried. Chaining neighbours onto a shared via is what the +original routing did, and it was right to. + +V1 and V1V8 have no plane anywhere in the six-layer stackup, so their lands +cannot be closed this way and are reported rather than touched. + +Every change is checked: the board is kept only if KiCad's DRC reports no more +violations and no more unconnected items than it started with. + + python3 scripts/finish.py BOARD --out OUT +""" +from __future__ import annotations + +if __name__ == "__main__": + from pathlib import Path as _NativePath + if (_NativePath(__file__).resolve().parents[1]/"NATIVE_BASELINE.json").exists(): + raise SystemExit('Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.') + + +import argparse, collections, json, os, re, shutil, sys, tempfile +from pathlib import Path + +sys.path.insert(0, str(Path(__file__).resolve().parent)) +from plane_escape import pcbnew, NM, drc, repair, PLANE_NETS + + +def residue(data): + """Unconnected items grouped by net, read out of the DRC report.""" + by_net = collections.Counter() + where = collections.defaultdict(list) + for e in data.get("unconnected_items", []): + for it in e.get("items", []): + m = re.search(r"\[([^\]]+)\]", it.get("description", "")) + if not m: + continue + by_net[m.group(1)] += 1 + where[m.group(1)].append((it["pos"]["x"], it["pos"]["y"], + it.get("description", ""))) + return by_net, where + + +def main(): + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("board"); ap.add_argument("--out", required=True) + ap.add_argument("--reach", type=float, default=1.6) + ap.add_argument("--clearance", type=float, default=0.15) + ap.add_argument("--via", type=float, default=0.55) + ap.add_argument("--drill", type=float, default=0.25) + ap.add_argument("--width", type=float, default=0.25) + ap.add_argument("--report-only", action="store_true") + ap.add_argument("--prefer", choices=("link", "via"), default="link", + help="link shares a via with a neighbour and is the right " + "default under the ball field, where vias are scarce; " + "via is what a land cut off from its plane needs") + a = ap.parse_args() + + work = Path(a.out) + shutil.copy(a.board, work) + pro = Path(a.board).with_suffix(".kicad_pro") + pro = str(pro) if pro.is_file() else None + if pro: + shutil.copy(pro, work.with_suffix(".kicad_pro")) + + v0, u0, data = drc(str(work)) + by_net, where = residue(data) + print(f" start {v0} violation(s), {u0} unconnected pair(s)\n") + print(" residue by net:") + for net, n in by_net.most_common(): + tag = ("plane" if net in PLANE_NETS else + "no plane" if net in ("V1", "V1V8") else "signal") + print(f" {net:16} {n:3} ({tag})") + if a.report_only: + return 0 + + print() + board = pcbnew.LoadBoard(str(work)) + added = repair(board, pro, a.via / 2 + a.clearance, a.reach, + a.width, a.via, a.drill, prefer=a.prefer) + pcbnew.ZONE_FILLER(board).Fill(board.Zones()); board.BuildConnectivity() + + trial = tempfile.mktemp(suffix=".kicad_pcb") + if pro: + shutil.copy(pro, Path(trial).with_suffix(".kicad_pro")) + pcbnew.SaveBoard(trial, board) + v1, u1, data1 = drc(trial) + print(f"\n closed {added} land(s)") + print(f" result {v0} -> {v1} violation(s), {u0} -> {u1} unconnected") + if v1 > v0 or u1 > u0: + os.unlink(trial) + print(" REVERTED not an improvement; board left untouched") + return 1 + shutil.move(trial, str(work)) + left, _ = residue(data1) + if left: + print("\n still open:") + for net, n in left.most_common(): + print(f" {net:16} {n:3}") + print(f"\n wrote {work}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/gnd_stitch.py b/hardware/courant/scripts/gnd_stitch.py new file mode 100644 index 0000000..2ad42a2 --- /dev/null +++ b/hardware/courant/scripts/gnd_stitch.py @@ -0,0 +1,179 @@ +#!/usr/bin/env python3 +""" +Replace the back-side decoupling caps' ground daisy-chain with plane vias. + +The autorouter connected the 38 decoupling capacitors' ground pads by running +B.Cu traces from one cap to the next, 3 mm at a time, threading between the BGA +balls. Electrically that is poor -- a cap's return current takes a sideways trip +through its neighbours instead of dropping into the ground plane a fraction of a +millimetre below -- and it is also what blocks the escape slots the remaining +BGA balls need, because those chains run exactly through the diagonal gaps. + +Both problems have the same fix: delete the chain and give each ground pad its +own via into the plane. + +Each removal orphans whatever was downstream, so the two go together: cut, then +re-via every ground pad DRC reports as disconnected, repeat until stable. The +whole thing is judged at the end by KiCad, and discarded unless the board comes +out at least as good as it went in. + + python3 scripts/gnd_stitch.py BOARD --out OUT +""" +from __future__ import annotations + +if __name__ == "__main__": + from pathlib import Path as _NativePath + if (_NativePath(__file__).resolve().parents[1]/"NATIVE_BASELINE.json").exists(): + raise SystemExit('Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.') + + +import argparse, json, math, os, shutil, subprocess, tempfile +from pathlib import Path + + +def load_pcbnew(): + import importlib + saved, devnull = os.dup(2), os.open(os.devnull, os.O_WRONLY) + try: + os.dup2(devnull, 2) + return importlib.import_module("pcbnew") + finally: + os.dup2(saved, 2); os.close(saved); os.close(devnull) + + +pcbnew = load_pcbnew() +NM = 1_000_000 + + +def drc(path): + o = tempfile.mktemp(suffix=".json") + subprocess.run(["kicad-cli", "pcb", "drc", "--output", o, "--format", "json", + "--units", "mm", "--severity-error", "--refill-zones", path], + capture_output=True, text=True) + j = json.load(open(o)); os.unlink(o) + return len(j.get("violations", [])), len(j.get("unconnected_items", [])), j + + +def clear_spot(board, net, px, py, need, limit=1.5): + for r in [i * 0.05 for i in range(2, int(limit / 0.05) + 1)]: + for k in range(32): + ang = 2 * math.pi * k / 32 + sx, sy = px + r * math.cos(ang), py + r * math.sin(ang) + ok = True + for t in board.GetTracks(): + if t.GetNetCode() == net: + continue + if t.Type() == pcbnew.PCB_VIA_T: + p = t.GetPosition() + if math.hypot(p.x/1e6-sx, p.y/1e6-sy) < t.GetWidth(pcbnew.F_Cu)/2/1e6 + need: + ok = False; break + else: + a, e = t.GetStart(), t.GetEnd(); rr = t.GetWidth()/2/1e6 + x1, y1, x2, y2 = a.x/1e6, a.y/1e6, e.x/1e6, e.y/1e6 + dx, dy = x2-x1, y2-y1; L = dx*dx + dy*dy + tt = 0 if L == 0 else max(0, min(1, ((sx-x1)*dx + (sy-y1)*dy)/L)) + if math.hypot(sx-(x1+tt*dx), sy-(y1+tt*dy)) < rr + need: + ok = False; break + if ok: + for fp in board.GetFootprints(): + for pad in fp.Pads(): + if pad.GetNetCode() == net: + continue + p = pad.GetPosition() + rr = max(pad.GetSize().x, pad.GetSize().y)/2/1e6 + if math.hypot(p.x/1e6-sx, p.y/1e6-sy) < rr + need: + ok = False; break + if not ok: + break + if ok: + return (sx, sy) + return None + + +def main(): + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("board"); ap.add_argument("--out", required=True) + ap.add_argument("--clearance", type=float, default=0.16) + ap.add_argument("--via", type=float, default=0.55) + ap.add_argument("--drill", type=float, default=0.25) + ap.add_argument("--max-len", type=float, default=3.5, + help="longest B.Cu ground hop treated as chain, in mm") + a = ap.parse_args() + + work = Path(a.out); shutil.copy(a.board, work) + pro = Path(a.board).with_suffix(".kicad_pro") + if pro.is_file(): + shutil.copy(pro, work.with_suffix(".kicad_pro")) + v0, u0, _ = drc(str(work)) + print(f" start {v0} violation(s), {u0} unconnected") + need = a.via / 2 + a.clearance + + board = pcbnew.LoadBoard(str(work)) + gnd = board.FindNet("GND").GetNetCode() + # Ground pads of the back-side decoupling array. + pads = [(fp.GetReference(), pad.GetPosition()) + for fp in board.GetFootprints() if fp.IsFlipped() + for pad in fp.Pads() if pad.GetNetCode() == gnd] + near = lambda p, q: math.hypot(p.x-q.x, p.y-q.y)/1e6 < 0.4 + + doomed = [] + for t in board.GetTracks(): + if t.Type() != pcbnew.PCB_TRACE_T or t.GetNetCode() != gnd: + continue + if t.GetLayer() != pcbnew.B_Cu or t.GetLength()/1e6 > a.max_len: + continue + s, e = t.GetStart(), t.GetEnd() + if any(near(s, q) for _, q in pads) and any(near(e, q) for _, q in pads): + doomed.append(t) + for t in doomed: + board.Remove(t) + print(f" cut {len(doomed)} chain hop(s) between decoupling ground pads") + pcbnew.ZONE_FILLER(board).Fill(board.Zones()); board.BuildConnectivity() + pcbnew.SaveBoard(str(work), board) + + total_vias = 0 + for _ in range(12): + v, u, data = drc(str(work)) + orphans = [] + for e in data.get("unconnected_items", []): + for i in e["items"]: + if "[GND]" in i["description"] and " of C" in i["description"]: + orphans.append((i["description"].split(" of ")[1].split()[0], + i["pos"]["x"], i["pos"]["y"])) + if not orphans: + break + board = pcbnew.LoadBoard(str(work)) + gnd = board.FindNet("GND").GetNetCode() + added = 0 + for ref, px, py in orphans: + spot = clear_spot(board, gnd, px, py, need) + if not spot: + continue + via = pcbnew.PCB_VIA(board) + via.SetPosition(pcbnew.VECTOR2I(int(spot[0]*NM), int(spot[1]*NM))) + via.SetWidth(int(a.via*NM)); via.SetDrill(int(a.drill*NM)) + via.SetNetCode(gnd); via.SetViaType(pcbnew.VIATYPE_THROUGH); board.Add(via) + t = pcbnew.PCB_TRACK(board) + t.SetStart(pcbnew.VECTOR2I(int(px*NM), int(py*NM))) + t.SetEnd(pcbnew.VECTOR2I(int(spot[0]*NM), int(spot[1]*NM))) + t.SetWidth(int(0.3*NM)); t.SetLayer(pcbnew.B_Cu) + t.SetNetCode(gnd); board.Add(t) + added += 1 + if not added: + break + total_vias += added + pcbnew.ZONE_FILLER(board).Fill(board.Zones()); board.BuildConnectivity() + pcbnew.SaveBoard(str(work), board) + print(f" vias {total_vias} ground pad(s) dropped straight into the plane") + + vf, uf, _ = drc(str(work)) + print(f"\n result {v0} -> {vf} violation(s), {u0} -> {uf} unconnected") + if vf > v0 or uf > u0: + print(" NOTE not an improvement; discard this file") + print(f" wrote {work}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/hop.py b/hardware/courant/scripts/hop.py new file mode 100644 index 0000000..db5e284 --- /dev/null +++ b/hardware/courant/scripts/hop.py @@ -0,0 +1,246 @@ +#!/usr/bin/env python3 +""" +Close short unconnected pairs by placing the copper directly. + +What the router leaves behind on this board is mostly not routing: thirteen of +the fourteen remaining pairs are under 2.6 mm apart, and several under 1 mm. +They are two ends of the same net that need a wire between them, and a +topological router that has already decided it cannot place one will keep +deciding that. Placing it geometrically is both more direct and checkable. + +For each pair this tries, in order of preference: + + * a straight segment on a layer both endpoints can reach; + * an L, cornering at either right angle; + * a mitred L, turning through 45 degrees, which fits where a square corner + does not because the diagonal keeps clear of pads on both sides. + +Each candidate is sampled along its length against every piece of foreign +copper on that layer, and through vias on all of them. The first that is clear +is placed, the board is re-checked with KiCad's DRC, and it is kept only if the +unconnected count fell and the violation count did not rise. Anything else is +rolled back, so a failure costs nothing but time. + + python3 scripts/hop.py BOARD --out OUT [--max-span MM] +""" +from __future__ import annotations + +if __name__ == "__main__": + from pathlib import Path as _NativePath + if (_NativePath(__file__).resolve().parents[1]/"NATIVE_BASELINE.json").exists(): + raise SystemExit('Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.') + + +import argparse, json, math, os, re, shutil, subprocess, sys, tempfile +from pathlib import Path + +sys.path.insert(0, str(Path(__file__).resolve().parent)) +from plane_escape import (pcbnew, NM, drc, obstacles, obstacles_on, + clear_at, path_clear, find_slot) + + +def layers_of(board, uuid): + """Copper layers an item occupies; a through via reaches all of them.""" + for t in board.GetTracks(): + if t.m_Uuid.AsString() == uuid: + if isinstance(t, pcbnew.PCB_VIA): + return [l for l in board.GetEnabledLayers().CuStack()] + return [t.GetLayer()] + for fp in board.GetFootprints(): + for pad in fp.Pads(): + if pad.m_Uuid.AsString() == uuid: + return [l for l in board.GetEnabledLayers().CuStack() + if pad.IsOnLayer(l)] + return [] + + +def candidates(ax, ay, bx, by): + """Straight, then square corners, then 45 degree mitres.""" + yield [(ax, ay), (bx, by)] + yield [(ax, ay), (bx, ay), (bx, by)] + yield [(ax, ay), (ax, by), (bx, by)] + dx, dy = bx - ax, by - ay + if abs(dx) > 1e-9 and abs(dy) > 1e-9: + m = min(abs(dx), abs(dy)) + sx, sy = math.copysign(m, dx), math.copysign(m, dy) + yield [(ax, ay), (ax + sx, ay + sy), (bx, by)] + yield [(ax, ay), (bx - sx, by - sy), (bx, by)] + + +def main(): + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("board"); ap.add_argument("--out", required=True) + ap.add_argument("--max-span", type=float, default=4.0, + help="skip pairs further apart than this; they are routing, " + "not a hop") + ap.add_argument("--clearance", type=float, default=0.15) + ap.add_argument("--width", type=float, default=0.2) + a = ap.parse_args() + + work = Path(a.out) + shutil.copy(a.board, work) + pro = Path(a.board).with_suffix(".kicad_pro") + pro = str(pro) if pro.is_file() else None + if pro: + shutil.copy(pro, work.with_suffix(".kicad_pro")) + + v0, u0, _ = drc(str(work)) + print(f" start {v0} violation(s), {u0} unconnected pair(s)\n") + need = a.width / 2 + a.clearance + placed = skipped = rejected = 0 + + while True: + v_now, u_now, data = drc(str(work)) + board = pcbnew.LoadBoard(str(work)) + progressed = False + for e in data.get("unconnected_items", []): + its = e.get("items", []) + if len(its) != 2: + continue + (ax, ay), (bx, by) = ((i["pos"]["x"], i["pos"]["y"]) for i in its) + span = math.dist((ax, ay), (bx, by)) + if span > a.max_span: + continue + m = re.search(r"\[([^\]]+)\]", its[0].get("description", "")) + name = m.group(1) if m else "?" + la = set(layers_of(board, its[0]["uuid"])) + lb = set(layers_of(board, its[1]["uuid"])) + shared = [l for l in board.GetEnabledLayers().CuStack() if l in la & lb] + code = board.GetNetsByName()[name].GetNetCode() if name in \ + board.GetNetsByName() else None + if code is None: + continue + + done = False + # Endpoints on different layers need a via in the hop; most of what + # survives the router is this shape, because the capacitor is on the + # back and the rail it must reach runs on the front. + if not shared: + vneed = 0.55 / 2 + a.clearance + discs, segs = obstacles(board, code) + # Search for somewhere the via can actually go, nearest the + # midpoint first. Under the ball field the obvious three points + # -- both endpoints and the midpoint -- are all occupied, and + # trying only those finds nothing at all. + mx, my = (ax + bx) / 2, (ay + by) / 2 + spots = [] + for i in range(-50, 51): + for jj in range(-50, 51): + px, py = mx + i * 0.05, my + jj * 0.05 + d = math.hypot(px - mx, py - my) + if d > 2.5: + continue + if clear_at(discs, segs, px, py, vneed): + spots.append((d, px, py)) + spots.sort() + for _, vx, vy in spots[:80]: + # A leg may dogleg as well. Straight-only legs fail on + # pairs where the via slot is reachable but not in a + # straight line from the pad -- which is most of them once + # the easy ones are gone. + legs = [] + for (px, py), ls in (((ax, ay), la), ((bx, by), lb)): + if math.dist((px, py), (vx, vy)) < 1e-3: + continue + leg = None + for l in board.GetEnabledLayers().CuStack(): + if l not in ls: + continue + d2, s2 = obstacles_on(board, code, l) + for route in candidates(px, py, vx, vy): + if all(path_clear(d2, s2, q[0], q[1], r[0], r[1], need) + for q, r in zip(route, route[1:])): + leg = (route, l); break + if leg: + break + if leg is None: + legs = None; break + legs.append(leg) + if legs is None: + continue + v = pcbnew.PCB_VIA(board) + v.SetPosition(pcbnew.VECTOR2I(int(vx * NM), int(vy * NM))) + v.SetWidth(int(0.55 * NM)); v.SetDrill(int(0.25 * NM)) + v.SetNetCode(code); v.SetViaType(pcbnew.VIATYPE_THROUGH) + board.Add(v) + added = [v] + for route, l in legs: + for q, r in zip(route, route[1:]): + t = pcbnew.PCB_TRACK(board) + t.SetStart(pcbnew.VECTOR2I(int(q[0] * NM), int(q[1] * NM))) + t.SetEnd(pcbnew.VECTOR2I(int(r[0] * NM), int(r[1] * NM))) + t.SetWidth(int(a.width * NM)); t.SetLayer(l) + t.SetNetCode(code); board.Add(t); added.append(t) + pcbnew.ZONE_FILLER(board).Fill(board.Zones()) + board.BuildConnectivity() + trial = tempfile.mktemp(suffix=".kicad_pcb") + if pro: + shutil.copy(pro, Path(trial).with_suffix(".kicad_pro")) + pcbnew.SaveBoard(trial, board) + v1, u1, _ = drc(trial) + if v1 <= v_now and u1 < u_now: + shutil.move(trial, str(work)) + print(f" HOP {name:9} {span:5.2f} mm via at " + f"({vx:.2f}, {vy:.2f}) -> {v1} violation(s), " + f"{u1} unconnected") + placed += 1; done = progressed = True + break + os.unlink(trial) + for t in added: + board.RemoveNative(t) + board.BuildConnectivity() + rejected += 1 + if done: + break + continue + for layer in shared: + discs, segs = obstacles_on(board, code, layer) + for path in candidates(ax, ay, bx, by): + if not all(path_clear(discs, segs, p[0], p[1], q[0], q[1], need) + for p, q in zip(path, path[1:])): + continue + added = [] + for p, q in zip(path, path[1:]): + t = pcbnew.PCB_TRACK(board) + t.SetStart(pcbnew.VECTOR2I(int(p[0] * NM), int(p[1] * NM))) + t.SetEnd(pcbnew.VECTOR2I(int(q[0] * NM), int(q[1] * NM))) + t.SetWidth(int(a.width * NM)); t.SetLayer(layer) + t.SetNetCode(code); board.Add(t); added.append(t) + pcbnew.ZONE_FILLER(board).Fill(board.Zones()) + board.BuildConnectivity() + trial = tempfile.mktemp(suffix=".kicad_pcb") + if pro: + shutil.copy(pro, Path(trial).with_suffix(".kicad_pro")) + pcbnew.SaveBoard(trial, board) + v1, u1, _ = drc(trial) + if v1 <= v_now and u1 < u_now: + shutil.move(trial, str(work)) + print(f" HOP {name:9} {span:5.2f} mm on " + f"{board.GetLayerName(layer):6} " + f"({len(path) - 1} seg) -> {v1} violation(s), " + f"{u1} unconnected") + placed += 1; done = progressed = True + break + os.unlink(trial) + for t in added: + board.RemoveNative(t) + board.BuildConnectivity() + rejected += 1 + if done: + break + if done: + break + if not progressed: + break + + vf, uf, data = drc(str(work)) + left = [e for e in data.get("unconnected_items", [])] + print(f"\n placed {placed} hop(s), {rejected} candidate(s) rejected by DRC") + print(f" result {v0} -> {vf} violation(s), {u0} -> {uf} unconnected") + print(f" wrote {work}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/make-pinmap.py b/hardware/courant/scripts/make-pinmap.py new file mode 100644 index 0000000..30e6013 --- /dev/null +++ b/hardware/courant/scripts/make-pinmap.py @@ -0,0 +1,11 @@ +"""Generate a lossless ball map from AMD's checked-in package file.""" +import json,re +from pathlib import Path +root=Path(__file__).resolve().parent.parent +pins=[] +for line in (root/'reference/xc7a35tftg256pkg.txt').read_text().splitlines(): + cols=line.split() + if cols and re.fullmatch(r'[A-HJ-NPRT](?:[1-9]|1[0-6])',cols[0]): + pins.append({'ball':cols[0],'function':cols[1],'bank':cols[3]}) +assert len(pins)==256 and len({p['ball'] for p in pins})==256 +(root/'fpga-pins.json').write_text(json.dumps(pins,indent=2)+'\n') diff --git a/hardware/courant/scripts/models3d.py b/hardware/courant/scripts/models3d.py new file mode 100644 index 0000000..33bb916 --- /dev/null +++ b/hardware/courant/scripts/models3d.py @@ -0,0 +1,191 @@ +#!/usr/bin/env python3 +""" +Attach KiCad 3D models to the board so it can be rendered as it will be built. + +tscircuit generates footprints with pads, courtyard and silkscreen but no +`(model ...)` reference, so KiCad's 3D viewer has nothing to place and renders +the board as bare lands. That is not wrong -- it is an accurate picture of the +fabricated PCB before assembly -- but it is not what the finished hardware +looks like. + +This maps each footprint name onto a body from KiCad's standard 3D library and +writes the reference in. Nothing electrical changes: models affect rendering +and mechanical checks only, never copper, DRC or fabrication output. + +The board this writes to is a render copy, not dist/courant.routed.kicad_pcb. +design.ts owns the placement and would drop these references on the next +export, so baking them into the routed board would quietly rot. + +Some mappings are the nearest standard body rather than the exact part -- the +regulator's QFN-16 and the optocoupler are approximations, noted below. They +are right to within a fraction of a millimetre and wrong only in the way a +photograph of a similar chip is wrong. + + python3 scripts/models3d.py BOARD --out OUT +""" +from __future__ import annotations + +import argparse, math, os, sys +from pathlib import Path + +sys.path.insert(0, str(Path(__file__).resolve().parent)) +from plane_escape import pcbnew + +LIB = Path("/usr/share/kicad/3dmodels") + +# footprint name -> library-relative model. Exact unless marked. +MAP = { + "resistor_res0603": "Resistor_SMD.3dshapes/R_0603_1608Metric.step", + "capacitor_cap0201": "Capacitor_SMD.3dshapes/C_0201_0603Metric.step", + "capacitor_cap0603": "Capacitor_SMD.3dshapes/C_0603_1608Metric.step", + "capacitor_cap0805": "Capacitor_SMD.3dshapes/C_0805_2012Metric.step", + "capacitor_cap1210": "Capacitor_SMD.3dshapes/C_1210_3225Metric.step", + # 17x17 mm, 16x16 balls on a 1.0 mm pitch: the FTG256 exactly. + "XC7A35T-1FTG256C": # footprint name kept from the pre-swap export + "Package_BGA.3dshapes/BGA-256_17.0x17.0mm_Layout16x16_P1.0mm" + "_Ball0.5mm_Pad0.4mm_NSMD.step", + "XC7A50T-1FTG256I": + "Package_BGA.3dshapes/BGA-256_17.0x17.0mm_Layout16x16_P1.0mm" + "_Ball0.5mm_Pad0.4mm_NSMD.step", + "W25Q64JVSSIQ": "Package_SO.3dshapes/JEITA_SOIC-8_3.9x4.9mm_P1.27mm.step", + "MCP6002-I_SN": "Package_SO.3dshapes/JEITA_SOIC-8_3.9x4.9mm_P1.27mm.step", + "MCP3208-CI_SL": "Package_SO.3dshapes/JEITA_SOIC-16_3.9x9.9mm_P1.27mm.step", + "PCM5102APWR": "Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.step", + "REF3125AIDBZR": "Package_TO_SOT_SMD.3dshapes/SOT-23.step", + "MCP6561T-E_OT": "Package_TO_SOT_SMD.3dshapes/SOT-23-5.step", + "BAT54S": "Package_TO_SOT_SMD.3dshapes/SOT-23.step", + "1N4148W": "Diode_SMD.3dshapes/D_SOD-123.step", + # U8's pads are 6 PTH on 7.62 mm rows at 2.54 mm pitch -- a plain DIP-6. + # The earlier choice here was the *socket* body, which is 3 mm taller than + # the part and would have been designed around. + "H11L1M": "Package_DIP.3dshapes/DIP-6_W7.62mm.step", + # The exact part the BOM specifies, not a stand-in: cjiang FNR4030S1R0MT, + # 4.0 x 4.0 x 3.0 mm. The earlier SRN4018 is the same footprint but 1.8 mm + # tall, which understates the height above the board by 1.2 mm. + "inductor": "Inductor_SMD.3dshapes/L_Changjiang_FNR4030S.step", + # Approximation: TPS62130 is RGT0016C with a 1.68 mm exposed pad against + # the library's 1.7 mm. Same body size; only the pad differs. + "TPS62130ARGTR": "Package_DFN_QFN.3dshapes/QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm.step", +} +# Oscillators share a body, matched by prefix. The board's 3.2 x 2.5 mm part +# has no library equivalent; this is the nearest 4-pin SMD can and renders a +# little small. +# Every connector on this board is a plain 0.1 inch through-hole header -- +# the panel-facing interface geometry -- so they are matched by shape rather than by name: +# through-hole pads on a 2.54 mm pitch, N of them, is a 1xN pin header. +# Naming each of the fifteen individually would need editing this file every +# time a header gains or loses a pin. +HEADER = "Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x%02d_P2.54mm_Vertical.step" + +PREFIX = { + "ASE-": "Oscillator.3dshapes/Oscillator_SMD_SeikoEpson_SG210-4Pin_2.5x2.0mm.step", +} + + +def local_pads(fp): + """Pad centres in the footprint's own unrotated frame, by pad number.""" + o = fp.GetPosition() + a = fp.GetOrientation().AsRadians() + ca, sa = math.cos(a), math.sin(a) + out = {} + for pad in fp.Pads(): + q = pad.GetPosition() + dx, dy = (q.x - o.x) / 1e6, (q.y - o.y) / 1e6 + out[pad.GetNumber()] = (dx * ca + dy * sa, -dx * sa + dy * ca) + return out + + +def header_for(fp, lib): + """A 1xN 0.1 inch header, plus the transform that lands it on the pads. + + KiCad's own header footprints put pin 1 at the origin with the row running + along +Y, and their model needs no offset or rotation because of it. These + footprints are generated by tscircuit: the row runs along X and is centred + on the origin instead. Attaching the model without correcting for that puts + every connector a half-body off and turned ninety degrees. + + The correction is derived from the pads rather than assumed, so a header + placed at any angle -- J1 sits at 90 -- comes out right. KiCad's model + offset is in a frame whose Y and Z-rotation are negated against the board's. + """ + pads = list(fp.Pads()) + if len(pads) < 2 or not all(p.GetAttribute() == pcbnew.PAD_ATTRIB_PTH + for p in pads): + return None + loc = local_pads(fp) + if "1" not in loc or "2" not in loc: + return None + gaps = sorted({round(math.dist(a, b), 2) + for i, a in enumerate(loc.values()) + for b in list(loc.values())[i + 1:]}) + if not gaps or abs(gaps[0] - 2.54) > 0.05: + return None + rel = HEADER % len(pads) + if not (lib / rel).is_file(): + return None + (x1, y1), (x2, y2) = loc["1"], loc["2"] + theta = math.degrees(math.atan2(y2 - y1, x2 - x1)) # row direction + # KiCad's stored model rotation turns the opposite way to the board frame, + # so this is +(theta - 90), not -. With the sign the other way the body's + # pin 1 still lands on pad 1 and every other pin runs off the far side -- + # which looks almost right and is completely wrong. + return rel, (x1, -y1, 0.0), (0.0, 0.0, theta - 90.0) + + +def main(): + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("board"); ap.add_argument("--out", required=True) + ap.add_argument("--lib", type=Path, default=LIB) + a = ap.parse_args() + + if not a.lib.is_dir() or not any(a.lib.iterdir()): + print(f" {a.lib} is empty -- install kicad-packages3d first") + return 1 + + board = pcbnew.LoadBoard(a.board) + placed = missing = skipped = 0 + absent: set = set() + for fp in board.GetFootprints(): + # Match on the value as well as the footprint name. A part-number + # change (the A35T -> A50T swap) updates the value while the footprint + # keeps whatever name the last export gave it, so keying on one alone + # silently drops the model for exactly the part you just changed. + name = fp.GetFPIDAsString().split(":")[-1].split("__", 1)[0] + rel = MAP.get(fp.GetValue()) or MAP.get(name) + if rel is None: + for pre, r in PREFIX.items(): + if name.startswith(pre): + rel = r; break + offset = rot = (0.0, 0.0, 0.0) + if rel is None: + hit = header_for(fp, a.lib) + if hit is not None: + rel, offset, rot = hit + if rel is None: + skipped += 1 + continue + path = a.lib / rel + if not path.is_file(): + absent.add(rel); missing += 1 + continue + m = pcbnew.FP_3DMODEL() + m.m_Filename = str(path) + m.m_Offset = pcbnew.VECTOR3D(*offset) + m.m_Rotation = pcbnew.VECTOR3D(*rot) + m.m_Scale = pcbnew.VECTOR3D(1.0, 1.0, 1.0) + m.m_Show = True + fp.Models().push_back(m) + placed += 1 + + pcbnew.SaveBoard(a.out, board) + print(f" attached {placed} model(s)") + print(f" no mapping {skipped} footprint(s) -- 12 thermal-via arrays, 4 mounting holes, 3 fiducials") + if absent: + print(f" not in lib {missing}: " + ", ".join(sorted(absent)[:4])) + print(f" wrote {a.out}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/netlist.py b/hardware/courant/scripts/netlist.py new file mode 100644 index 0000000..12a9df5 --- /dev/null +++ b/hardware/courant/scripts/netlist.py @@ -0,0 +1,95 @@ +#!/usr/bin/env python3 +""" +Write the netlist and the panel interface from the routed board. + +This board has no drawn schematic to export. It is defined in code -- design.ts +-- and tscircuit's schematic renderer produces an essentially blank sheet for +it (twenty text elements for two hundred components), so there is nothing +honest to ship under that name. The netlist below is the electrical definition +instead, and it is taken from the routed board rather than the source, which +makes it the authoritative record of what was actually fabricated. + +The panel interface table is the other half: every one of the fifteen headers +is a connection to hardware that is not on this PCB, and whoever builds the +front panel needs the pinout more than they need a drawing. + + python3 scripts/netlist.py BOARD --netlist OUT.txt --panel OUT.csv +""" +from __future__ import annotations + +import argparse, csv, re, sys +from collections import defaultdict +from pathlib import Path + +sys.path.insert(0, str(Path(__file__).resolve().parent)) +from plane_escape import pcbnew + +PANEL = { + "J1": "5 V DC input, externally fused", + "J2": "JTAG, to programmer", + "J3": "PROGRAM_B, momentary to GND forces reconfiguration", + "J4": "Reset, momentary to GND", + "J5": "Stereo line out, to panel jacks", + "J6": "Pitch potentiometer, panel mounted", + "J7": "Decay potentiometer, panel mounted", + "J8": "Timbre potentiometer, panel mounted", + "J9": "Rotary encoder with switch, panel mounted", + "J10": "Mode selector switch, panel mounted", + "J11": "Status LEDs x4, anodes -- series resistors are on-board", + "J12": "Pitch CV input jack, 0-5 V", + "J13": "Mod CV input jack, 0-5 V", + "J14": "Gate input jack", + "J15": "MIDI DIN socket, pins 4 and 5", +} + + +def main(): + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("board") + ap.add_argument("--netlist", required=True) + ap.add_argument("--panel", required=True) + a = ap.parse_args() + + board = pcbnew.LoadBoard(a.board) + nets = defaultdict(list) + for fp in board.GetFootprints(): + for pad in fp.Pads(): + if pad.GetNetname(): + nets[pad.GetNetname()].append( + (fp.GetReference(), pad.GetNumber())) + + def key(r): + m = re.match(r"([A-Za-z]+)(\d+)", r[0]) + return (m.group(1), int(m.group(2)), r[1]) if m else (r[0], 0, r[1]) + + with open(a.netlist, "w") as f: + f.write("Courant Rev A -- netlist, extracted from the routed board\n") + f.write(f"{len(nets)} nets, " + f"{sum(len(v) for v in nets.values())} connections\n\n") + for name in sorted(nets): + pads = sorted(nets[name], key=key) + f.write(f"{name} ({len(pads)})\n") + for ref, num in pads: + f.write(f" {ref}.{num}\n") + f.write("\n") + + rows = [] + for ref, purpose in PANEL.items(): + fp = board.FindFootprintByReference(ref) + if fp is None: + continue + for pad in sorted(fp.Pads(), key=lambda p: int(p.GetNumber())): + rows.append({"Connector": ref, "Pin": pad.GetNumber(), + "Net": pad.GetNetname(), "Purpose": purpose}) + with open(a.panel, "w", newline="") as f: + w = csv.DictWriter(f, fieldnames=["Connector", "Pin", "Net", "Purpose"]) + w.writeheader(); w.writerows(rows) + + print(f" netlist {len(nets)} nets -> {a.netlist}") + print(f" panel {len(rows)} pins on {len(PANEL)} headers -> {a.panel}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/nudge.py b/hardware/courant/scripts/nudge.py new file mode 100644 index 0000000..8d27a6f --- /dev/null +++ b/hardware/courant/scripts/nudge.py @@ -0,0 +1,117 @@ +#!/usr/bin/env python3 +""" +Move a capacitor a fraction of a millimetre so its neighbour can connect. + +Under a 1.0 mm BGA the thing that blocks a connection is often not other +routing but a capacitor's own opposite land: a 0201 at 45 degrees puts its +second pad 0.66 mm from its first, and a trace leaving the first pad has to +pass within 0.25 mm of the second. Twenty micrometres decides it, and no +router can help because routers do not move components. + +This tries small offsets of the named footprint -- eight directions, growing +radius -- and after each one asks scripts/hop.py's placement search whether the +connection can now be made. The first offset that produces a DRC-clean board +with fewer unconnected pairs wins; everything else is rolled back. + +Only footprints with no copper attached are safe to move this way, and the +script refuses otherwise: moving a pad out from under its own trace trades one +broken connection for another. + + python3 scripts/nudge.py BOARD --out OUT --ref C107 [--ref C134] +""" +from __future__ import annotations + +if __name__ == "__main__": + from pathlib import Path as _NativePath + if (_NativePath(__file__).resolve().parents[1]/"NATIVE_BASELINE.json").exists(): + raise SystemExit('Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.') + + +import argparse, math, os, shutil, subprocess, sys, tempfile +from pathlib import Path + +sys.path.insert(0, str(Path(__file__).resolve().parent)) +from plane_escape import pcbnew, NM, drc + +HOP = Path(__file__).resolve().parent / "hop.py" + + +def attached(board, fp): + lands = {(p.GetPosition().x, p.GetPosition().y) for p in fp.Pads()} + return sum(1 for t in board.GetTracks() if t.Type() == pcbnew.PCB_TRACE_T + and any((q.x, q.y) in lands for q in (t.GetStart(), t.GetEnd()))) + + +def offsets(step, rings): + for r in range(1, rings + 1): + for k in range(8): + a = k * math.pi / 4 + yield round(math.cos(a) * step * r, 4), round(math.sin(a) * step * r, 4) + + +def main(): + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("board"); ap.add_argument("--out", required=True) + ap.add_argument("--ref", action="append", required=True) + ap.add_argument("--step", type=float, default=0.15) + ap.add_argument("--rings", type=int, default=3) + a = ap.parse_args() + + work = Path(a.out) + shutil.copy(a.board, work) + pro = Path(a.board).with_suffix(".kicad_pro") + pro = str(pro) if pro.is_file() else None + if pro: + shutil.copy(pro, work.with_suffix(".kicad_pro")) + + v0, u0, _ = drc(str(work)) + print(f" start {v0} violation(s), {u0} unconnected pair(s)\n") + + for ref in a.ref: + board = pcbnew.LoadBoard(str(work)) + fp = board.FindFootprintByReference(ref) + if fp is None: + print(f" {ref:6} no such footprint"); continue + n = attached(board, fp) + if n: + print(f" {ref:6} REFUSED: {n} segment(s) attached; moving it would " + f"break them"); continue + home = fp.GetPosition() + best = None + for dx, dy in offsets(a.step, a.rings): + board = pcbnew.LoadBoard(str(work)) + fp = board.FindFootprintByReference(ref) + fp.SetPosition(pcbnew.VECTOR2I(int(home.x + dx * NM), + int(home.y + dy * NM))) + pcbnew.ZONE_FILLER(board).Fill(board.Zones()); board.BuildConnectivity() + moved = tempfile.mktemp(suffix=".kicad_pcb") + if pro: + shutil.copy(pro, Path(moved).with_suffix(".kicad_pro")) + pcbnew.SaveBoard(moved, board) + out = tempfile.mktemp(suffix=".kicad_pcb") + r = subprocess.run([sys.executable, str(HOP), moved, "--out", out], + capture_output=True, text=True) + if not os.path.exists(out): + os.unlink(moved); continue + v1, u1, _ = drc(out) + os.unlink(moved) + if v1 <= v0 and u1 < u0: + print(f" {ref:6} moved ({dx:+.2f}, {dy:+.2f}) mm -> " + f"{v1} violation(s), {u1} unconnected") + shutil.move(out, str(work)) + v0, u0 = v1, u1 + best = (dx, dy) + break + os.unlink(out) + if best is None: + print(f" {ref:6} no offset within {a.step * a.rings:.2f} mm helped") + + vf, uf, _ = drc(str(work)) + print(f"\n result {vf} violation(s), {uf} unconnected pair(s)") + print(f" wrote {work}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/plane_escape.py b/hardware/courant/scripts/plane_escape.py new file mode 100644 index 0000000..2947b7b --- /dev/null +++ b/hardware/courant/scripts/plane_escape.py @@ -0,0 +1,430 @@ +#!/usr/bin/env python3 +""" +Open a BGA escape slot by returning plane-backed copper to its plane. + +The five connections this board could not finish are not blocked by signal +traffic that a shove router would move aside. They are blocked by power routed +as *traces* across F.Cu and B.Cu inside U1's ball field -- 356 mm of it, of +which 262 mm is GND or V3V3 and therefore has a plane it could have used +instead. Freerouting daisy-chained the back-side decoupling capacitors along +the outer layers rather than dropping each one onto In1/In4 (GND) or In3 +(V3V3), and those chains run straight through the diagonal slots the remaining +balls need for their dog-bone vias. + +So: delete the plane-backed copper that occupies a slot, give whatever it +orphaned its own via into the plane, and the slot opens. This is strictly +better decoupling as well -- a cap that reaches its plane through a via at its +own pad has a shorter return loop than one chained to three neighbours. + +Nothing here is accepted on faith. Every step writes a trial board, runs +KiCad's DRC over it, and keeps the result only if the unconnected count falls +and the violation count does not rise. + + python3 scripts/plane_escape.py BOARD --out OUT [--net NET ...] +""" +from __future__ import annotations + +if __name__ == "__main__": + from pathlib import Path as _NativePath + if (_NativePath(__file__).resolve().parents[1]/"NATIVE_BASELINE.json").exists(): + raise SystemExit('Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.') + + +import argparse, json, math, os, re, shutil, subprocess, tempfile +from pathlib import Path + + +def load_pcbnew(): + import importlib + saved, devnull = os.dup(2), os.open(os.devnull, os.O_WRONLY) + try: + os.dup2(devnull, 2) + return importlib.import_module("pcbnew") + finally: + os.dup2(saved, 2); os.close(saved); os.close(devnull) + + +pcbnew = load_pcbnew() +NM = 1_000_000 + +# Nets that have a plane to fall back into, and may therefore have their +# outer-layer copper deleted: the via that replaces it reaches the same net. +PLANE_NETS = {"GND", "V3V3"} + + +def drc(path): + o = tempfile.mktemp(suffix=".json") + subprocess.run(["kicad-cli", "pcb", "drc", "--output", o, "--format", "json", + "--units", "mm", "--severity-error", "--refill-zones", path], + capture_output=True, text=True) + j = json.load(open(o)); os.unlink(o) + return len(j.get("violations", [])), len(j.get("unconnected_items", [])), j + + +def seg_dist(px, py, x1, y1, x2, y2): + dx, dy = x2 - x1, y2 - y1 + L = dx * dx + dy * dy + t = 0 if L == 0 else max(0.0, min(1.0, ((px - x1) * dx + (py - y1) * dy) / L)) + return math.hypot(px - (x1 + t * dx), py - (y1 + t * dy)) + + +def obstacles(board, netcode): + """Foreign copper, as discs and segments, keyed by nothing: a through via + crosses every layer, so a via slot must be clear on all of them at once.""" + discs, segs = [], [] + for t in board.GetTracks(): + if t.GetNetCode() == netcode: + continue + if isinstance(t, pcbnew.PCB_VIA): + p = t.GetPosition() + discs.append((p.x / NM, p.y / NM, t.GetWidth(pcbnew.F_Cu) / 2 / NM)) + else: + s, e = t.GetStart(), t.GetEnd() + segs.append((s.x / NM, s.y / NM, e.x / NM, e.y / NM, t.GetWidth() / 2 / NM)) + for fp in board.GetFootprints(): + for pad in fp.Pads(): + if pad.GetNetCode() == netcode: + continue + p, sz = pad.GetPosition(), pad.GetSize() + discs.append((p.x / NM, p.y / NM, max(sz.x, sz.y) / 2 / NM)) + return discs, segs + + +def obstacles_on(board, netcode, layer): + """Foreign copper a *trace* on LAYER must avoid. Unlike a via this is a + single-layer question, except for through vias, which are on every layer.""" + discs, segs = [], [] + for t in board.GetTracks(): + if t.GetNetCode() == netcode: + continue + if isinstance(t, pcbnew.PCB_VIA): + p = t.GetPosition() + discs.append((p.x / NM, p.y / NM, t.GetWidth(pcbnew.F_Cu) / 2 / NM)) + elif t.GetLayer() == layer: + a, b = t.GetStart(), t.GetEnd() + segs.append((a.x / NM, a.y / NM, b.x / NM, b.y / NM, t.GetWidth() / 2 / NM)) + for fp in board.GetFootprints(): + for pad in fp.Pads(): + if pad.GetNetCode() == netcode or not pad.IsOnLayer(layer): + continue + p, sz = pad.GetPosition(), pad.GetSize() + discs.append((p.x / NM, p.y / NM, max(sz.x, sz.y) / 2 / NM)) + return discs, segs + + +def same_net_points(board, netcode, layer): + """Where a trace on LAYER could join this net without a via.""" + out = [] + for t in board.GetTracks(): + if t.GetNetCode() != netcode: + continue + if isinstance(t, pcbnew.PCB_VIA): + p = t.GetPosition(); out.append((p.x / NM, p.y / NM)) + elif t.GetLayer() == layer: + for p in (t.GetStart(), t.GetEnd()): + out.append((p.x / NM, p.y / NM)) + for fp in board.GetFootprints(): + for pad in fp.Pads(): + if pad.GetNetCode() == netcode and pad.IsOnLayer(layer): + p = pad.GetPosition(); out.append((p.x / NM, p.y / NM)) + return out + + +def path_clear(discs, segs, ax, ay, bx, by, need, reserved=(), step=0.05): + n = max(1, int(math.hypot(bx - ax, by - ay) / step)) + for i in range(n + 1): + t = i / n + if not clear_at(discs, segs, ax + t * (bx - ax), ay + t * (by - ay), + need, reserved): + return False + return True + + +def find_link(board, netcode, ax, ay, layer, need, reach, reserved=()): + """Nearest point of this net that a clear straight trace can reach on LAYER. + + A ball whose only via slot has been given to a neighbour does not have to + have a via of its own -- it only has to reach copper that already does. + """ + discs, segs = obstacles_on(board, netcode, layer) + best = None + for bx, by in same_net_points(board, netcode, layer): + d = math.hypot(bx - ax, by - ay) + if d < 1e-3 or d > reach or (best and d >= best[0]): + continue + if path_clear(discs, segs, ax, ay, bx, by, need, reserved): + best = (d, bx, by) + return best + + +def clear_at(discs, segs, px, py, need, reserved=()): + # A slot being freed for an escape must not be handed straight back to the + # net whose copper was just removed from it -- which is exactly what the + # nearest-clear-point search does if nothing forbids it. + for x, y, r in reserved: + if math.hypot(px - x, py - y) < r: + return False + for x, y, r in discs: + if math.hypot(px - x, py - y) < r + need: + return False + for x1, y1, x2, y2, r in segs: + if seg_dist(px, py, x1, y1, x2, y2) < r + need: + return False + return True + + +def find_slot(discs, segs, ax, ay, need, reach, reserved=(), step=0.05): + """Nearest point to (ax, ay) that a through via can occupy.""" + best = None + n = int(reach / step) + for i in range(-n, n + 1): + for j in range(-n, n + 1): + px, py = ax + i * step, ay + j * step + d = math.hypot(px - ax, py - ay) + if d > reach or (best and d >= best[0]): + continue + if clear_at(discs, segs, px, py, need, reserved): + best = (d, px, py) + return best + + +def blockers_at(board, netcode, sx, sy, need, rip_any=False): + """Copper that stops a via at (sx, sy), split by whether it can be deleted. + + With rip_any, any track or via may go and be re-routed afterwards; a pad + never can, because moving a component is not the router's to do. + """ + plane, fixed = [], [] + for t in board.GetTracks(): + if t.GetNetCode() == netcode: + continue + if isinstance(t, pcbnew.PCB_VIA): + p = t.GetPosition() + d = math.hypot(p.x / NM - sx, p.y / NM - sy) - t.GetWidth(pcbnew.F_Cu) / 2 / NM + else: + s, e = t.GetStart(), t.GetEnd() + d = seg_dist(sx, sy, s.x / NM, s.y / NM, e.x / NM, e.y / NM) - t.GetWidth() / 2 / NM + if d >= need: + continue + (plane if (rip_any or t.GetNetname() in PLANE_NETS) else fixed).append(t) + for fp in board.GetFootprints(): + for pad in fp.Pads(): + if pad.GetNetCode() == netcode: + continue + p, sz = pad.GetPosition(), pad.GetSize() + if math.hypot(p.x / NM - sx, p.y / NM - sy) < max(sz.x, sz.y) / 2 / NM + need: + fixed.append(pad) # a pad is never ours to delete + return plane, fixed + + +def item_layer(board, uuid, fallback): + """The copper layer an item lives on -- a stub must not be drawn anywhere else.""" + for t in board.GetTracks(): + if t.m_Uuid.AsString() == uuid: + return fallback if isinstance(t, pcbnew.PCB_VIA) else t.GetLayer() + for fp in board.GetFootprints(): + for pad in fp.Pads(): + if pad.m_Uuid.AsString() == uuid: + return pcbnew.B_Cu if pad.IsOnLayer(pcbnew.B_Cu) else pcbnew.F_Cu + return fallback + + +def repair(board, pro, need, reach, width, via, drill, reserved=(), + prefer="via", verbose=True): + """Give every plane-net item the deletion orphaned its own via into the plane. + + A through via on GND lands on In1 and In4; on V3V3 it lands on In3. Both + pours cover the whole board, so the via alone restores the connection and + the search only has to reach from the orphan, not between two endpoints. + """ + added, done = 0, set() + baseline, last = None, None + while True: + trial = tempfile.mktemp(suffix=".kicad_pcb") + if pro: shutil.copy(pro, Path(trial).with_suffix(".kicad_pro")) + pcbnew.ZONE_FILLER(board).Fill(board.Zones()); board.BuildConnectivity() + pcbnew.SaveBoard(trial, board) + v_now, _, data = drc(trial) + os.unlink(trial) + + # Undo one placement at a time rather than judging the batch at the + # end: a single link that breaks a clearance would otherwise discard + # every good one made alongside it. + if baseline is None: + baseline = v_now + elif v_now > baseline and last is not None: + key, items = last + for it in items: + board.RemoveNative(it) + board.BuildConnectivity() + if verbose: + print(f" undo {key[0]} at ({key[1]}, {key[2]}): " + f"+{v_now - baseline} violation(s)") + added -= 1; last = None + continue + last = None + # KiCad's DRC JSON leaves "net" null on unconnected items and puts the + # net name in the description instead: 'Track [GND] on B.Cu, ...'. + todo = [] + for e in data.get("unconnected_items", []): + for it in e.get("items", []): + m = re.search(r"\[([^\]]+)\]", it.get("description", "")) + if m and m.group(1) in PLANE_NETS: + todo.append((m.group(1), it)) + if not todo: + return added + placed = False + for name, it in todo: + key = (name, round(it["pos"]["x"], 3), round(it["pos"]["y"], 3)) + if key in done: + continue + ax, ay = it["pos"]["x"], it["pos"]["y"] + code = board.GetNetsByName()[name].GetNetCode() + layer = item_layer(board, it["uuid"], pcbnew.B_Cu) + discs, segs = obstacles(board, code) + slot = find_slot(discs, segs, ax, ay, need, reach, reserved) + link = find_link(board, code, ax, ay, layer, + width / 2 + (need - via / 2), reach, reserved) + # A via is the shorter return path and the better connection, but + # vias are the scarce resource here: 225 interior slots less the 38 + # the capacitor array occupies is 187, against 36 signal escapes, + # 76 power ball vias and 76 capacitor lands -- 188 wanted. Spending + # one per land does not fit and strands the lands that come last. + # With prefer="link" a land joins its neighbour's copper instead and + # the group shares a via, which is what the original routing did. + if prefer == "link" and link is not None: + slot = None + if slot is None and link is None: + if verbose: + print(f" {name:5} orphan at ({ax:.3f}, {ay:.3f}) on " + f"{board.GetLayerName(layer)}: no slot, no link") + continue + done.add(key) + placed_items = [] + if slot is not None: + _, vx, vy = slot + v = pcbnew.PCB_VIA(board) + v.SetPosition(pcbnew.VECTOR2I(int(vx * NM), int(vy * NM))) + v.SetWidth(int(via * NM)); v.SetDrill(int(drill * NM)) + v.SetNetCode(code); v.SetViaType(pcbnew.VIATYPE_THROUGH) + board.Add(v); placed_items.append(v) + how = f"via ({vx:.3f}, {vy:.3f})" + else: + _, vx, vy = link + how = f"link ({vx:.3f}, {vy:.3f})" + if math.hypot(vx - ax, vy - ay) > 1e-3: + t = pcbnew.PCB_TRACK(board) + t.SetStart(pcbnew.VECTOR2I(int(ax * NM), int(ay * NM))) + t.SetEnd(pcbnew.VECTOR2I(int(vx * NM), int(vy * NM))) + t.SetWidth(int(width * NM)); t.SetLayer(layer) + t.SetNetCode(code); board.Add(t); placed_items.append(t) + last = (key, placed_items) + if verbose: + print(f" {name:5} orphan at ({ax:.3f}, {ay:.3f}) -> {how}" + f" on {board.GetLayerName(layer)}") + added += 1; placed = True + break + if not placed: + return added + + +def escape(board, pro, net, need, reach, width, via, drill, + rip_any=False, do_repair=True): + """Free the best diagonal slot beside NET's ball and put its dog-bone in.""" + u1 = board.FindFootprintByReference("U1") + pad = next((p for p in u1.Pads() if p.GetNetname() == net), None) + if pad is None: + print(f" {net:14} no such ball on U1"); return None + c = pad.GetPosition(); bx, by = c.x / NM, c.y / NM + code = pad.GetNetCode() + + # Only the four adjacent diagonal slots are reachable: a clear slot further + # out is useless because the straight line to it crosses another ball. + cands = [] + for dx in (-1, 1): + for dy in (-1, 1): + sx, sy = bx + dx * 0.5, by + dy * 0.5 + plane, fixed = blockers_at(board, code, sx, sy, need, rip_any) + cands.append((len(fixed), len(plane), sx, sy, plane)) + cands.sort() + nfixed, nplane, sx, sy, plane = cands[0] + if nfixed: + print(f" {net:14} best slot ({sx:.1f}, {sy:.1f}) still has {nfixed} " + f"immovable blocker(s) -- skipping") + return None + + gone = ", ".join(sorted({t.GetNetname() for t in plane})) or "nothing" + print(f" {net:14} slot ({sx:.1f}, {sy:.1f}): ripping {nplane} item(s) [{gone}]") + for t in plane: + board.RemoveNative(t) + if do_repair: + repair(board, pro, need, reach, width, via, drill, + reserved=[(sx, sy, via / 2 + need)]) + + v = pcbnew.PCB_VIA(board) + v.SetPosition(pcbnew.VECTOR2I(int(sx * NM), int(sy * NM))) + v.SetWidth(int(via * NM)); v.SetDrill(int(drill * NM)) + v.SetNetCode(code); v.SetViaType(pcbnew.VIATYPE_THROUGH); board.Add(v) + t = pcbnew.PCB_TRACK(board) + t.SetStart(c); t.SetEnd(pcbnew.VECTOR2I(int(sx * NM), int(sy * NM))) + t.SetWidth(int(width * NM)); t.SetLayer(pcbnew.F_Cu) + t.SetNetCode(code); board.Add(t) + pcbnew.ZONE_FILLER(board).Fill(board.Zones()); board.BuildConnectivity() + return (sx, sy) + + +def main(): + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("board"); ap.add_argument("--out", required=True) + ap.add_argument("--net", action="append", required=True) + ap.add_argument("--reach", type=float, default=1.5) + ap.add_argument("--clearance", type=float, default=0.15) + ap.add_argument("--via", type=float, default=0.55) + ap.add_argument("--drill", type=float, default=0.25) + ap.add_argument("--width", type=float, default=0.2) + ap.add_argument("--rip-any", action="store_true", + help="rip any track or via out of the slot, not only nets " + "with a plane to fall back into") + ap.add_argument("--no-repair", action="store_true", + help="do not re-connect what was ripped; leave it to the router") + a = ap.parse_args() + + work = Path(a.out) + shutil.copy(a.board, work) + pro = Path(a.board).with_suffix(".kicad_pro") + pro = str(pro) if pro.is_file() else None + if pro: shutil.copy(pro, work.with_suffix(".kicad_pro")) + + need = a.via / 2 + a.clearance + v0, u0, _ = drc(str(work)) + print(f" start {v0} violation(s), {u0} unconnected\n") + + kept = [] + for net in a.net: + board = pcbnew.LoadBoard(str(work)) + if escape(board, pro, net, need, a.reach, a.width, a.via, a.drill, + a.rip_any, not a.no_repair) is None: + continue + trial = tempfile.mktemp(suffix=".kicad_pcb") + if pro: shutil.copy(pro, Path(trial).with_suffix(".kicad_pro")) + pcbnew.SaveBoard(trial, board) + v1, u1, _ = drc(trial) + vn, un, _ = drc(str(work)) + if v1 <= vn and (u1 <= un or a.no_repair): + shutil.move(trial, str(work)) + print(f" {net:14} KEPT -> {v1} violation(s), {u1} unconnected\n") + kept.append(net) + else: + os.unlink(trial) + print(f" {net:14} REVERTED ({v1} violation(s), {u1} unconnected)\n") + + vf, uf, _ = drc(str(work)) + print(f" result {len(kept)} escaped: {', '.join(kept) or 'none'}") + print(f" {v0} -> {vf} violation(s), {u0} -> {uf} unconnected") + print(f" wrote {work}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/power.py b/hardware/courant/scripts/power.py new file mode 100644 index 0000000..36bafa7 --- /dev/null +++ b/hardware/courant/scripts/power.py @@ -0,0 +1,85 @@ +#!/usr/bin/env python3 +""" +Power budget for the 5 V input, computed from the board's own rail loading. + +This is a budget, not a measurement. Every line is a datasheet or engineering +figure with its basis stated, given as a low/high pair rather than a single +number, because the only honest answer before a board exists is a range. The +question it settles is whether a Eurorack case's +5 V rail can run this: the +source specifies "5 V / 3 A", which is headroom rather than draw, and 3 A would +exclude most cases. + +FPGA dynamic power is the term nobody can pin down without a synthesis run and +a switching activity file; the range below is deliberately wide at that line. + + python3 scripts/power.py +""" +from __future__ import annotations + +if __name__ == "__main__": + from pathlib import Path as _NativePath + if (_NativePath(__file__).resolve().parents[1]/"NATIVE_BASELINE.json").exists(): + raise SystemExit('Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.') + + +# rail, part, low mA, high mA, basis +LOADS = [ + ("V1 (1.0 V)", "U1 VCCINT, 9 pins", 150, 600, + "A50T static ~40 mA; the rest is the FDTD mesh and voices at 100 MHz. " + "Widest term in the budget -- needs synthesis + activity to narrow"), + ("V1V8 (1.8 V)", "U1 VCCAUX/VCCBRAM, 5 pins", 30, 80, + "VCCAUX ~25 mA static; BRAM adds with mesh size"), + ("V3V3 (3.3 V)", "U1 VCCO, 24 pins / 36 I/O", 20, 50, + "LVCMOS33 into short traces, I2S and SPI at a few MHz"), + ("V3V3 (3.3 V)", "Y1 100 MHz oscillator", 25, 40, "ASE series at 3.3 V"), + ("V3V3 (3.3 V)", "Y2 12.288 MHz oscillator", 5, 15, "ASE series, stock data 5-10 mA"), + ("V3V3 (3.3 V)", "U3 PCM5102A DAC", 18, 25, "datasheet typical, playing"), + ("V3V3 (3.3 V)", "U8 H11L1M optocoupler", 0, 10, + "LED current only while MIDI is arriving; 0 when idle"), + ("V3V3 (3.3 V)", "J11 status LEDs x4", 0, 6, + "1 kOhm series, ~1.3 mA each, all four lit"), + ("V3V3 (3.3 V)", "U2 W25Q64 flash", 1, 5, + "idle after configuration; 4 mA while reading"), + ("V3V3 (3.3 V)", "U4 MCP3208 ADC", 1, 1, "500 uA typical active"), + ("V3V3 (3.3 V)", "U5 REF3125 + divider load", 1, 2, + "300 uA quiescent plus pot and CV divider current"), + ("V3V3 (3.3 V)", "U6 MCP6002, U7 MCP6561", 1, 1, "~100 uA each"), +] +RAIL_V = {"V1 (1.0 V)": 1.0, "V1V8 (1.8 V)": 1.8, "V3V3 (3.3 V)": 3.3} +EFF = (0.90, 0.85) # TPS62130 efficiency, best and worst case here +VIN = 5.0 + + +def main(): + per_rail: dict = {} + print(" load mA low mA high") + for rail, part, lo, hi, _ in LOADS: + a, b = per_rail.get(rail, (0, 0)) + per_rail[rail] = (a + lo, b + hi) + print(f" {rail:14} {part:28} {lo:6} {hi:7}") + + print("\n rail totals") + out_lo = out_hi = 0.0 + for rail, (lo, hi) in per_rail.items(): + v = RAIL_V[rail] + out_lo += v * lo / 1000 + out_hi += v * hi / 1000 + print(f" {rail:14} {lo:4}-{hi:4} mA {v * lo / 1000:.3f}-{v * hi / 1000:.3f} W") + + print(f"\n output power {out_lo:.2f} - {out_hi:.2f} W") + in_lo = out_lo / EFF[0] + in_hi = out_hi / EFF[1] + print(f" input power at {EFF[1]:.0%}-{EFF[0]:.0%} {in_lo:.2f} - {in_hi:.2f} W") + print(f" input current at {VIN:.0f} V {in_lo / VIN * 1000:.0f} - " + f"{in_hi / VIN * 1000:.0f} mA") + print(f"\n source specifies 3000 mA -- that is " + f"{3000 / (in_hi / VIN * 1000):.0f}x the worst case here, i.e. headroom") + print(" Eurorack +5 V rails commonly supply 500-1500 mA: comfortable either way.") + print("\n NOT INCLUDED: inrush. The bulk capacitance is a few hundred uF and the") + print(" TPS62130 soft-start capacitors (3.3 nF) set the ramp; a case's current") + print(" limit sees that, not the steady state.") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/reland_decaps.py b/hardware/courant/scripts/reland_decaps.py new file mode 100644 index 0000000..9b22017 --- /dev/null +++ b/hardware/courant/scripts/reland_decaps.py @@ -0,0 +1,200 @@ +#!/usr/bin/env python3 +""" +Re-land the back-side decoupling array on the already-routed board. + +The array under U1 was 0402, centred on the ball grid. A dog-bone escape via +needs 0.275 mm of barrel plus 0.15 mm of clearance, and the diagonal slot it +occupies is 0.707 mm from four balls of 0.25 mm radius -- 0.032 mm of slack +before anything else is placed. A capacitor centred on a ball aims both lands +at that ball's four slots and blocks all of them, which is why ten of the +twenty slots the last five connections needed were unusable and why no router, +interactive or otherwise, could finish them. + +design.ts now places the same capacitors as 0201, offset half a pitch +diagonally so each sits on a *slot* rather than on a ball, and turned 45 +degrees so its lands point along the diagonal at the two balls it straddles. +Each capacitor then consumes exactly one slot instead of four -- 38 slot-kills +across the array rather than 152 -- and leaves its neighbours 0.528 mm clear +against the 0.425 mm requirement. + +This script moves that change onto the routed board without re-routing it. +Each land travels about 0.77 mm, so the 92 segments that terminate on one +cannot simply be stretched after it; they are deleted. Of those, 75 are GND +and V3V3 daisy-chains -- the outer-layer copper Freerouting wove through the +ball field instead of dropping each capacitor onto the planes already sitting +under it. Every one of them is replaced by a via into its own plane at its own +pad, which is both the fix for the slots and a shorter return loop than the +chain it replaces. The remaining 17 are V1 and V1V8, which have no plane and +are left unrouted for a person to finish. + +The other 1724 segments are untouched. + + python3 scripts/reland_decaps.py ROUTED --from FRESH --out OUT + +FRESH is the board design.ts exports (new lands, no copper); ROUTED carries the +routing. Net codes differ between the two boards -- 94 of 97 on this one -- so +every transplanted pad is re-bound to its net by name, never by number. +""" +from __future__ import annotations + +if __name__ == "__main__": + from pathlib import Path as _NativePath + if (_NativePath(__file__).resolve().parents[1]/"NATIVE_BASELINE.json").exists(): + raise SystemExit('Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.') + + +import argparse, json, os, re, shutil, subprocess, sys, tempfile +from pathlib import Path + +sys.path.insert(0, str(Path(__file__).resolve().parent)) +from plane_escape import (pcbnew, NM, drc, obstacles, find_slot, find_link, + item_layer, repair, PLANE_NETS) + + +def main(): + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("routed") + ap.add_argument("--from", dest="fresh", required=True) + ap.add_argument("--out", required=True) + ap.add_argument("--refs", default="C100-C137") + ap.add_argument("--reach", type=float, default=1.2) + ap.add_argument("--clearance", type=float, default=0.15) + ap.add_argument("--via", type=float, default=0.55) + ap.add_argument("--drill", type=float, default=0.25) + ap.add_argument("--width", type=float, default=0.25) + ap.add_argument("--no-repair", action="store_true", + help="leave the capacitor lands unconnected. A via per land " + "does not fit: 225 interior slots less 38 the array now " + "occupies is 187, against 36 signal escapes + 76 power " + "ball vias + 76 capacitor lands = 188 wanted. Vias have " + "to be shared, so the escapes are placed first and the " + "router re-shares the rest around them.") + a = ap.parse_args() + + m = re.fullmatch(r"([A-Za-z]+)(\d+)-\1(\d+)", a.refs) + refs = {f"{m.group(1)}{i}" for i in range(int(m.group(2)), int(m.group(3)) + 1)} + + work = Path(a.out) + shutil.copy(a.routed, work) + pro = Path(a.routed).with_suffix(".kicad_pro") + pro = str(pro) if pro.is_file() else None + if pro: + shutil.copy(pro, work.with_suffix(".kicad_pro")) + + v0, u0, _ = drc(str(work)) + print(f" start {v0} violation(s), {u0} unconnected") + + fresh = pcbnew.LoadBoard(a.fresh) + board = pcbnew.LoadBoard(str(work)) + by_name = {n.GetNetname(): n.GetNetCode() + for n in board.GetNetInfo().NetsByNetcode().values()} + + have_fresh = {f.GetReference() for f in fresh.GetFootprints()} & refs + have_rt = {f.GetReference() for f in board.GetFootprints()} & refs + if have_fresh != refs or have_rt != refs: + print(f" ABORT refs missing: fresh {sorted(refs - have_fresh)[:3]} " + f"routed {sorted(refs - have_rt)[:3]}") + return 1 + + # Land positions as they are *now*, so the copper that ends on one can be + # found before the footprint moves out from under it. + lands = set() + for fp in board.GetFootprints(): + if fp.GetReference() in refs: + for pad in fp.Pads(): + p = pad.GetPosition(); lands.add((p.x, p.y)) + + doomed = [] + for t in board.GetTracks(): + if isinstance(t, pcbnew.PCB_VIA): + continue + if any((p.x, p.y) in lands for p in (t.GetStart(), t.GetEnd())): + doomed.append(t) + by_net = {} + for t in doomed: + by_net[t.GetNetname()] = by_net.get(t.GetNetname(), 0) + 1 + print(f" delete {len(doomed)} segment(s) landing on the old array: " + + ", ".join(f"{k} {v}" for k, v in sorted(by_net.items(), key=lambda x: -x[1]))) + for t in doomed: + board.RemoveNative(t) + + # Swap the footprints wholesale. Pad positions live relative to the + # footprint in the board file, and pcbnew exposes no setter for that, so a + # pad cannot be moved in place -- the footprint has to be replaced. + swapped = 0 + for old in [f for f in board.GetFootprints() if f.GetReference() in refs]: + src = fresh.FindFootprintByReference(old.GetReference()) + nets = {pad.GetNumber(): pad.GetNetname() for pad in old.Pads()} + board.RemoveNative(old) + new = pcbnew.Cast_to_FOOTPRINT(src.Duplicate(False)) + board.Add(new) + for pad in new.Pads(): + name = nets.get(pad.GetNumber()) + if name in by_name: + pad.SetNetCode(by_name[name]) + swapped += 1 + print(f" transplant {swapped} footprint(s) re-landed as 0201 at 45 deg") + + pcbnew.ZONE_FILLER(board).Fill(board.Zones()); board.BuildConnectivity() + + def save(b): + t = tempfile.mktemp(suffix=".kicad_pcb") + if pro: + shutil.copy(pro, Path(t).with_suffix(".kicad_pro")) + pcbnew.SaveBoard(t, b) + return t + + # The lands moved 0.77 mm, so some of them now sit on copper that used to + # route around where they were. All of it is ripped up rather than dodged -- + # not only the GND and V3V3 that has a plane to fall back into, but the V1 + # and V1V8 rails and the handful of signals caught in the array as well. + # Whatever this disconnects is re-routed afterwards; leaving a short in + # place to save the router some work is not a trade worth making. + for _ in range(12): + t = save(board) + _, _, data = drc(t); os.unlink(t) + hits = {} + for v in data.get("violations", []): + desc = [i.get("description", "") for i in v.get("items", [])] + if not any(re.search(r"of (" + "|".join(sorted(refs)) + r") on", d) for d in desc): + continue + for i in v.get("items", []): + mm = re.search(r"\[([^\]]+)\]", i.get("description", "")) + if mm and "Pad" not in i.get("description", ""): + hits[i["uuid"]] = mm.group(1) + if not hits: + break + gone = 0 + for t_ in list(board.GetTracks()): + if t_.m_Uuid.AsString() in hits: + board.RemoveNative(t_); gone += 1 + print(f" clear {gone} item(s) ripped up from under the new lands") + if not gone: + break + pcbnew.ZONE_FILLER(board).Fill(board.Zones()); board.BuildConnectivity() + + # Each capacitor now reaches its plane at its own pad instead of through a + # chain of its neighbours -- the shorter return loop, and the reason the + # escape slots are free. + if a.no_repair: + print(" plane vias skipped -- lands left for the router to share") + else: + added = repair(board, pro, a.via / 2 + a.clearance, a.reach, + a.width, a.via, a.drill) + print(f" plane vias {added} placed") + pcbnew.ZONE_FILLER(board).Fill(board.Zones()); board.BuildConnectivity() + + trial = tempfile.mktemp(suffix=".kicad_pcb") + if pro: + shutil.copy(pro, Path(trial).with_suffix(".kicad_pro")) + pcbnew.SaveBoard(trial, board) + v1, u1, _ = drc(trial) + print(f" after swap {v1} violation(s), {u1} unconnected") + shutil.move(trial, str(work)) + print(f" wrote {work}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/route.py b/hardware/courant/scripts/route.py new file mode 100644 index 0000000..7088b0c --- /dev/null +++ b/hardware/courant/scripts/route.py @@ -0,0 +1,696 @@ +#!/usr/bin/env python3 +""" +Route the board. + +tscircuit places the board and owns the netlist; it does not route it. This +script drives the handoff end to end and brings the copper back: + + dist/courant.kicad_pcb (from `npm run export`) + -> dist/courant.kicad_pro design rules, from scripts/rules.json + -> dist/courant.dsn Specctra, written by KiCad + -> dist/courant.ses Specctra session, written by Freerouting + -> dist/courant.routed.kicad_pcb + +Why KiCad writes the DSN and not `tsci export -f specctra-dsn`: tscircuit's +converter places every component with `side: "front"` regardless of its layer, +which would move all 38 back-side BGA decoupling capacitors to the top of the +board, and it crashes outright on a pad whose `pcb_component_id` is null (the +three fiducials). KiCad's exporter gets both right, and it is the same file +Freerouting is actually tested against. + +Requirements, none of which npm can install: + + * KiCad 9 or newer with the `pcbnew` Python module (`python3 -c "import pcbnew"`) + * a JRE + * freerouting.jar, from https://github.com/freerouting/freerouting/releases + Point $FREEROUTING_JAR at it, or pass --jar, or drop it in hardware/courant/. + +Usage: + python3 scripts/route.py [--passes N] [--threads N] [--jar PATH] + python3 scripts/route.py --import-only # re-import an existing .ses +""" +from __future__ import annotations + +if __name__ == "__main__": + from pathlib import Path as _NativePath + if (_NativePath(__file__).resolve().parents[1]/"NATIVE_BASELINE.json").exists(): + raise SystemExit('Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.') + + +import argparse +import json +import os +import re +import shutil +import subprocess +import sys +from pathlib import Path + +HERE = Path(__file__).resolve().parent +ROOT = HERE.parent +DIST = ROOT / "dist" + +BOARD = PROJECT = DSN = SES = ROUTED = FRCFG = None + + +def shown(p: Path) -> str: + """Path for a message: repo-relative when it is in the repo, else absolute. + + --dist can point anywhere, and Path.relative_to raises rather than falling + back when it does not. + """ + return str(p.relative_to(ROOT)) if p.is_relative_to(ROOT) else str(p) + + +def set_dist(d: Path) -> None: + """Point the whole pipeline at a directory other than dist/. + + A re-route that starts from a board which already carries copper is an + experiment, and an experiment must not be able to overwrite the routed + board it was seeded from. --dist gives it somewhere else to write; the + per-directory lock in check_not_already_running() then keeps two of them + from colliding as well. + """ + global DIST, BOARD, PROJECT, DSN, SES, ROUTED, FRCFG + DIST = d + BOARD = DIST / "courant.kicad_pcb" + PROJECT = DIST / "courant.kicad_pro" + DSN = DIST / "courant.dsn" + SES = DIST / "courant.ses" + ROUTED = DIST / "courant.routed.kicad_pcb" + FRCFG = DIST / "freerouting" + + +set_dist(DIST) + + +def load_pcbnew(): + """Import KiCad's pcbnew module without its startup noise. + + Importing pcbnew outside the KiCad application prints a page of + `assert "m_choices.GetCount() > 0" failed in PROPERTY_ENUM()` to stderr + while it registers property enums it has no UI for. It is harmless and + there is no flag for it, so file descriptor 2 is closed over the import + only -- anything these scripts actually report still reaches the terminal. + """ + import importlib + import os as _os + saved = _os.dup(2) + devnull = _os.open(_os.devnull, _os.O_WRONLY) + try: + _os.dup2(devnull, 2) + return importlib.import_module("pcbnew") + finally: + _os.dup2(saved, 2) + _os.close(saved) + _os.close(devnull) + + +def die(msg: str) -> None: + print(f"route: {msg}", file=sys.stderr) + raise SystemExit(1) + + +def find_jar(explicit: str | None) -> Path: + for candidate in (explicit, os.environ.get("FREEROUTING_JAR"), + ROOT / "freerouting.jar", DIST / "freerouting.jar"): + if candidate and Path(candidate).is_file(): + return Path(candidate) + die("freerouting.jar not found. Download it from\n" + " https://github.com/freerouting/freerouting/releases\n" + "and set $FREEROUTING_JAR, or pass --jar PATH.") + + +def write_project() -> None: + """Write the KiCad project file that carries the board's design rules. + + KiCad reads design rules from the project, not the board, so the rules have + to sit next to the .kicad_pcb under the same basename for the DSN export, + the DRC and the Gerber export to agree with each other. + """ + rules = json.loads((HERE / "rules.json").read_text()) + rules.pop("_comment", None) + PROJECT.write_text(json.dumps(rules, indent=2)) + + +def protect_existing_wiring(dsn: Path, ripup_box=None, keep=()) -> tuple[int, int]: + """Decide, per wire and via, whether the router may rip it up. + + KiCad writes pre-existing copper into the DSN's wiring section as + `(type route)`, which tells Freerouting it is looking at its own previous + output and may do as it likes with it. `protect` maps to SYSTEM_FIXED and + takes that permission away. + + Protecting everything is the safe default and, on a board seeded with a + previous route, it is also a way to lose. A router that may not rip up is a + router that cannot negotiate: on this board it closed 84 of 139 connections + in the first pass and then sat at 48 unrouted and 23 violations for four + passes, because the conflicts that remained could only be resolved by + moving copper it had been forbidden to touch. + + So protection is selective. `ripup_box` is a region -- in DSN coordinates, + which are micrometres with y negated -- inside which copper stays rippable; + everything outside it is frozen. Pass U1's bounding box and the router may + rework the ball field, where all the contention is, while the rest of the + board and both ground planes stay exactly as they were. + + `keep` names points that stay protected wherever they are: the escape vias + placed by hand in slots that took real work to open, and which the router + would be free to delete and then fail to re-create. + """ + text = dsn.read_text() + head, sep, wiring = text.partition("(wiring") + if not sep: + return 0, 0 + + def points(line): + body = line.split("(path", 1)[1] if "(path" in line else line.split('"', 2)[-1] + nums, out = re.findall(r"-?\d+(?:\.\d+)?", body.split("(net", 1)[0]), [] + if "(path" in line: + nums = nums[1:] # drop the width that follows the layer + for i in range(0, len(nums) - 1, 2): + out.append((float(nums[i]), float(nums[i + 1]))) + return out + + def inside(pts): + if not ripup_box: + return False + x0, y0, x1, y1 = ripup_box + return any(x0 <= x <= x1 and y0 <= y <= y1 for x, y in pts) + + def pinned(pts): + return any(abs(x - kx) <= 50 and abs(y - ky) <= 50 + for x, y in pts for kx, ky in keep) + + frozen = free = 0 + out = [] + for line in wiring.splitlines(keepends=True): + if "(type route)" in line: + pts = points(line) + if inside(pts) and not pinned(pts): + free += 1 + else: + line = line.replace("(type route)", "(type protect)") + frozen += 1 + out.append(line) + dsn.write_text(head + sep + "".join(out)) + return frozen, free + + +# Nets whose pour is a return path, and therefore must not be cut by signals. +RETURN_NETS = {"GND", "AGND", "DGND"} + + +def restrict_signal_layers(dsn: Path, plane_layers: list[str], + ground_class: str = "Ground") -> int: + """Keep signals off the ground planes without locking GND out of them. + + The obvious approach -- declaring the plane layers `(type power)` in the + DSN -- is wrong, and wrong in a way that looks exactly like the board being + too dense. A `power` layer is not "routable by GND only"; Freerouting takes + it as unavailable for connections altogether, so the GND pins cannot reach + their own plane either. Three routing runs left 55 to 60 connections + unrouted that way, about fifty of them GND, and the planes being off limits + was read as insufficient routing capacity. It was not: the board was never + short of layers, GND was short of a way down. + + Specctra has the mechanism actually wanted. Every layer stays `signal`, so + vias and plane connections work normally, and each net class except the + ground class carries a `use_layer` clause naming only the non-plane layers. + Signals are then confined to the signal layers by rule, while GND keeps the + whole stackup and drops straight into its pours. + """ + text = dsn.read_text() + all_layers = re.findall(r"\(layer\s+(\S+)\s*\n\s*\(type\s+\w+\)", text) + routable = [l for l in all_layers if l not in plane_layers] + if not routable: + return 0 + clause = "(use_layer " + " ".join(routable) + ")" + + def patch(m: re.Match) -> str: + name, body = m.group(1), m.group(0) + if name.startswith(ground_class) or "use_layer" in body: + return body + return body.replace("(circuit\n", "(circuit\n " + clause + "\n", 1) + + text, n = re.subn(r"\(class\s+(\S+)[\s\S]*?\n \)", patch, text), 0 + if isinstance(text, tuple): + text, n = text + dsn.write_text(text) + return len(re.findall(re.escape(clause), text)) + + +def plane_layers(board, pcbnew) -> list[str]: + """Copper layers the router must not touch: the ground planes, and only those. + + The reason to forbid routing on a poured layer is to protect return + current, and return current flows in the ground planes. A power pour is + different: V3V3 is decoupled at two dozen points across this board, and a + slot in it costs far less than a slot in GND, which every signal on an + adjacent layer references. + + The specificity is worth having, because reserving too much is as damaging + as reserving too little. Measured on this board: reserving nothing left 166 + signal segments cut through both ground planes but only 8 connections + unrouted; reserving both ground planes gave clean planes and 56 unrouted; + additionally reserving the V3V3 plane gave about 90. Four signal layers is + what this board needs, so In3 carries the 3.3 V pour *and* signals, and the + pour fills around them. + """ + out = [] + for zone in board.Zones(): + if zone.GetNetname() not in RETURN_NETS: + continue + for layer in zone.GetLayerSet().CuStack(): + name = board.GetLayerName(layer) + if name not in out: + out.append(name) + return out + + +def remove_degenerate_tracks(board, pcbnew, limit_mm: float = 0.01) -> int: + """Delete segments too short to be geometry. + + A track a few microns long joins two points that are already coincident as + far as any fabrication process is concerned, so removing it cannot + disconnect anything -- whatever touched one end touches the other. It can, + however, stop the router dead. Freerouting normalizes every protected wire + into a polyline before it can treat it as an obstacle, and a zero-length + segment sends that recursion to its depth limit; on this board 29 such + segments (7 of them on V3V3) pinned the fanout stage in a loop that emitted + nothing but `PolylineTrace.normalize: max normalization depth reached` for + thirteen minutes and never reached the autorouter at all. + + They arrive from the router itself, and from importing a session whose + wiring has been re-landed, so this runs on both sides of the round trip. + """ + doomed = [t for t in board.GetTracks() + if t.Type() == pcbnew.PCB_TRACE_T + and t.GetLength() < limit_mm * 1_000_000] + for t in doomed: + board.RemoveNative(t) + if doomed: + board.BuildConnectivity() + return len(doomed) + + +def weld_near_misses(board, pcbnew, tol_mm: float = 0.02) -> int: + """Snap same-net track endpoints that nearly, but do not exactly, meet. + + KiCad decides connectivity geometrically: two 0.15 mm tracks whose + endpoints miss each other by seven micrometres still overlap, so the net + reads as connected and DRC says nothing. Freerouting decides it from the + endpoints, so it sees a break, adds the connection to its worklist, and + then fails to route it -- the gap is far too short to hold a trace. + + On this board that accounted for 192 phantom breaks, 173 of them on V1V8, + and V1V8 was among the nets the router reported itself unable to finish. + They come from the router's own floating-point output on the previous run, + which is why they survived every DRC since. + + Snapping each cluster to its first member closes the gap. The largest move + is the tolerance itself -- 20 um, an order of magnitude below anything a + fabricator resolves. + """ + tol = tol_mm * 1_000_000 + groups: dict = {} + for t in board.GetTracks(): + if t.Type() != pcbnew.PCB_TRACE_T: + continue + groups.setdefault((t.GetNetCode(), t.GetLayer()), []).append(t) + + welded = 0 + for tracks in groups.values(): + anchors: list = [] + for t in tracks: + for get, set_ in ((t.GetStart, t.SetStart), (t.GetEnd, t.SetEnd)): + p = get() + for a in anchors: + dx, dy = p.x - a.x, p.y - a.y + if dx * dx + dy * dy <= tol * tol: + if dx or dy: + set_(a); welded += 1 + break + else: + anchors.append(p) + if welded: + board.BuildConnectivity() + return welded + + +def export_dsn(ripup_ref: str | None = None, keep_mm=()) -> None: + pcbnew = load_pcbnew() + board = pcbnew.LoadBoard(str(BOARD)) + shed = remove_degenerate_tracks(board, pcbnew) + welded = weld_near_misses(board, pcbnew) + if shed or welded: + print(f" clean {shed} degenerate segment(s) dropped, " + f"{welded} near-miss junction(s) welded before export") + pcbnew.SaveBoard(str(BOARD), board) + board = pcbnew.LoadBoard(str(BOARD)) + if not pcbnew.ExportSpecctraDSN(board, str(DSN)): + die("KiCad failed to write the DSN") + box = None + if ripup_ref: + fp = board.FindFootprintByReference(ripup_ref) + if fp is None: + die(f"--ripup {ripup_ref}: no such footprint") + bb = fp.GetBoundingBox() + # DSN coordinates are micrometres with y negated. + box = (bb.GetLeft() / 1000, -bb.GetBottom() / 1000, + bb.GetRight() / 1000, -bb.GetTop() / 1000) + keep = [(x * 1000, -y * 1000) for x, y in keep_mm] + frozen, free = protect_existing_wiring(DSN, box, keep) + planes = plane_layers(board, pcbnew) + marked = restrict_signal_layers(DSN, planes) + print(f" dsn {DSN.name} ({frozen} item(s) protected" + + (f", {free} left rippable inside {ripup_ref}" if box else "") + + (f", {len(keep)} escape via(s) pinned" if keep else "") + + f", {marked} class(es) kept off the ground planes: {', '.join(planes)})") + + +def run_freerouting(jar: Path, passes: int, threads: int, gui: bool = False, + fanout: bool = True, optimize: bool = True) -> None: + """Run the router headless. + + Freerouting's defaults are wrong for a batch run in three ways that cost + real time: it opens a GUI and spends the run repainting it, its + multi-threading feature flag is off, which holds the whole route to about + one core, and its fanout stage has no budget of its own. All three live in + a settings file rather than on the command line, so + the settings file is written here and $FREEROUTING__USER_DATA_PATH points + the tool at it. That also keeps this run out of the user's own + ~/.config/freerouting, and turns off the telemetry that is on by default. + """ + FRCFG.mkdir(parents=True, exist_ok=True) + (FRCFG / "freerouting.json").write_text(json.dumps({ + # A profile id has to be present or the tool NPEs on startup. + "profile": {"id": "00000000-0000-4000-8000-000000000000", "email": "", + "allow_telemetry": False, "allow_contact": False}, + # Headless by default. --gui puts the router's board window up so the + # route can be watched; it costs real time, because the tool repaints + # the whole board, conduction areas included, while it works. + "gui": {"enabled": gui, "dialog_confirmation_timeout": 0}, + "router": { + "enabled": True, "max_passes": passes, "job_timeout": "PT3H", + "vias_allowed": True, + # Fanout and the optimizer draw on the same job budget as the + # autorouter, and fanout will happily spend all of it: on this board + # it escapes 506 of 544 pins in the first three passes and then + # grinds on the same ~33 it cannot place, at a minute or more a + # pass. Capping it leaves the time for the stage that actually + # routes nets. + # Automatic neckdown lets the router thin a trace to squeeze past an + # obstacle. It produced 0.1124 mm copper against a 0.15 mm minimum + # and 70 DRC errors; the minimum is a fab limit, not a preference. + "automatic_neckdown": False, + "neck_width_um": 150, + # --no-fanout turns this stage off entirely. Its budget is only + # checked between passes, so a pass that fails to terminate ignores + # it: on a board seeded with already-routed copper, fanout has been + # seen to sit in a single pass indefinitely and never hand over to + # the autorouter. When every surviving wire is protected and the + # escapes are pre-placed, fanout is an optimisation rather than a + # requirement -- the autorouter will place the vias it needs itself. + "fanout": {"enabled": fanout, "max_passes": 6, "timeout": "PT12M"}, + # The optimizer cannot close a connection -- it shortens routes and + # removes vias on what is already routed. That is worth having on + # this board, where vias are the binding constraint, but it also + # holds the session file hostage: Freerouting writes the .ses only + # when the whole job ends, so a 45 minute optimizer is 45 minutes + # before the result can be imported and measured. --no-optimize + # trades the polish for the answer. + "optimizer": {"enabled": optimize, "max_passes": 20, + "timeout": "PT45M"}, + "scoring": {}, + }, + "usage_and_diagnostic_data": {"disable_analytics": True}, + "feature_flags": {"multi_threading": True}, + "api_server": {"enabled": False}, + "mcp_server": {"enabled": False}, + "logging": {"console": {"enabled": True, "level": "INFO"}, + "file": {"enabled": True, "level": "INFO"}}, + "version": "2.4.1", + }, indent=1)) + + SES.unlink(missing_ok=True) + env = {**os.environ, "FREEROUTING__USER_DATA_PATH": str(FRCFG)} + cmd = ["java", "-jar", str(jar), "-de", str(DSN), "-do", str(SES), + "-mp", str(passes), "-mt", str(threads)] + print(f" route {' '.join(cmd[2:])}") + proc = subprocess.run(cmd, env=env, cwd=DIST, stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, text=True) + (DIST / "freerouting-run.log").write_text(proc.stdout) + for line in proc.stdout.splitlines(): + if "stage" in line and ("completed" in line or "interrupted" in line): + print(" " + line.split("INFO", 1)[-1].strip()) + if not SES.is_file(): + die("Freerouting produced no session file; see dist/freerouting-run.log") + + +MIN_SILK_TEXT_MM = 0.8 + + +def normalize_silkscreen(board, pcbnew) -> int: + """Raise reference designators to a size a screen printer can resolve. + + tscircuit emits most references at 0.4 mm, half of KiCad's 0.8 mm minimum + and below what silkscreen printing holds -- they come back smeared or + filled in, which matters for assembly and rework, and accounts for 199 of + the DRC violations on the first routed board. Only the height is wrong; + the 0.15 mm stroke is already above the 0.08 mm floor, and value text is + already on F.Fab and hidden, which is what it should be. + + Nothing else about the silkscreen is touched here. The outlines clear each + other by more than half a millimetre, which is the one thing about this + board's silk that was never actually broken, and the connectors' generic + "pinN" labels are left at 0.5 mm on purpose: enlarging them to 0.8 mm would + put roughly 2.4 mm of text on a 2.54 mm header pitch, and the board already + carries the labels that matter ("5V DC", "MIDI IN", "PITCH", "LINE L G R") + as board-level silkscreen next to each connector. They remain as DRC + warnings rather than being made illegible or removed. + + Raising the references costs about nineteen extra `silk_overlap` warnings, + nearly all of which are a reference sitting on its own footprint outline. + That is normal and prints fine; a reference too small to read does not. + """ + fixed = 0 + for fp in board.GetFootprints(): + ref = fp.Reference() + if not ref.IsVisible(): + continue + if ref.GetTextHeight() < int(MIN_SILK_TEXT_MM * 1e6): + ref.SetTextSize(pcbnew.VECTOR2I(int(MIN_SILK_TEXT_MM * 1e6), + int(MIN_SILK_TEXT_MM * 1e6))) + fixed += 1 + return fixed + + +def widen_thin_tracks(board, pcbnew) -> tuple[int, int]: + """Bring stub copper up to the board minimum, except where it must be thin. + + Freerouting emits short pad-exit stubs at about 0.1124 mm regardless of the + net class width, and `automatic_neckdown: false` does not stop it. Most of + those stubs are half a millimetre of copper leaving an 0603 pad with room + to spare on every side, so they are simply widened to the 0.15 mm minimum. + + Inside the BGA they are left alone. Escaping between two FTG256 balls has + 0.5 mm to work with, and 0.1124 mm of trace with 0.15 mm either side fits + where 0.15 mm of trace does not -- widening those ten segments trades a + width warning for four real clearance violations against the balls + themselves. A narrower trace under a BGA is a deliberate, normal technique; + it does mean the board's true minimum feature is 0.1124 mm rather than + 0.15 mm, which is what the fab has to be told (see docs/board.md section 3). + """ + u1 = next((f for f in board.GetFootprints() if f.GetReference() == "U1"), None) + if u1 is None: + return 0, 0 + bb = u1.GetBoundingBox(False, False) + margin = 200000 + x0, x1 = bb.GetX() - margin, bb.GetX() + bb.GetWidth() + margin + y0, y1 = bb.GetY() - margin, bb.GetY() + bb.GetHeight() + margin + + def in_escape(track) -> bool: + return any(x0 <= p.x <= x1 and y0 <= p.y <= y1 + for p in (track.GetStart(), track.GetEnd())) + + minimum = int(0.15 * 1e6) + widened = kept = 0 + for t in board.GetTracks(): + if t.Type() != pcbnew.PCB_TRACE_T or t.GetWidth() >= minimum: + continue + if in_escape(t): + kept += 1 + else: + t.SetWidth(minimum) + widened += 1 + return widened, kept + + +def remove_dangling_vias(board, pcbnew) -> int: + """Drop vias the router left connected to nothing. + + Fanout places an escape via for every pad it can, and when the autorouter + later routes that net a different way the via is simply abandoned. It is + not harmful, but it is a hole the fab drills and plates for no reason, and + it shows up as `via_dangling` in DRC. + """ + connectivity = board.GetConnectivity() + doomed = [] + for t in board.GetTracks(): + if t.Type() != pcbnew.PCB_VIA_T: + continue + try: + neighbours = connectivity.GetConnectedItems(t) + except TypeError: + continue + # The via itself is normally in its own connected set, so a via that + # reaches nothing else has at most one entry. + if len([n for n in neighbours if n is not t]) < 1: + doomed.append(t) + for v in doomed: + board.Remove(v) + return len(doomed) + + +def import_ses() -> int: + """Pull the routed copper back into the board and refill the ground planes.""" + pcbnew = load_pcbnew() + board = pcbnew.LoadBoard(str(BOARD)) + if not pcbnew.ImportSpecctraSES(board, str(SES)): + die("KiCad failed to import the session file") + + bumped = normalize_silkscreen(board, pcbnew) + board.BuildConnectivity() + widened, necked = widen_thin_tracks(board, pcbnew) + dropped = remove_dangling_vias(board, pcbnew) + shed = remove_degenerate_tracks(board, pcbnew) + + # The pours are regenerated here rather than trusted from the placed board: + # they have to flow around copper that did not exist when tscircuit emitted + # them, and an unfilled zone is not a ground plane. + filler = pcbnew.ZONE_FILLER(board) + filler.Fill(board.Zones()) + board.BuildConnectivity() + pcbnew.SaveBoard(str(ROUTED), board) + + if shed: + print(f" clean {shed} degenerate segment(s) dropped after import") + tracks = [t for t in board.GetTracks() if t.Type() == pcbnew.PCB_TRACE_T] + vias = [t for t in board.GetTracks() if t.Type() == pcbnew.PCB_VIA_T] + length = sum(t.GetLength() for t in tracks) / 1e6 + unrouted = board.GetConnectivity().GetUnconnectedCount(True) + print(f" routed {len(tracks)} segments ({length:.0f} mm), {len(vias)} vias, " + f"{board.GetAreaCount()} zones filled") + print(f" silk {bumped} reference designator(s) raised to " + f"{MIN_SILK_TEXT_MM} mm") + print(f" width {widened} stub(s) widened to 0.15 mm, " + f"{necked} left necked in the BGA escape") + print(f" cleanup {dropped} dangling via(s) removed") + print(f" {'OK' if unrouted == 0 else 'INCOMPLETE'} " + f"{unrouted} unrouted connection(s)") + print(f" wrote {shown(ROUTED)}") + return unrouted + + +def check_not_already_running() -> None: + """Refuse to start if another route is writing the same dist/ directory. + + Two routes sharing output files will swap the board out from under each + other. That happened here once: a six-layer session finished importing two + minutes after the board had been rebuilt with eight layers, producing an + archive that held eight copper layers of six-layer routing. It is not + detectable from the file afterwards, so this is a guard rather than a note. + + The lock is per output directory, not per machine, so an isolated run with + its own tree can proceed in parallel -- which is the whole point of having + one, when a long route is already in flight. + """ + lock = DIST / ".route.lock" + if lock.is_file(): + try: + other = int(lock.read_text().strip()) + except ValueError: + other = None + if other and other != os.getpid(): + try: + os.kill(other, 0) + except (ProcessLookupError, PermissionError): + pass # stale lock, ours now + else: + die(f"another route is already writing {DIST} (pid {other}).\n" + "Wait for it, kill it, or run from a separate tree.") + DIST.mkdir(parents=True, exist_ok=True) + lock.write_text(str(os.getpid())) + import atexit + atexit.register(lambda: lock.unlink(missing_ok=True)) + + +def main() -> int: + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("--passes", type=int, default=100) + ap.add_argument("--threads", type=int, default=max(1, (os.cpu_count() or 2) - 2)) + ap.add_argument("--jar") + ap.add_argument("--gui", action="store_true", + help="show Freerouting's board window while it routes (slower)") + ap.add_argument("--no-fanout", action="store_true", + help="skip the fanout stage and go straight to autorouting") + ap.add_argument("--no-optimize", action="store_true", + help="skip the optimizer; the session file is written as " + "soon as autorouting ends rather than up to 45 minutes " + "later, at the cost of via-count and length polish") + ap.add_argument("--ripup", metavar="REF", + help="let the router rip up and rework copper inside this " + "footprint's bounding box; everything outside stays " + "frozen. Without it every pre-existing wire is " + "protected, which on a seeded re-route can wall the " + "router off from the only moves that would help.") + ap.add_argument("--keep-via", metavar="X,Y", action="append", default=[], + help="protect the via at these mm coordinates even inside " + "--ripup, for escapes placed by hand (repeatable)") + ap.add_argument("--import-only", action="store_true", + help="skip the router and re-import the existing .ses") + ap.add_argument("--dist", type=Path, + help="work in this directory instead of dist/, so a re-route " + "seeded from an already-routed board cannot overwrite it") + args = ap.parse_args() + + if args.dist: + set_dist(args.dist.resolve()) + print(f" dist {DIST}") + check_not_already_running() + try: + load_pcbnew() + except ImportError: + die("KiCad's pcbnew Python module is not importable.\n" + "Install KiCad 9+ (Fedora: dnf install kicad; Debian: apt install kicad).") + if not BOARD.is_file(): + die(f"{shown(BOARD)} not found -- run `npm run export` first.") + + write_project() + print(f" rules {PROJECT.name} from scripts/rules.json") + + if not args.import_only: + if not shutil.which("java"): + die("java not found; Freerouting needs a JRE.") + jar = find_jar(args.jar) + keep = [] + for spec in args.keep_via: + try: + x, y = (float(v) for v in spec.split(",")) + except ValueError: + die(f"--keep-via {spec}: expected X,Y in mm") + keep.append((x, y)) + export_dsn(args.ripup, keep) + run_freerouting(jar, args.passes, args.threads, args.gui, + fanout=not args.no_fanout, + optimize=not args.no_optimize) + elif not SES.is_file(): + die(f"{shown(SES)} not found; run without --import-only first.") + + return 1 if import_ses() else 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/rules.json b/hardware/courant/scripts/rules.json new file mode 100644 index 0000000..7abf1d1 --- /dev/null +++ b/hardware/courant/scripts/rules.json @@ -0,0 +1,114 @@ +{ + "_comment": [ + "Fabrication design rules for the Courant Rev A board, as a KiCad project", + "file. scripts/route.py writes this next to dist/courant.kicad_pcb so that", + "the router, the DRC and the Gerber export all read the same numbers.", + "", + "Why these values, and not KiCad's defaults (0.2 mm track / 0.2 mm clearance", + "/ 0.6 mm via): the XC7A35T's FTG256 balls are 0.5 mm pads on a 1.0 mm", + "pitch, so the gap between two neighbouring balls is 0.5 mm. Escaping a", + "signal between them needs width + 2 x clearance to fit in that gap, and", + "KiCad's defaults need 0.6 mm. At 0.15/0.15 it is 0.45 mm and it fits.", + "", + "The same argument sets the via: a dog-bone via sits in the diagonal gap", + "between four balls, 0.707 mm from each ball centre. With a 0.55 mm via pad", + "and a 0.5 mm ball pad that leaves 0.707 - 0.25 - 0.275 = 0.182 mm, which", + "clears 0.15 mm. A 0.6 mm via would leave 0.157 mm and would not.", + "", + "0.25 mm drill in a 1.6 mm board is a 6.4:1 aspect ratio (<= 8:1 preferred)", + "and the 0.15 mm annular ring is past the 0.13 mm knee where breakout risk", + "collapses. All of this is inside every standard 6-layer process.", + "", + "The Power class widens the rails. It keeps the Default clearance and via,", + "deliberately: VCCO, VCCINT and VCCAUX balls are inside the same 1.0 mm ball", + "field as the signals, so a wider power via could not be fanned out at all.", + "", + "GND has its own class so the router can be told where signals may go without also telling GND where it may not. scripts/route.py restricts every class except Ground to the non-plane layers via a Specctra `use_layer` clause. The earlier attempt marked the plane layers `(type power)` instead, which does not mean 'no signals here' -- it makes the layer unavailable for connections at all, so GND pins could not reach their own plane. That single mistake left 50-odd GND connections unrouted in three separate routing runs and was misread as the board being too dense." + ], + "board": { + "design_settings": { + "rules": { + "min_clearance": 0.15, + "min_track_width": 0.15, + "min_through_hole_diameter": 0.25, + "min_via_annular_width": 0.125, + "min_via_diameter": 0.5, + "min_hole_to_hole": 0.25, + "min_silk_clearance": 0.0 + } + } + }, + "net_settings": { + "classes": [ + { + "name": "Default", + "clearance": 0.15, + "track_width": 0.15, + "via_diameter": 0.55, + "via_drill": 0.25, + "microvia_diameter": 0.3, + "microvia_drill": 0.1 + }, + { + "name": "Power", + "clearance": 0.15, + "track_width": 0.4, + "via_diameter": 0.55, + "via_drill": 0.25, + "microvia_diameter": 0.3, + "microvia_drill": 0.1 + }, + { + "name": "Ground", + "clearance": 0.15, + "track_width": 0.3, + "via_diameter": 0.55, + "via_drill": 0.25, + "microvia_diameter": 0.3, + "microvia_drill": 0.1 + } + ], + "netclass_patterns": [ + { + "netclass": "Ground", + "pattern": "GND" + }, + { + "netclass": "Power", + "pattern": "VIN5" + }, + { + "netclass": "Power", + "pattern": "V1" + }, + { + "netclass": "Power", + "pattern": "V1V8" + }, + { + "netclass": "Power", + "pattern": "V3V3" + }, + { + "netclass": "Power", + "pattern": "A3V3" + }, + { + "netclass": "Power", + "pattern": "SW1" + }, + { + "netclass": "Power", + "pattern": "SW2" + }, + { + "netclass": "Power", + "pattern": "SW3" + } + ] + }, + "meta": { + "filename": "courant.kicad_pro", + "version": 3 + } +} diff --git a/hardware/courant/scripts/schematic.py b/hardware/courant/scripts/schematic.py new file mode 100644 index 0000000..168fd66 --- /dev/null +++ b/hardware/courant/scripts/schematic.py @@ -0,0 +1,140 @@ +#!/usr/bin/env python3 +""" +Render the schematic from circuit JSON, because tscircuit's own renderers do not. + +`tsci export -f schematic-svg` and `-f schematic-pdf` both emit a near-empty +sheet for this design -- twenty text elements and sixteen lines for two hundred +components, about ten kilobytes either way. The data is not missing: the circuit +JSON carries 183 schematic components, 739 ports, 532 traces and 248 net labels. +Only the drawing is missing, so this draws it. + +It is a schematic in the sense that matters for a handoff -- every component, +every pin, every wire and every net label, to scale and legible -- and not in +the sense of a hand-drafted sheet with signal flow arranged left to right. +tscircuit places symbols on a grid in declaration order; no autolayout will +turn that into the drawing a person would have made. + + python3 scripts/schematic.py CIRCUIT_JSON --out OUT.svg +""" +from __future__ import annotations + +import argparse, json +from xml.sax.saxutils import escape + +PX = 64.0 # pixels per schematic unit +PAD = 1.2 # margin, schematic units + + +def main(): + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("circuit"); ap.add_argument("--out", required=True) + ap.add_argument("--title", default="Courant Rev A") + a = ap.parse_args() + + d = json.load(open(a.circuit)) + by = {} + for e in d: + by.setdefault(e.get("type"), []).append(e) + src = {e["source_component_id"]: e for e in by.get("source_component", [])} + + xs, ys = [], [] + def note(x, y): + xs.append(x); ys.append(y) + + for c in by.get("schematic_component", []): + w, h = c["size"]["width"] / 2, c["size"]["height"] / 2 + note(c["center"]["x"] - w, c["center"]["y"] - h) + note(c["center"]["x"] + w, c["center"]["y"] + h) + for t in by.get("schematic_trace", []): + for ed in t.get("edges", []): + for p in (ed.get("from"), ed.get("to")): + if p: note(p["x"], p["y"]) + for n in by.get("schematic_net_label", []): + note(n["center"]["x"], n["center"]["y"]) + if not xs: + print(" nothing to draw"); return 1 + + x0, x1 = min(xs) - PAD, max(xs) + PAD + y0, y1 = min(ys) - PAD, max(ys) + PAD + W, H = (x1 - x0) * PX, (y1 - y0) * PX + + def X(v): return (v - x0) * PX + def Y(v): return (y1 - v) * PX # schematic Y is up, SVG Y is down + + o = [f'', + '', + ''] + + # wires first, so symbols sit on top of them + for t in by.get("schematic_trace", []): + for ed in t.get("edges", []): + f, g = ed.get("from"), ed.get("to") + if not f or not g: + continue + o.append(f'') + for j in t.get("junctions", []): + o.append(f'') + + for c in by.get("schematic_component", []): + cx, cy = c["center"]["x"], c["center"]["y"] + w, h = c["size"]["width"], c["size"]["height"] + o.append(f'') + s = src.get(c.get("source_component_id"), {}) + name = s.get("name", "") + # circuit JSON keeps the value under a different key per component + # type; there is no common one, and reading only display_value drops + # every resistor, capacitor and inductor on the sheet. + val = next((s[k] for k in ("display_resistance", "display_capacitance", + "display_inductance", "display_value", + "manufacturer_part_number") if s.get(k)), "") + if name: + o.append(f'{escape(name)}') + if val: + o.append(f'{escape(str(val))}') + + for p in by.get("schematic_port", []): + o.append(f'') + + for n in by.get("schematic_net_label", []): + cx, cy = n["center"]["x"], n["center"]["y"] + o.append(f'' + f'{escape(n.get("text", ""))}') + + for t in by.get("schematic_text", []): + pos = t.get("position") or t.get("center") + if not pos: + continue + o.append(f'{escape(t.get("text", ""))}') + + o.append('') + o.append(f'{escape(a.title)} — schematic — ' + f'{len(by.get("schematic_component", []))} components, ' + f'{len(by.get("schematic_trace", []))} nets drawn') + o.append('') + open(a.out, "w").write("\n".join(o)) + print(f" {len(by.get('schematic_component', []))} components, " + f"{len(by.get('schematic_port', []))} ports, " + f"{len(by.get('schematic_trace', []))} traces, " + f"{len(by.get('schematic_net_label', []))} net labels") + print(f" {W:.0f} x {H:.0f} px -> {a.out}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/scripts/stitch.py b/hardware/courant/scripts/stitch.py new file mode 100644 index 0000000..c0dfa28 --- /dev/null +++ b/hardware/courant/scripts/stitch.py @@ -0,0 +1,196 @@ +#!/usr/bin/env python3 +""" +Close short BGA escapes by finding a via slot that is clear on every layer. + +The connections the autorouter leaves on this board are mostly a ball on the +top and its decoupling capacitor underneath, needing a via between them. They +are not routing problems and a maze router handles them badly -- it searches for +a path when what is wanted is a hole in the right place. + +The one thing that makes this work is checking *all* layers. A through via +crosses six of them, and a slot that is obviously free on F.Cu and B.Cu can be +occupied on In2 by a trace nobody was looking at; two earlier attempts here +placed vias that shorted to exactly that. So the search tests every copper +layer, and then KiCad's DRC checks the result before it is kept. + + python3 scripts/stitch.py BOARD --out OUT [--reach MM] +""" +from __future__ import annotations + +if __name__ == "__main__": + from pathlib import Path as _NativePath + if (_NativePath(__file__).resolve().parents[1]/"NATIVE_BASELINE.json").exists(): + raise SystemExit('Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.') + + +import argparse, json, math, os, shutil, subprocess, tempfile +from pathlib import Path + + +def load_pcbnew(): + import importlib + saved, devnull = os.dup(2), os.open(os.devnull, os.O_WRONLY) + try: + os.dup2(devnull, 2) + return importlib.import_module("pcbnew") + finally: + os.dup2(saved, 2); os.close(saved); os.close(devnull) + + +pcbnew = load_pcbnew() +NM = 1_000_000 + + +def drc(path): + o = tempfile.mktemp(suffix=".json") + subprocess.run(["kicad-cli", "pcb", "drc", "--output", o, "--format", "json", + "--units", "mm", "--severity-error", "--refill-zones", path], + capture_output=True, text=True) + j = json.load(open(o)); os.unlink(o) + return len(j.get("violations", [])), len(j.get("unconnected_items", [])), j + + +def obstacles(board, netcode): + """Foreign copper as discs and segments, with the layers they sit on.""" + discs, segs = [], [] + for t in board.GetTracks(): + if t.GetNetCode() == netcode: + continue + if t.Type() == pcbnew.PCB_VIA_T: + p = t.GetPosition() + discs.append((p.x / 1e6, p.y / 1e6, t.GetWidth(pcbnew.F_Cu) / 2 / 1e6)) + else: + a, e = t.GetStart(), t.GetEnd() + segs.append((a.x / 1e6, a.y / 1e6, e.x / 1e6, e.y / 1e6, t.GetWidth() / 2 / 1e6)) + for fp in board.GetFootprints(): + for pad in fp.Pads(): + if pad.GetNetCode() == netcode: + continue + p = pad.GetPosition(); sz = pad.GetSize() + discs.append((p.x / 1e6, p.y / 1e6, max(sz.x, sz.y) / 2 / 1e6)) + return discs, segs + + +def seg_dist(px, py, x1, y1, x2, y2): + dx, dy = x2 - x1, y2 - y1 + L = dx * dx + dy * dy + t = 0 if L == 0 else max(0.0, min(1.0, ((px - x1) * dx + (py - y1) * dy) / L)) + return math.hypot(px - (x1 + t * dx), py - (y1 + t * dy)) + + +def find_slot(discs, segs, a, b, need, reach, step=0.05): + """A point clear of all foreign copper, reachable from both endpoints.""" + best = None + steps = int(reach / step) + for i in range(-steps, steps + 1): + for j in range(-steps, steps + 1): + px, py = a[0] + i * step, a[1] + j * step + if math.hypot(px - a[0], py - a[1]) > reach: + continue + if math.hypot(px - b[0], py - b[1]) > reach: + continue + ok = True + for x, y, r in discs: + if math.hypot(px - x, py - y) < r + need: + ok = False; break + if ok: + for x1, y1, x2, y2, r in segs: + if seg_dist(px, py, x1, y1, x2, y2) < r + need: + ok = False; break + if ok: + cost = math.hypot(px - a[0], py - a[1]) + math.hypot(px - b[0], py - b[1]) + if best is None or cost < best[0]: + best = (cost, px, py) + return best + + +def main(): + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("board"); ap.add_argument("--out", required=True) + ap.add_argument("--reach", type=float, default=2.5, + help="how far a stub may run from either endpoint") + ap.add_argument("--clearance", type=float, default=0.15) + ap.add_argument("--via", type=float, default=0.55) + ap.add_argument("--drill", type=float, default=0.25) + ap.add_argument("--width", type=float, default=0.25) + a = ap.parse_args() + + work = Path(a.out) + shutil.copy(a.board, work) + pro = Path(a.board).with_suffix(".kicad_pro") + if pro.is_file(): + shutil.copy(pro, work.with_suffix(".kicad_pro")) + + v0, u0, _ = drc(str(work)) + print(f" start {v0} violation(s), {u0} unconnected") + need = a.via / 2 + a.clearance + + kept = skipped = reverted = 0 + while True: + v_now, u_now, data = drc(str(work)) + pending = data.get("unconnected_items", []) + progressed = False + for e in pending: + items = e.get("items", []) + if len(items) != 2: + continue + board = pcbnew.LoadBoard(str(work)) + idx = {t.m_Uuid.AsString(): t for t in board.GetTracks()} + for fp in board.GetFootprints(): + for pad in fp.Pads(): + idx[pad.m_Uuid.AsString()] = pad + ia, ib = idx.get(items[0]["uuid"]), idx.get(items[1]["uuid"]) + if ia is None or ib is None: + continue + net = ia.GetNetCode(); name = ia.GetNetname() + pa = (items[0]["pos"]["x"], items[0]["pos"]["y"]) + pb = (items[1]["pos"]["x"], items[1]["pos"]["y"]) + la = ia.GetLayer() if ia.Type() == pcbnew.PCB_TRACE_T else pcbnew.F_Cu + lb = ib.GetLayer() if ib.Type() == pcbnew.PCB_TRACE_T else pcbnew.F_Cu + + discs, segs = obstacles(board, net) + slot = find_slot(discs, segs, pa, pb, need, a.reach) + if slot is None: + continue + _, vx, vy = slot + + v = pcbnew.PCB_VIA(board) + v.SetPosition(pcbnew.VECTOR2I(int(vx * NM), int(vy * NM))) + v.SetWidth(int(a.via * NM)); v.SetDrill(int(a.drill * NM)) + v.SetNetCode(net); v.SetViaType(pcbnew.VIATYPE_THROUGH); board.Add(v) + for (sx, sy), ly in ((pa, la), (pb, lb)): + t = pcbnew.PCB_TRACK(board) + t.SetStart(pcbnew.VECTOR2I(int(sx * NM), int(sy * NM))) + t.SetEnd(pcbnew.VECTOR2I(int(vx * NM), int(vy * NM))) + t.SetWidth(int(a.width * NM)); t.SetLayer(ly) + t.SetNetCode(net); board.Add(t) + pcbnew.ZONE_FILLER(board).Fill(board.Zones()); board.BuildConnectivity() + + trial = tempfile.mktemp(suffix=".kicad_pcb") + if pro.is_file(): + shutil.copy(pro, Path(trial).with_suffix(".kicad_pro")) + pcbnew.SaveBoard(trial, board) + v1, u1, _ = drc(trial) + if v1 <= v_now and u1 < u_now: + shutil.move(trial, str(work)) + print(f" STITCH {name:14s} via at ({vx:.3f}, {vy:.3f})" + f" -> {v1} violation(s), {u1} unconnected") + kept += 1; progressed = True + break + os.unlink(trial) + reverted += 1 + if not progressed: + break + + vf, uf, _ = drc(str(work)) + print(f"\n result {kept} stitched, {reverted} rejected by DRC") + print(f" {v0} -> {vf} violation(s), {u0} -> {uf} unconnected") + if vf > v0 or uf >= u0: + print(" NOTE not an improvement; discard this file") + print(f" wrote {work}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/hardware/courant/tsconfig.json b/hardware/courant/tsconfig.json new file mode 100644 index 0000000..560de7e --- /dev/null +++ b/hardware/courant/tsconfig.json @@ -0,0 +1,23 @@ +{ + "compilerOptions": { + "target": "ES2023", + "module": "ESNext", + "moduleResolution": "Bundler", + "jsx": "react-jsx", + "jsxImportSource": "react", + "strict": true, + "skipLibCheck": true, + "resolveJsonModule": true, + "allowImportingTsExtensions": true, + "noEmit": true, + "types": [ + "react", + "node" + ] + }, + "include": [ + "*.ts", + "*.tsx", + "scripts/*.ts" + ] +} diff --git a/hardware/panel/.backplane.json b/hardware/panel/.backplane.json new file mode 100644 index 0000000..0fef8d1 --- /dev/null +++ b/hardware/panel/.backplane.json @@ -0,0 +1,7 @@ +{ + "pcb": "design/radian_panel.kicad_pcb", + "schematic": "design/radian_panel.kicad_sch", + "gerbers": [ + "fab" + ] +} diff --git a/hardware/panel/INTEGRATION.md b/hardware/panel/INTEGRATION.md new file mode 100644 index 0000000..01393cc --- /dev/null +++ b/hardware/panel/INTEGRATION.md @@ -0,0 +1,12 @@ +# RADIAN Panel P1 — integration status, 2026-09-17 + +The current panel is the six-pot direct-stack revision. Native KiCad 10.0.6 ERC, DRC, filled-zone connectivity and schematic/PCB parity all pass with zero findings. + +The panel no longer connects to the mainboard through individual function harnesses. J100 and J101 are Samtec IPS1-110-01-L-D sockets that mate directly with mainboard J17/J18 Samtec IPT1-110-06-L-D terminal strips. The two 20-pin interfaces carry power, six pot controls, CV/gate, audio, encoder/MODE/LEDs, MIDI and service/JTAG. Only truly off-board functions such as the retained MIDI DIN and desktop inlet still use short leads. + +`../stack/panel-stack.json` defines the common pin map, pad geometry and mechanical stack: 19.99 mm fully mated, 20.45 mm maximum and ~20.0 mm nominal support spacing. Standoffs/support hardware, not the connectors, must carry structural load. + +Current fabrication-format outputs are in `fab/` and `radian_panel-fab.zip`; current reports are in `reports/native/`. They are engineering outputs. Real connector seating, enclosure tolerances, support hardware, power/load/thermal/fault behaviour and hardware bring-up remain first-article checks. + +## Mechanical integration +The reference enclosure CAD is synchronized to STACK-P2: the two-row six-control surface, MODE on its raised insert, shifted mainboard/support planes, and drawing-derived **20-contact Samtec IPT1/IPS1 models** on both boards. `../stack/validate_direct_stack.py` verifies all 40 contacts pin-by-pin for physical XY, pin number, signal net, drill size, board side and attached 3D model. The assembled CAD also checks every modeled panel component/pin envelope against the mainboard assembly and reports no unintended panel↔mainboard clash. Samtec's rounded REF dimensions close the housing interface by 0.01 mm in the reference solids; the official mated-view values independently give 3.82 mm nominal geometric insertion and 0.84 mm contact wipe. Physical first-article tolerance/retention remains required. diff --git a/hardware/panel/NATIVE_BASELINE.json b/hardware/panel/NATIVE_BASELINE.json new file mode 100644 index 0000000..99ddf50 --- /dev/null +++ b/hardware/panel/NATIVE_BASELINE.json @@ -0,0 +1,6 @@ +{ + "authoritative_board": "design/radian_panel.kicad_pcb", + "sha256": "9ddd199c1c5e68db47bafff481415ce4db48de8bb185d7cad0d8c10a837b4292", + "policy": "Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.", + "review_only": true +} diff --git a/hardware/panel/README.md b/hardware/panel/README.md new file mode 100644 index 0000000..d3b7b9e --- /dev/null +++ b/hardware/panel/README.md @@ -0,0 +1,26 @@ +# RADIAN / PANEL P1 — direct-stack six-control revision + +**One panel/interface PCB for the RADIAN FPGA mainboard. Engineering prototype; native electrical/PCB checks are clean, but physical hardware validation is still required.** + +Open `design/radian_panel.kicad_pro` with KiCad 10 and keep the project-local symbols/footprints with it. The authoritative panel PCB passes native ERC, DRC, filled-zone connectivity and schematic/PCB parity with zero findings. Current review fabrication outputs are in `fab/` and `radian_panel-fab.zip`. + +## Current architecture +- Four-layer panel PCB, 1.6 mm thick, about 180.5 × 108 mm, with DIN/ventilation reliefs. +- Six Bourns 10 kOhm pots: **TENSION · DECAY · CHAOS · DRIVE · DELAY · REVERB**. +- Push encoder, MODE switch, four LEDs and five vertical mono patch jacks. +- Rack +12 V and desktop 12 V feed the panel converter; the mainboard still receives regulated VIN5. +- Rack input remains a 10-pin module-side Eurorack connector; −12 V is unused. +- Default MOD bypass preserves the original unipolar behavior; the optional bipolar MOD path still requires firmware calibration. +- PITCH scaling and stereo line-level outputs are unchanged. + +## Direct panel-to-mainboard connection +The old J101…J116 cable-header bundle is retired. The boards now connect directly through two 2×10, 2.54 mm mezzanine pairs: +- **J17 main ↔ J100 panel:** Samtec IPT1-110-06-L-D ↔ IPS1-110-01-L-D, carrying VIN5/GND/VREF25, six pot wipers, CV/gate and stereo audio. +- **J18 main ↔ J101 panel:** the same Samtec pair, carrying 3V3/GND, encoder, MODE, LEDs, MIDI, PROGRAM/RESET and JTAG. + +The shared source of truth is `../stack/panel-stack.json`. It specifies 19.99 mm fully mated spacing, 20.45 mm maximum spacing and a ~20.0 mm support-stack target. Standoffs/supports carry structural load; the connectors are not structural fasteners. + +The final native boards have 40/40 mating pins matched by net and assembled XY, with 1.02 mm mainboard drills and 1.04 mm panel drills. Exact connector MPNs are present in both BOMs. Real connector seating, retention and enclosure tolerance still require a physical first article. + +## Case / enclosure +The retained desktop/Eurorack enclosure has been revised to match this panel. The old three macro holes are closed, six current control locations are present, MODE moves to (154, 57) mm, and the old raised MODE insert becomes the REVERB insert. The mainboard/support plane is shifted 0.46 mm for the 19.99 mm fully-mated Samtec stack. See `cad/RADIAN_P1_desktop_fit_study.step` and `reports/CASE_UPDATE.md`. diff --git a/hardware/panel/cad/RADIAN_P1_fit_template.stl b/hardware/panel/cad/RADIAN_P1_fit_template.stl new file mode 100644 index 0000000..4530605 Binary files /dev/null and b/hardware/panel/cad/RADIAN_P1_fit_template.stl differ diff --git a/hardware/panel/cad/RADIAN_panel_P1_outline_reference.dxf b/hardware/panel/cad/RADIAN_panel_P1_outline_reference.dxf new file mode 100644 index 0000000..bd2b185 --- /dev/null +++ b/hardware/panel/cad/RADIAN_panel_P1_outline_reference.dxf @@ -0,0 +1,7098 @@ + 0 +SECTION + 2 +HEADER + 9 +$ACADVER + 1 +AC1018 + 9 +$HANDSEED + 5 +FFFFFFFF + 9 +$ANGBASE + 50 +0.0 + 9 +$ANGDIR + 70 +1 + 9 +$MEASUREMENT + 70 +1 + 9 +$INSUNITS + 70 +4 + 0 +ENDSEC + 0 +SECTION + 2 +TABLES + 0 +TABLE + 2 +APPID + 5 +1 +330 +0 +100 +AcDbSymbolTable + 70 +1 + 0 +APPID + 5 +2 +330 +1 +100 +AcDbSymbolTableRecord +100 +AcDbRegAppTableRecord + 2 +ACAD + 70 +0 + 0 +ENDTAB + 0 +TABLE + 2 +LTYPE + 5 +3 +330 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Your use of this data constitutes your acceptance of the terms and conditions set forth below. +The information within the data (“Information”) has been provided to you free of charge for your use according to the terms of the Creative Commons Attribution-ShareAlike 4.0 International Public License and remains the sole property of Würth Elektronik eiSos GmbH & Co. KG. While Würth Elektronik eiSos GmbH & Co. KG has used reasonable efforts to ensure its accuracy, Würth Elektronik eiSos GmbH & Co. KG. does not guarantee that it is error-free, nor makes any other representation, warranty or guarantee that the Information is completely accurate or up-to-date. In many cases, the Information has been simplified to remove proprietary detail while maintaining critical interface geometric detail for your use. Würth Elektronik eiSos GmbH & Co. KG expressly disclaims all implied warranties regarding this Information, including but not limited to any implied warranties or merchantability or fitness for a purpose. This also applies if you translate, alter, arrange, transform, or otherwise modify the Information in any way, shape or form. +Würth Elektronik eiSos GmbH & Co. KG will in no case be liable for your use, or the results of your use, of the Information or any accompanying written materials. IT IS YOUR RESPONSIBILITY TO VERIFY THE RESULTS OF YOUR USE OF THIS INFORMATION IN YOUR OWN PARTICULAR ENGINEERING AND PRODUCT ENVIRONMENT AND YOU ASSUME THE ENTIRE RISK OF DOING SO OR FAILING TO DO SO. IN NO CASE WILL WÜRTH ELEKTRONIK EISOS GMBH & CO. KG BE LIABLE FOR YOUR USE, OR THE RESULTS OF YOUR USE OF THE INFORMATION OR ANY ACCOMPANYING WRITTEN MATERIAL IF YOU TRANSLATE, ALTER, ARRANGE, TRANSFORM, OR OTHERWISE MODIFY THE INFORMATION IN ANY WAY, SHAPE OR FORM. +In no event will Würth Elektronik eiSos GmbH & Co. KG or its contractors, directors, officers, employees, affiliates or distributors be liable for any direct, indirect, special, incidental or consequential damages (including but not limited to, damages for lost business, lost profits, business interruptions and loss of information) arising from your use of, or your inability to use the Information or any accompanying written materials, even if Würth Elektronik eiSos GmbH & Co. KG has been advised of the possibility of such damages. +Würth Elektronik eiSos GmbH & Co. KG reserves the right to change any portion of the Information at any time without notice. You are obliged to use the Information in accordance with the Creative Commons Attribution-ShareAlike 4.0 International Public License. The following exception to the Creative Commons Attribution-ShareAlike 4.0 International Public License applies to your use of the Information: To the extent that the creation of electronic designs that use 'Licensed Material' can be considered to be 'Adapted Material', then the copyright holder waives article 3 of the license with respect to these designs and any generated files which use data provided as part of the 'Licensed Material'. You are free to use the library data in your own projects without the obligation to share your project files under this or any other license agreement. However, if you wish to redistribute these libraries, or parts thereof (including in modified form) as a collection then the exception above does not apply. diff --git a/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_SMD_Wurth.pretty/J_Wurth_WR-BHD_61230820621.kicad_mod b/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_SMD_Wurth.pretty/J_Wurth_WR-BHD_61230820621.kicad_mod new file mode 100644 index 0000000..29f4947 --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_SMD_Wurth.pretty/J_Wurth_WR-BHD_61230820621.kicad_mod @@ -0,0 +1,243 @@ +(footprint "J_Wurth_WR-BHD_61230820621" + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (layer "F.Cu") + (descr "2.54 mm Male SMT Box Header, body 17.8x9.5x10mm, https://www.we-online.com/en/components/products/datasheet/61230820621?ki") + (tags "SMT") + (property "Reference" "REF**" + (at 0 -10.16 0) + (unlocked yes) + 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b/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_61202021621.kicad_mod new file mode 100644 index 0000000..f0caf03 --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_61202021621.kicad_mod @@ -0,0 +1,329 @@ +(footprint "J_Wurth_WR-BHD_61202021621" + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (layer "F.Cu") + (descr "2.54 mm Male Box Header, body 33.06x9.1x12.1mm, https://www.we-online.com/en/components/products/datasheet/61202021621?ki") + (tags "THT") + (property "Reference" "REF**" + (at 1.27 -6.35 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "3b456430-352e-4c99-aa72-3994bf520101") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "J_Wurth_WR-BHD_61202021621" + (at 1.27 29.21 0) + (unlocked yes) + (layer "F.Fab") + (uuid "f37cde21-b229-430c-9910-087ff8e54c63") + (effects + (font + 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b/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_61204022821.kicad_mod @@ -0,0 +1,489 @@ +(footprint "J_Wurth_WR-BHD_61204022821" + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (layer "F.Cu") + (descr "2.54 mm Male Box Header with long lever, body 70.3x8.3x31.2mm, https://www.we-online.com/en/components/products/datasheet/61204022821?ki") + (tags "THT") + (property "Reference" "REF**" + (at 1.57 -20.955 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "a82e3561-487b-451b-a4aa-a4b438defead") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "J_Wurth_WR-BHD_61204022821" + (at 1.27 61.595 0) + (unlocked yes) + (layer "F.Fab") + (uuid "ed506b45-27fa-4df0-8941-52941dfd712f") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at -3.145 5.08 270) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid 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b/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_612040235221.kicad_mod @@ -0,0 +1,477 @@ +(footprint "J_Wurth_WR-BHD_612040235221" + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (layer "F.Cu") + (descr "Male Angled Box Header High Temperature, body 58.4x12.94x12.2mm, https://www.we-online.com/en/components/products/datasheet/612040235221?ki") + (tags "THT") + (property "Reference" "REF**" + (at 8.89 -6.35 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "a5fd1159-0c51-48ba-920c-24afeb7e42c0") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "J_Wurth_WR-BHD_612040235221" + (at 8.54 54.61 0) + (unlocked yes) + (layer "F.Fab") + (uuid "ff9e5662-a6df-4492-a097-b3ea4b84198f") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 13.255 2.54 90) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid 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+) diff --git a/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_612050235121.kicad_mod b/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_612050235121.kicad_mod new file mode 100644 index 0000000..a72250c --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_612050235121.kicad_mod @@ -0,0 +1,569 @@ +(footprint "J_Wurth_WR-BHD_612050235121" + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (layer "F.Cu") + (descr "2.54 mm Male Box Header High Temperature, body 71.1x9.05x12mm, https://www.we-online.com/en/components/products/datasheet/612050235121?ki") + (tags "THT") + (property "Reference" "REF**" + (at 1.27 -6.35 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "69404605-9b63-4e84-a3d5-227c437a92ea") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + 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a/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_612050235221.kicad_mod b/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_612050235221.kicad_mod new file mode 100644 index 0000000..ea85c35 --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_612050235221.kicad_mod @@ -0,0 +1,557 @@ +(footprint "J_Wurth_WR-BHD_612050235221" + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (layer "F.Cu") + (descr "Male Angled Box Header High Temperature, body 71.1x12.94x12.2mm, https://www.we-online.com/en/components/products/datasheet/612050235221?ki") + (tags "THT") + (property "Reference" "REF**" + (at 8.89 -6.35 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "a5fd1159-0c51-48ba-920c-24afeb7e42c0") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property 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+ ) + (rotate + (xyz 0 0 0) + ) + ) +) diff --git a/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_62504421721.kicad_mod b/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_62504421721.kicad_mod new file mode 100644 index 0000000..c9a3186 --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_62504421721.kicad_mod @@ -0,0 +1,548 @@ +(footprint "J_Wurth_WR-BHD_62504421721" + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (layer "F.Cu") + (descr "2.00 mm Male Angled Box Header, body 51.25x8.7x8.5mm, https://www.we-online.com/en/components/products/datasheet/62504421721?ki") + (tags "THT") + (property "Reference" "REF**" + (at 5.6 -6 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "303f9e8b-f38f-4173-96d3-ea610c66e8b1") + (effects + (font + (size 1 1) + (thickness 0.15) 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a/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_62504422021.kicad_mod b/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_62504422021.kicad_mod new file mode 100644 index 0000000..b5ae3ad --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-BHD_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-BHD_62504422021.kicad_mod @@ -0,0 +1,510 @@ +(footprint "J_Wurth_WR-BHD_62504422021" + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (layer "F.Cu") + (descr "2.00 mm Male Box Header with Lever, body 59.7x6x18.85mm, https://www.we-online.com/en/components/products/datasheet/62504422021?ki") + (tags "THT") + (property "Reference" "REF**" + (at 1 -19 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "e5c84944-cf5c-4a7f-be97-4eac06ef720b") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" 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(size 1.27 1.27) + ) + ) + ) + ) + ) + (embedded_fonts no) + ) +) diff --git a/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/Disclaimer_READ_ME.txt b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/Disclaimer_READ_ME.txt new file mode 100644 index 0000000..dfd6f4a --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/Disclaimer_READ_ME.txt @@ -0,0 +1,7 @@ +Disclaimer + +Please carefully read the disclaimer before using any of this data. Your use of this data constitutes your acceptance of the terms and conditions set forth below. +The information within the data (“Information”) has been provided to you free of charge for your use according to the terms of the Creative Commons Attribution-ShareAlike 4.0 International Public License and remains the sole property of Würth Elektronik eiSos GmbH & Co. KG. While Würth Elektronik eiSos GmbH & Co. KG has used reasonable efforts to ensure its accuracy, Würth Elektronik eiSos GmbH & Co. KG. does not guarantee that it is error-free, nor makes any other representation, warranty or guarantee that the Information is completely accurate or up-to-date. In many cases, the Information has been simplified to remove proprietary detail while maintaining critical interface geometric detail for your use. Würth Elektronik eiSos GmbH & Co. KG expressly disclaims all implied warranties regarding this Information, including but not limited to any implied warranties or merchantability or fitness for a purpose. This also applies if you translate, alter, arrange, transform, or otherwise modify the Information in any way, shape or form. +Würth Elektronik eiSos GmbH & Co. KG will in no case be liable for your use, or the results of your use, of the Information or any accompanying written materials. IT IS YOUR RESPONSIBILITY TO VERIFY THE RESULTS OF YOUR USE OF THIS INFORMATION IN YOUR OWN PARTICULAR ENGINEERING AND PRODUCT ENVIRONMENT AND YOU ASSUME THE ENTIRE RISK OF DOING SO OR FAILING TO DO SO. IN NO CASE WILL WÜRTH ELEKTRONIK EISOS GMBH & CO. KG BE LIABLE FOR YOUR USE, OR THE RESULTS OF YOUR USE OF THE INFORMATION OR ANY ACCOMPANYING WRITTEN MATERIAL IF YOU TRANSLATE, ALTER, ARRANGE, TRANSFORM, OR OTHERWISE MODIFY THE INFORMATION IN ANY WAY, SHAPE OR FORM. +In no event will Würth Elektronik eiSos GmbH & Co. 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The following exception to the Creative Commons Attribution-ShareAlike 4.0 International Public License applies to your use of the Information: To the extent that the creation of electronic designs that use 'Licensed Material' can be considered to be 'Adapted Material', then the copyright holder waives article 3 of the license with respect to these designs and any generated files which use data provided as part of the 'Licensed Material'. You are free to use the library data in your own projects without the obligation to share your project files under this or any other license agreement. However, if you wish to redistribute these libraries, or parts thereof (including in modified form) as a collection then the exception above does not apply. diff --git a/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_SMD_Wurth.pretty/J_Wurth_WR-DC_694103107102.kicad_mod b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_SMD_Wurth.pretty/J_Wurth_WR-DC_694103107102.kicad_mod new file mode 100644 index 0000000..0e6e666 --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_SMD_Wurth.pretty/J_Wurth_WR-DC_694103107102.kicad_mod @@ -0,0 +1,51 @@ +(footprint "J_Wurth_WR-DC_694103107102" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "DC Power Jacks, body 9.3x8x5.3mm, https://www.we-online.com/en/components/products/datasheet/694103107102?ki") + (tags "SMT") + (attr smd) + (fp_text reference "REF**" (at 0 -6.6 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 3d8f7c84-16bb-46a1-a61a-ded1f582ebc9) + ) + (fp_text value "J_Wurth_WR-DC_694103107102" (at 0 6.6 unlocked) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 4ce620bf-b645-4233-a18a-0875ffa14a4d) + ) + (fp_text user "${REFERENCE}" (at 0 0 unlocked) (layer "F.Fab") + (effects (font (size 0.5 0.5) (thickness 0.075))) + (tstamp 2f960cf8-7802-41ae-9025-cc58de6252ee) + ) + (fp_line (start -5.4 2.9) (end -5.4 -2.5) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 35d36a3b-25de-4992-8833-f1880388e871)) + (fp_line (start -5 -5.985) (end -3 -5.985) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 49ff5a1e-65b8-4996-be77-68611db31dbc)) + (fp_line (start -2.6 -4.1) (end -0.9 -4.1) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 8c773212-c83f-455f-b7cf-2064cb91487f)) + (fp_line (start -2.6 4.1) (end -0.9 4.1) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 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(layer "F.Fab") (tstamp dbf95b23-dc9e-49b3-bfeb-011c78b546a1)) + (pad "" np_thru_hole circle (at -2.5 0 90) (size 1 1) (drill 1) (layers "*.Cu" "*.Mask") (tstamp 36d8fbc5-b496-4d9f-a15a-7f458082c62a)) + (pad "" np_thru_hole circle (at 2.5 0 90) (size 1 1) (drill 1) (layers "*.Cu" "*.Mask") (tstamp e79fb02b-921c-46ee-be87-996dcfe65ec7)) + (pad "1" smd rect (at -4 -3.9) (size 2.2 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 9a512f6f-71ac-4c58-92b7-4e15c1542a4b)) + (pad "1" smd rect (at 0.5 -3.9) (size 2.2 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 5eddff13-f7d0-4fd1-8b20-2a09ad878351)) + (pad "2" smd rect (at 0.5 4.3 90) (size 2.2 2.2) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp eeff9bfc-2332-405f-ba7c-e674fbef9cc5)) + (pad "3" smd rect (at -4 4.3 90) (size 2.2 2.2) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 43885fde-ddcb-4ee6-903d-b85e30862b74)) + (model "${WE_3DMODEL_DIR}/Connector_SMD_Wurth.3dshapes/J_Wurth_WR-DC_694103107102.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_SMD_Wurth.pretty/J_Wurth_WR-DC_694106105102.kicad_mod b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_SMD_Wurth.pretty/J_Wurth_WR-DC_694106105102.kicad_mod new file mode 100644 index 0000000..85db40d --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_SMD_Wurth.pretty/J_Wurth_WR-DC_694106105102.kicad_mod @@ -0,0 +1,58 @@ +(footprint "J_Wurth_WR-DC_694106105102" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "DC Power Jacks, body 15.2x17x11mm, https://www.we-online.com/en/components/products/datasheet/694106105102?ki") + (tags "SMT") + (attr smd) + (fp_text reference "REF**" (at 0 -15.5 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e6085eeb-5b76-4e1d-ae44-56c9c2ae7b1f) + ) + (fp_text value "J_Wurth_WR-DC_694106105102" (at 0 5 unlocked) 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a/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_SMD_Wurth.pretty/J_Wurth_WR-DC_694108105102.kicad_mod b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_SMD_Wurth.pretty/J_Wurth_WR-DC_694108105102.kicad_mod new file mode 100644 index 0000000..3b75ce5 --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_SMD_Wurth.pretty/J_Wurth_WR-DC_694108105102.kicad_mod @@ -0,0 +1,58 @@ +(footprint "J_Wurth_WR-DC_694108105102" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "DC Power Jacks, body 15.2x17x11mm, https://www.we-online.com/en/components/products/datasheet/694108105102?ki") + (tags "SMT") + (attr smd) + (fp_text reference "REF**" (at 0 -15.5 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp a589f1ce-0bde-418e-9e75-f740047062ca) + ) + (fp_text value "J_Wurth_WR-DC_694108105102" (at 0 5 unlocked) (layer "F.Fab") hide + (effects (font (size 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a/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694102303002.kicad_mod b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694102303002.kicad_mod new file mode 100644 index 0000000..a03c322 --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694102303002.kicad_mod @@ -0,0 +1,48 @@ +(footprint "J_Wurth_WR-DC_694102303002" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "DC Power Jacks, body 5x11.1x7.4mm, https://www.we-online.com/en/components/products/datasheet/694102303002?ki") + (tags "THT") + (attr smd) + (fp_text reference "REF**" (at 0 -1.9 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 6810e301-1d37-481d-94ba-9d36c2a1c678) + ) + (fp_text value "J_Wurth_WR-DC_694102303002" (at 0 12.2 unlocked) (layer "F.Fab") hide + (effects (font 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a/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694105309102.kicad_mod b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694105309102.kicad_mod new file mode 100644 index 0000000..7874076 --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694105309102.kicad_mod @@ -0,0 +1,71 @@ +(footprint "J_Wurth_WR-DC_694105309102" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "DC Power Jacks, body 10x11.7x9.1mm, https://www.we-online.com/en/components/products/datasheet/694105309102?ki") + (tags "THT") + (attr smd) + (fp_text reference "REF**" (at 0 -2.5 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 3c68e9b8-97d4-4277-af14-cc0016a2741f) + ) + (fp_text value "J_Wurth_WR-DC_694105309102" (at 0 15 unlocked) (layer "F.Fab") hide + (effects (font (size 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(tstamp 1f99a4b9-e9c3-4262-b217-504c19ba6b96)) + (pad "" thru_hole oval (at -7.2 9.5) (size 1.6 2.9) (drill oval 1 2.3) (layers "*.Cu" "*.Mask") (tstamp 1da72592-0b4e-49c2-927c-8860c2f7b1d4)) + (pad "" smd rect (at 0 -0.25) (size 5.4 3) (layers "F.Paste") (tstamp df7d74e4-9817-4d4a-b279-55cb4fcc2604)) + (pad "" thru_hole oval (at 5.5 9.5) (size 1.6 2.9) (drill oval 1 2.3) (layers "*.Cu" "*.Mask") (tstamp 84f13ee0-be38-42d1-aadf-35ae1e36e2e3)) + (pad "" smd rect (at 6.15 1.99) (size 3.3 5) (layers "F.Paste") (tstamp d986a0ae-fcb9-4f4d-998a-1e3129855268)) + (pad "" smd rect (at 6.2 9.15) (size 3.3 8) (layers "F.Paste") (tstamp a4d3ea13-6185-4c20-839f-d21138870b67)) + (pad "1" thru_hole rect (at 0 0) (size 2.2 2.2) (drill 1.6) (layers "*.Cu" "*.Mask") (tstamp 2ba195a2-8ed5-4b38-aaea-c8cad2dc9a5b)) + (pad "2" thru_hole oval (at -7.1 2.9) (size 1.4 2.9) (drill oval 0.8 2.3) (layers "*.Cu" "*.Mask") (tstamp 6a63c241-53e0-42af-b43d-4c98ad972f5a)) + (pad "3" thru_hole oval (at 5.5 2.7) (size 1.4 2.9) (drill oval 0.8 2) (layers "*.Cu" "*.Mask") (tstamp 035cfee2-4870-4f9c-91be-fd20391f5eb7)) + (model "${WE_3DMODEL_DIR}/Connector_THT_Wurth.3dshapes/J_Wurth_WR-DC_694105309102.step" hide + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694106301002.kicad_mod b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694106301002.kicad_mod new file mode 100644 index 0000000..0653978 --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694106301002.kicad_mod @@ -0,0 +1,46 @@ +(footprint "J_Wurth_WR-DC_694106301002" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "DC Power Jacks, body 9x14.5x10.7mm, https://www.we-online.com/en/components/products/datasheet/694106301002?ki") + (tags "THT") + (attr smd) + (fp_text reference "REF**" (at 0 -2.3 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 11e72b99-c20e-49b9-8429-e68d18c99c58) + ) + (fp_text value "J_Wurth_WR-DC_694106301002" (at 0 14.9 unlocked) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 5f0a7b28-2b9d-4596-b8a0-550fe52756ca) + ) + (fp_text user "${REFERENCE}" (at 0 -0.1 unlocked) (layer "F.Fab") + (effects (font (size 0.5 0.5) (thickness 0.075))) + (tstamp 1ed7d923-a93d-40da-b9c6-f9803bc2c6f6) + ) + (fp_line (start -4.6 -1.1) (end -4.6 13.6) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 6c0e43a9-8c16-449f-aa67-3e5750eadf88)) + (fp_line (start -4.6 -1.1) (end 4.6 -1.1) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 658a8b38-d01e-4564-8780-12ef81f793e9)) + (fp_line (start -4.6 13.6) (end 4.6 13.6) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 1a4e4ee0-6fb5-4fdf-b663-f95325e19369)) + (fp_line (start -0.5 -1.585) (end 0.5 -1.585) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 7d0cd6c9-849c-4584-aff5-59d6ab28e13e)) + (fp_line (start 4.6 -1.1) (end 4.6 0.79) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp a3e41fbf-05b1-47bb-a14d-b2378323df69)) + (fp_line (start 4.6 5.11) (end 4.6 13.6) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 3d0454ef-913c-44f6-8bdc-ab3cfce35e36)) + (fp_rect (start -5 -1.5) (end 5.95 14) + (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd") (tstamp 33c400f5-92d1-4cbf-98af-2414fb823cd1)) + (fp_line (start -0.5 -1) (end 0 -0.2) + (stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp dbbe4b44-539b-4e0b-abcc-94c6cb23d2bb)) + (fp_line (start 0.5 -1) (end 0 -0.2) + (stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp 90a57cad-4816-4154-b386-a0a345094c73)) + (fp_rect (start -4.5 -1) (end 4.5 13.5) + (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab") (tstamp f526ecbe-7464-48b9-b983-8a321acf661f)) + (pad "1" thru_hole rect (at 0 0) (size 4.2 1.7) (drill oval 3.2 0.7) (layers "*.Cu" "*.Mask") (tstamp 3869a93a-8109-4bf1-ae01-d611356e8b6b)) + (pad "2" thru_hole oval (at 0 5.8) (size 3.8 1.7) (drill oval 2.8 0.7) (layers "*.Cu" "*.Mask") (tstamp 8ff68860-e87c-4e3d-8790-bc6b0fd4a70c)) + (pad "3" thru_hole oval (at 4.8 2.95) (size 1.7 3.8) (drill oval 0.7 2.8) (layers "*.Cu" "*.Mask") (tstamp d869d061-abf2-488c-9604-4f26f0ed1e03)) + (model "${WE_3DMODEL_DIR}/Connector_THT_Wurth.3dshapes/J_Wurth_WR-DC_694106301002.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694106402002.kicad_mod b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694106402002.kicad_mod new file mode 100644 index 0000000..e06daaa --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694106402002.kicad_mod @@ -0,0 +1,46 @@ +(footprint "J_Wurth_WR-DC_694106402002" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "DC Power Jacks, body 9x10.7x14mm, https://www.we-online.com/en/components/products/datasheet/694106402002?ki") + (tags "THT") + (attr smd) + (fp_text reference "REF**" (at 3.5 -5.5 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e9b5894f-f357-44a8-a5c5-177c4e3b88d7) + ) + (fp_text value "J_Wurth_WR-DC_694106402002" (at 3.5 7.8 unlocked) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 8f8c1ff0-018a-4933-97e6-97134f229e89) + ) + (fp_text user "${REFERENCE}" (at 3.5 0 unlocked) (layer "F.Fab") + (effects (font (size 0.5 0.5) (thickness 0.075))) + (tstamp ed8ef6c3-b8d0-40b0-81d3-2f1fbfdc87e2) + ) + (fp_line (start -1.585 -0.5) (end -1.585 0.5) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 5ec60691-cbaf-4cc3-9756-b7e711632023)) + (fp_line (start -1.1 -4.3) (end 8.1 -4.3) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp dd2e8d6e-8772-4f1d-a2a9-64b2a67faac3)) + (fp_line (start -1.1 -2.4) (end -1.1 -4.3) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp f5acac28-b5b2-4621-a6a2-e847220df4b7)) + (fp_line (start -1.1 6.6) (end -1.1 2.4) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 46ce0d4d-1ad3-482f-a188-e7b0da61175b)) + (fp_line (start -1.1 6.6) (end 8.1 6.6) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 12e7d757-037e-4bb4-a25c-b65a434485ba)) + (fp_line (start 8.1 -4.3) (end 8.1 6.6) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp c3439e78-e5a1-4325-a768-cc7a9a767bc4)) + (fp_rect (start -1.5 -4.7) (end 8.5 7) + (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd") (tstamp 3c231fa0-c8fc-4ef8-8f95-a7f90f434f7b)) + (fp_line (start -1 -0.5) (end -0.2 0) + (stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp a3b21a41-14d2-420e-bd79-68baa0b1bc11)) + (fp_line (start -0.2 0) (end -1 0.5) + (stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp dbe006ec-bca4-4945-bcce-3ad4ac689f50)) + (fp_rect (start -1 -4.2) (end 8 6.5) + (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab") (tstamp e0bb5171-5150-4ef1-b58e-d4883fe355e6)) + (pad "1" thru_hole rect (at 0 0) (size 2 4.25) (drill oval 0.8 3.5) (layers "*.Cu" "*.Mask") (tstamp acd0eac2-2169-4691-b9a8-2b0360bf12f3)) + (pad "2" thru_hole oval (at 2.3 5.3) (size 3.5 1.8) (drill oval 2.8 0.6) (layers "*.Cu" "*.Mask") (tstamp 7698438e-6ec7-485e-8d31-e754dfe5c175)) + (pad "3" thru_hole oval (at 6 2.8) (size 3.5 1.8) (drill oval 2.8 0.6) (layers "*.Cu" "*.Mask") (tstamp b9ad64ae-6b13-4e97-9b13-59606cfe7a50)) + (model "${WE_3DMODEL_DIR}/Connector_THT_Wurth.3dshapes/J_Wurth_WR-DC_694106402002.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694108301002.kicad_mod b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694108301002.kicad_mod new file mode 100644 index 0000000..35ad661 --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694108301002.kicad_mod @@ -0,0 +1,46 @@ +(footprint "J_Wurth_WR-DC_694108301002" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "DC Power Jacks, body 15x15x15mm, https://www.we-online.com/en/components/products/datasheet/694108301002?ki") + (tags "THT") + (attr smd) + (fp_text reference "REF**" (at 0 -2.2 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp fc7f4b73-d486-48b0-b7aa-0c2c5bd7d36d) + ) + (fp_text value "J_Wurth_WR-DC_694108301002" (at 0 15 unlocked) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp d17dd00a-d78f-4e23-9cdf-b4e01efab506) + ) + (fp_text user "${REFERENCE}" (at 0 -0.1 unlocked) (layer "F.Fab") + (effects (font (size 0.5 0.5) (thickness 0.075))) + (tstamp 0c9bf13d-0195-4d29-90bd-7dc955c44931) + ) + (fp_line (start -4.6 -1.1) (end -4.6 13.6) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp d718bb72-4cee-47bb-a9e9-2436995f9420)) + (fp_line (start -4.6 -1.1) (end 4.6 -1.1) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp b6e5e8c5-fc64-48c4-9765-a147f2a31115)) + (fp_line (start -4.6 13.6) (end 4.6 13.6) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 19ca328a-aceb-40d6-a413-1ed27d615bc8)) + (fp_line (start -0.5 -1.585) (end 0.5 -1.585) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 028790d8-4e17-4fe0-8597-4c9a46590995)) + (fp_line (start 4.6 -1.1) (end 4.6 0.79) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 24658790-f095-48dd-a0db-a8b3ee03ade2)) + (fp_line (start 4.6 5.11) (end 4.6 13.6) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 6569384e-4a4b-4b0a-99b5-f5cfa8bde004)) + (fp_rect (start -5 -1.5) (end 5.95 14) + (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd") (tstamp d1c08c82-d6d0-4a1f-9d6c-3faeee63fdb9)) + (fp_line (start -0.5 -1) (end 0 -0.2) + (stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp 2b097bec-2c4c-431b-90ae-a4269832c759)) + (fp_line (start 0.5 -1) (end 0 -0.2) + (stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp 49ad2c60-9eef-4ed2-9cf2-db7c5256d2c9)) + (fp_rect (start -4.5 -1) (end 4.5 13.5) + (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab") (tstamp 47eb1b1d-eb0d-43cf-b9fc-8598bb374a1c)) + (pad "1" thru_hole rect (at 0 0) (size 4.2 1.7) (drill oval 3.2 0.7) (layers "*.Cu" "*.Mask") (tstamp 4d77da45-0ca8-460a-9090-54cabe831f7f)) + (pad "2" thru_hole oval (at 0 5.8) (size 3.8 1.7) (drill oval 2.8 0.7) (layers "*.Cu" "*.Mask") (tstamp 3f80c435-f641-4b61-89dc-ad5d269e7f88)) + (pad "3" thru_hole oval (at 4.8 2.95) (size 1.7 3.8) (drill oval 0.7 2.8) (layers "*.Cu" "*.Mask") (tstamp 10cf034d-9fc8-48f5-9338-fcb5e0d0d841)) + (model "${WE_3DMODEL_DIR}/Connector_THT_Wurth.3dshapes/J_Wurth_WR-DC_694108301002.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694108402002.kicad_mod b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694108402002.kicad_mod new file mode 100644 index 0000000..e75cac1 --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/footprints/Connector_THT_Wurth.pretty/J_Wurth_WR-DC_694108402002.kicad_mod @@ -0,0 +1,46 @@ +(footprint "J_Wurth_WR-DC_694108402002" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "DC Power Jacks, body 15x15x15mm, https://www.we-online.com/en/components/products/datasheet/694108402002?ki") + (tags "THT") + (attr smd) + (fp_text reference "REF**" (at 3.5 -5.5 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 30842166-d9ba-4839-bec1-5672f7da47b4) + ) + (fp_text value "J_Wurth_WR-DC_694108402002" (at 3.5 7.8 unlocked) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp d4e71b59-d774-438c-9bce-33eb5714d281) + ) + (fp_text user "${REFERENCE}" (at 3.5 0 unlocked) (layer "F.Fab") + (effects (font (size 0.5 0.5) (thickness 0.075))) + (tstamp 78af2209-5939-4e59-8714-00af1e06963b) + ) + (fp_line (start -1.585 -0.5) (end -1.585 0.5) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp c6bc75d6-8c6a-4b8a-8522-e943d0292a99)) + (fp_line (start -1.1 -4.3) (end 8.1 -4.3) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp e2cc1f46-7cea-43f6-b7c2-0b6598649078)) + (fp_line (start -1.1 -2.4) (end -1.1 -4.3) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 998670dd-5719-4e95-be3c-d2581458ef14)) + (fp_line (start -1.1 6.6) (end -1.1 2.4) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 99609019-9d28-40ef-94f0-be9769a95697)) + (fp_line (start -1.1 6.6) (end 8.1 6.6) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp f51bd7fd-07c0-42cf-8837-bc49c8dce89b)) + (fp_line (start 8.1 -4.3) (end 8.1 6.6) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 3e73a3ff-cd87-49a5-b113-9bc710195032)) + (fp_rect (start -1.5 -4.7) (end 8.5 7) + (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd") (tstamp 1da1f55f-0e34-40fb-949f-0b7cecfb9bed)) + (fp_line (start -1 -0.5) (end -0.2 0) + (stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp df26c23a-1d9d-4f01-98cd-950d224dde0d)) + (fp_line (start -0.2 0) (end -1 0.5) + (stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp c55384f5-917a-4efd-bab3-40b28c5dc057)) + (fp_rect (start -1 -4.2) (end 8 6.5) + (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab") (tstamp 07983999-a66a-4791-8ae3-7a8de410a3df)) + (pad "1" thru_hole rect (at 0 0) (size 2 4.25) (drill oval 0.8 3.5) (layers "*.Cu" "*.Mask") (tstamp 517a3a10-3954-4dd2-a81c-dfa2fb516567)) + (pad "2" thru_hole oval (at 2.3 5.3) (size 3.5 1.8) (drill oval 2.8 0.6) (layers "*.Cu" "*.Mask") (tstamp 9cfa4826-49c8-4e1e-a3fb-5fe0f5927aed)) + (pad "3" thru_hole oval (at 6 2.8) (size 3.5 1.8) (drill oval 2.8 0.6) (layers "*.Cu" "*.Mask") (tstamp 054f3d0c-9072-492b-a3f6-029da67bedc3)) + (model "${WE_3DMODEL_DIR}/Connector_THT_Wurth.3dshapes/J_Wurth_WR-DC_694108402002.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/symbols/Connector_Wurth_WR-DC.kicad_sym b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/symbols/Connector_Wurth_WR-DC.kicad_sym new file mode 100644 index 0000000..ce3dca3 --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WR-DC_rev26b/symbols/Connector_Wurth_WR-DC.kicad_sym @@ -0,0 +1,2282 @@ +(kicad_symbol_lib (version 20220914) (generator kicad_symbol_editor) + (symbol "694102303002" (pin_names hide) (in_bom yes) (on_board yes) + (property "Reference" "J" (id 0) (at 0 5.08 0) + (effects (font (size 1.27 1.27))) + ) + (property "Value" "694102303002" (id 1) (at 12.7 22.86 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Footprint" "Connector_THT_Wurth:J_Wurth_WR-DC_694102303002" (id 2) (at 12.7 20.32 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Datasheet" "https://www.we-online.com/catalog/datasheet/694102303002.pdf?ki" (id 3) (at 12.7 17.78 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Manufacturer" "Wurth Elektronik" (id 4) (at 12.7 15.24 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Manufacturer URL" "https://www.we-online.com" (id 5) (at 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(property "Datasheet" "https://www.we-online.com/catalog/datasheet/694108402002.pdf?ki" (id 3) (at 12.7 17.78 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Manufacturer" "Wurth Elektronik" (id 4) (at 12.7 15.24 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Manufacturer URL" "https://www.we-online.com" (id 5) (at 12.7 12.7 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Created Date" "20251209" (id 6) (at 12.7 10.16 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Series" "WR-DC" (id 7) (at 12.7 7.62 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Part Number" "694108402002" (id 8) (at 12.7 5.08 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Mounting Technology" "THT" (id 9) (at 12.7 2.54 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Center pin Ø (Value) (mm)" "2.5" (id 10) (at 12.7 0 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Plug OD (mm)" "5.5" (id 11) (at 12.7 -2.54 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Type" "Vertical" (id 12) (at 12.7 -5.08 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "IR (A)" "3.0" (id 13) (at 12.7 -7.62 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Working Voltage (V (DC))" "30" (id 14) (at 12.7 -10.16 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "ki_keywords" "DC_POWER_JACKS_WR_DC" (id 15) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_description" "Power Jacks ED" (id 16) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_fp_filters" "*WR-DC*694108402002*" (id 17) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "694108402002_0_0" + (arc (start -3.175 2.54) (mid -4.4395 1.27) (end -3.175 0) + (stroke (width 0.1524) (type default)) + (fill (type none)) + ) + (polyline + (pts + (xy -3.81 -2.54) + (xy -4.445 -3.81) + ) + (stroke (width 0.1524) (type default)) + (fill (type none)) + ) + (polyline + (pts + (xy -3.175 -3.81) + (xy -3.81 -2.54) + ) + (stroke (width 0.1524) (type default)) + (fill (type none)) + ) + (polyline + (pts + (xy -3.175 2.54) + (xy 1.27 2.54) + ) + (stroke (width 0.1524) (type default)) + (fill (type none)) + ) + (polyline + (pts + (xy 0 -1.27) + (xy 0 -3.81) + ) + (stroke (width 0.1524) (type default)) + (fill (type none)) + ) + (polyline + (pts + (xy 0 -1.27) + (xy 2.54 -1.27) + ) + (stroke (width 0.1524) (type default)) + (fill (type none)) + ) + (polyline + (pts + (xy 1.27 -0.635) + (xy 2.54 -0.635) + ) + (stroke (width 0.1524) (type default)) + (fill (type none)) + ) + (polyline + (pts + (xy 1.27 0) + (xy -3.175 0) + ) + (stroke (width 0.1524) (type default)) + (fill (type none)) + ) + (polyline + (pts + (xy 1.27 0) + (xy 1.27 -0.635) + ) + (stroke (width 0.1524) (type default)) + (fill (type none)) + ) + (polyline + (pts + (xy 1.27 2.54) + (xy 1.27 0) + ) + (stroke (width 0.1524) (type default)) + (fill (type none)) + ) + (polyline + (pts + (xy 1.27 3.175) + (xy 1.27 2.54) + ) + (stroke (width 0.1524) (type default)) + (fill (type none)) + ) + (polyline + (pts + (xy 2.54 -3.81) + (xy -3.175 -3.81) + ) + (stroke (width 0.1524) (type default)) + (fill (type none)) + ) + (polyline + (pts + (xy 2.54 -0.635) + (xy 2.54 3.175) + ) + (stroke (width 0.1524) (type default)) + (fill (type none)) + ) + (polyline + (pts + (xy 2.54 3.175) + (xy 1.27 3.175) + ) + (stroke (width 0.1524) (type default)) + (fill (type none)) + ) + (polyline + (pts + (xy 0 -3.81) + (xy -0.508 -2.54) + (xy 0.508 -2.54) + (xy 0 -3.81) + ) + (stroke (width 0.1524) (type default)) + (fill (type outline)) + ) + ) + (symbol "694108402002_1_0" + (pin passive line (at 6.35 1.27 180) (length 3.81) + (name "1" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 6.35 -3.81 180) (length 3.81) + (name "3" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 6.35 -1.27 180) (length 3.81) + (name "2" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + ) + ) +) \ No newline at end of file diff --git a/hardware/panel/cad/models/production/KiCad_WS-SLTV_rev26b/Disclaimer_READ_ME.txt b/hardware/panel/cad/models/production/KiCad_WS-SLTV_rev26b/Disclaimer_READ_ME.txt new file mode 100644 index 0000000..dfd6f4a --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WS-SLTV_rev26b/Disclaimer_READ_ME.txt @@ -0,0 +1,7 @@ +Disclaimer + +Please carefully read the disclaimer before using any of this data. Your use of this data constitutes your acceptance of the terms and conditions set forth below. +The information within the data (“Information”) has been provided to you free of charge for your use according to the terms of the Creative Commons Attribution-ShareAlike 4.0 International Public License and remains the sole property of Würth Elektronik eiSos GmbH & Co. KG. While Würth Elektronik eiSos GmbH & Co. KG has used reasonable efforts to ensure its accuracy, Würth Elektronik eiSos GmbH & Co. KG. does not guarantee that it is error-free, nor makes any other representation, warranty or guarantee that the Information is completely accurate or up-to-date. In many cases, the Information has been simplified to remove proprietary detail while maintaining critical interface geometric detail for your use. Würth Elektronik eiSos GmbH & Co. KG expressly disclaims all implied warranties regarding this Information, including but not limited to any implied warranties or merchantability or fitness for a purpose. This also applies if you translate, alter, arrange, transform, or otherwise modify the Information in any way, shape or form. +Würth Elektronik eiSos GmbH & Co. KG will in no case be liable for your use, or the results of your use, of the Information or any accompanying written materials. IT IS YOUR RESPONSIBILITY TO VERIFY THE RESULTS OF YOUR USE OF THIS INFORMATION IN YOUR OWN PARTICULAR ENGINEERING AND PRODUCT ENVIRONMENT AND YOU ASSUME THE ENTIRE RISK OF DOING SO OR FAILING TO DO SO. IN NO CASE WILL WÜRTH ELEKTRONIK EISOS GMBH & CO. KG BE LIABLE FOR YOUR USE, OR THE RESULTS OF YOUR USE OF THE INFORMATION OR ANY ACCOMPANYING WRITTEN MATERIAL IF YOU TRANSLATE, ALTER, ARRANGE, TRANSFORM, OR OTHERWISE MODIFY THE INFORMATION IN ANY WAY, SHAPE OR FORM. +In no event will Würth Elektronik eiSos GmbH & Co. KG or its contractors, directors, officers, employees, affiliates or distributors be liable for any direct, indirect, special, incidental or consequential damages (including but not limited to, damages for lost business, lost profits, business interruptions and loss of information) arising from your use of, or your inability to use the Information or any accompanying written materials, even if Würth Elektronik eiSos GmbH & Co. KG has been advised of the possibility of such damages. +Würth Elektronik eiSos GmbH & Co. KG reserves the right to change any portion of the Information at any time without notice. You are obliged to use the Information in accordance with the Creative Commons Attribution-ShareAlike 4.0 International Public License. The following exception to the Creative Commons Attribution-ShareAlike 4.0 International Public License applies to your use of the Information: To the extent that the creation of electronic designs that use 'Licensed Material' can be considered to be 'Adapted Material', then the copyright holder waives article 3 of the license with respect to these designs and any generated files which use data provided as part of the 'Licensed Material'. You are free to use the library data in your own projects without the obligation to share your project files under this or any other license agreement. However, if you wish to redistribute these libraries, or parts thereof (including in modified form) as a collection then the exception above does not apply. diff --git a/hardware/panel/cad/models/production/KiCad_WS-SLTV_rev26b/footprints/Switch_THT_Wurth.pretty/SW_Wurth_WS-SLTV_450301014042.kicad_mod b/hardware/panel/cad/models/production/KiCad_WS-SLTV_rev26b/footprints/Switch_THT_Wurth.pretty/SW_Wurth_WS-SLTV_450301014042.kicad_mod new file mode 100644 index 0000000..f78a1ce --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WS-SLTV_rev26b/footprints/Switch_THT_Wurth.pretty/SW_Wurth_WS-SLTV_450301014042.kicad_mod @@ -0,0 +1,38 @@ +(footprint "SW_Wurth_WS-SLTV_450301014042" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "Mini Slide Switch, Opposite Side Connection 10x2.5 mm, body 10x2.5x6.4mm, https://www.we-online.com/en/components/products/datasheet/450301014042?ki") + (tags "THT") + (attr through_hole) + (fp_text reference "REF**" (at 0 -2.5 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 848b5c45-2293-4dd8-ab8d-71a16feda60a) + ) + (fp_text value "SW_Wurth_WS-SLTV_450301014042" (at 0 2.5 unlocked) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 2d76e583-558a-4861-ac6d-43d44d683dc2) + ) + (fp_text user "${REFERENCE}" (at 0 0 unlocked) (layer "F.Fab") + (effects (font (size 0.5 0.5) (thickness 0.075))) + (tstamp 2f5a3520-a232-4079-a5d0-7773cb434782) + ) + (fp_line (start -0.4 -1.585) (end 0.4 -1.585) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 629c20b6-60e7-44a4-aee2-d920cea6a665)) + (fp_rect (start -5.11 -1.36) (end 5.11 1.36) + (stroke (width 0.12) (type solid)) (fill none) (layer "F.SilkS") (tstamp beca020c-dd2e-40dd-a395-62d8c41e0de9)) + (fp_rect (start -5.25 -1.5) (end 5.25 1.5) + (stroke (width 0.05) (type solid)) (fill none) (layer "F.CrtYd") (tstamp 70ceb2a6-8f24-463b-9607-1594069ac329)) + (fp_line (start -0.4 -1.25) (end 0 -0.77) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 1eb76ead-0c4b-4067-aa62-63f296298c1d)) + (fp_line (start 0.4 -1.25) (end 0 -0.77) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 5e1f7129-5313-4a84-b231-fdd4d13ec615)) + (fp_rect (start -5 -1.25) (end 5 1.25) + (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp 319d0ade-9681-4a91-aaac-fe86d1bd74d0)) + (pad "1" thru_hole rect (at 0 0) (size 1.3 1.3) (drill 0.8) (layers "*.Cu" "*.Mask") (tstamp fea13788-4025-42b4-aaec-24aeb9408de5)) + (pad "2" thru_hole circle (at -2.54 0) (size 1.3 1.3) (drill 0.8) (layers "*.Cu" "*.Mask") (tstamp 32998917-0055-45e1-8b79-7c73ec3e0c4a)) + (pad "3" thru_hole circle (at 2.54 0) (size 1.3 1.3) (drill 0.8) (layers "*.Cu" "*.Mask") (tstamp 8dec20c2-0bb5-4cc9-bdac-cd0f5631b755)) + (model "${WE_3DMODEL_DIR}/Switch_THT_Wurth.3dshapes/SW_Wurth_WS-SLTV_450301014042.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/cad/models/production/KiCad_WS-SLTV_rev26b/footprints/Switch_THT_Wurth.pretty/SW_Wurth_WS-SLTV_452404020202.kicad_mod b/hardware/panel/cad/models/production/KiCad_WS-SLTV_rev26b/footprints/Switch_THT_Wurth.pretty/SW_Wurth_WS-SLTV_452404020202.kicad_mod new file mode 100644 index 0000000..e322be2 --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WS-SLTV_rev26b/footprints/Switch_THT_Wurth.pretty/SW_Wurth_WS-SLTV_452404020202.kicad_mod @@ -0,0 +1,59 @@ +(footprint "SW_Wurth_WS-SLTV_452404020202" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "Slide Switch, Same Side Connection 9.0x3.5 mm, body 3.5x9x5.5mm, https://www.we-online.com/en/components/products/datasheet/452404020202?ki") + (tags "THT") + (attr through_hole) + (fp_text reference "REF**" (at 1.65 -3.25 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 9b7ac7b2-896b-4622-aad2-48b3e90c8109) + ) + (fp_text value "SW_Wurth_WS-SLTV_452404020202" (at 1.65 8.25 unlocked) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp f604e3f0-9973-44d5-94ca-7f17f6f77709) + ) + (fp_text user "${REFERENCE}" (at 1.65 2.5 unlocked) (layer "F.Fab") + (effects (font (size 0.5 0.5) (thickness 0.075))) + (tstamp 863cacf5-05be-4d14-90c6-9634a852007f) + ) + (fp_line (start -1.035 -0.7) (end -1.035 0.7) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 60649601-c04b-4ada-a0e4-987a197b4701)) + (fp_line (start -0.21 -2.11) (end -0.21 -0.96) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 15061175-48b3-494f-add2-92ab6855224a)) + (fp_line (start -0.21 -2.11) (end 3.51 -2.11) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp d63a06e1-74cd-4693-ac89-25e5a8ea68e3)) + (fp_line (start -0.21 0.96) (end -0.21 1.54) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 995f7ee6-f544-493d-ba0b-2cd62788c303)) + (fp_line (start -0.21 3.46) (end -0.21 4.04) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 07d5fc1d-4170-46b3-abe9-5ff8ddd077bd)) + (fp_line (start -0.21 7.11) (end -0.21 5.96) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp a5f42a4e-b25d-4378-a781-3d009802ef42)) + (fp_line (start -0.21 7.11) (end 3.51 7.11) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp f9b0040a-6ece-4aa5-9809-4bd1b0c8c8be)) + (fp_line (start 3.51 -2.11) (end 3.51 -0.96) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp ff4c628e-bea2-4529-a3a4-606f8463d400)) + (fp_line (start 3.51 0.96) (end 3.51 1.54) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 874350c0-91ef-4b03-81ee-b7dace56927d)) + (fp_line (start 3.51 3.46) (end 3.51 4.04) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 617484c0-9381-4f05-9518-25e8b3579143)) + (fp_line (start 3.51 7.11) (end 3.51 5.96) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp f6c11cab-4a64-4143-80ef-40c0b490ec5f)) + (fp_rect (start -0.95 -2.25) (end 4.25 7.25) + (stroke (width 0.05) (type solid)) (fill none) (layer "F.CrtYd") (tstamp dae71a46-2e67-4e7d-a7f3-4c58b1a4e061)) + (fp_line (start -0.1 -0.7) (end 0.74 0) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 621aaad6-7b22-41fe-98a9-e96f876bdfe0)) + (fp_line (start -0.1 0.7) (end 0.74 0) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 2f3e2fa0-03a9-4e84-bd69-b15870467641)) + (fp_rect (start -0.1 -2) (end 3.4 7) + (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp 36cebcf4-6670-48f1-baa4-74879a97c248)) + (pad "1" thru_hole rect (at 0 0) (size 1.4 1.4) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp 17f369a0-5eef-49dd-aaf2-7ff128ffbd98)) + (pad "2" thru_hole circle (at 0 2.5) (size 1.4 1.4) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp 3143c4c7-92d3-4fb3-8f2b-6715d7002bee)) + (pad "3" thru_hole circle (at 0 5) (size 1.4 1.4) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp 02f5cb33-86f9-4a69-9c7f-2b7f238cd3bd)) + (pad "4" thru_hole circle (at 3.3 0) (size 1.4 1.4) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp bbf1f91a-1af2-4747-ac54-5bc1cb5a2b89)) + (pad "5" thru_hole circle (at 3.3 2.5) (size 1.4 1.4) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp 61f52469-dabc-4834-ae6c-fe13c04ff309)) + (pad "6" thru_hole circle (at 3.3 5) (size 1.4 1.4) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp 41225906-7071-4d6c-88c6-c8e457b21af4)) + (model "${WE_3DMODEL_DIR}/Switch_THT_Wurth.3dshapes/SW_Wurth_WS-SLTV_452404020202.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/cad/models/production/KiCad_WS-SLTV_rev26b/symbols/Switch_Wurth_WS-SLTV.kicad_sym b/hardware/panel/cad/models/production/KiCad_WS-SLTV_rev26b/symbols/Switch_Wurth_WS-SLTV.kicad_sym new file mode 100644 index 0000000..508398e --- /dev/null +++ b/hardware/panel/cad/models/production/KiCad_WS-SLTV_rev26b/symbols/Switch_Wurth_WS-SLTV.kicad_sym @@ -0,0 +1,217 @@ +(kicad_symbol_lib (version 20220914) (generator kicad_symbol_editor) + (symbol "450301014042" (pin_names hide) (in_bom yes) (on_board yes) + (property "Reference" "SW" (at 0 5.08 0) + (effects (font (size 1.27 1.27))) + ) + (property "Value" "450301014042" (at 12.7 22.86 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Footprint" "Switch_THT_Wurth:SW_Wurth_WS-SLTV_450301014042" (at 12.7 20.32 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Datasheet" "https://www.we-online.com/catalog/datasheet/450301014042.pdf?ki" (at 12.7 17.78 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Manufacturer" "Wurth Elektronik" (at 12.7 15.24 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Manufacturer URL" "https://www.we-online.com" (at 12.7 12.7 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Created Date" "20260312" (at 12.7 10.16 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Series" "WS-SLTV" (at 12.7 7.62 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Part Number" "450301014042" (at 12.7 5.08 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Mounting Technology" "THT" (at 12.7 2.54 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Operation Force(g)" "800 g" (at 12.7 0 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "Schematic" "SPDT" (at 12.7 -2.54 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "ki_keywords" "THT" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_description" "Mini Slide Switch, Opposite Side Connection 10x2.5 mm" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_fp_filters" "*WS-SLTV*450301014042*" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "450301014042_1_0" + (polyline + (pts + (xy -0.3556 0.4826) + (xy 1.397 2.6924) + ) + (stroke (width 0) (type solid)) + (fill (type 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(pin passive line (at 5.08 2.54 180) (length 2.54) + (name "1" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -5.08 2.54 0) (length 2.54) + (name "COM" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 5.08 0 180) (length 2.54) + (name "3" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 5.08 -2.54 180) (length 2.54) + (name "4" (effects (font (size 1.27 1.27)))) + (number "4" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -5.08 -2.54 0) (length 2.54) + (name "COM1" (effects (font (size 1.27 1.27)))) + (number "5" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 5.08 -5.08 180) (length 2.54) + (name "6" (effects (font (size 1.27 1.27)))) + (number "6" (effects (font (size 1.27 1.27)))) + ) + ) + ) +) diff --git a/hardware/panel/cad/models/production/Same_Sky_PJ-110AH/BOM.txt b/hardware/panel/cad/models/production/Same_Sky_PJ-110AH/BOM.txt new file mode 100644 index 0000000..e0d1619 --- /dev/null +++ b/hardware/panel/cad/models/production/Same_Sky_PJ-110AH/BOM.txt @@ -0,0 +1,3 @@ +3DX_Same_Sky_Supplier: Same Sky +3DX_Same_Sky_Description: 2.0 x 6.0 mm, 5.0 A, Vertical, Through Hole, Shielded, Dc Power Jack Connector +3DX_Same_Sky_Model Number: PJ-110AH diff --git a/hardware/panel/cad/models/production/Same_Sky_SD-50BV/BOM.txt b/hardware/panel/cad/models/production/Same_Sky_SD-50BV/BOM.txt new file mode 100644 index 0000000..d7b2cce --- /dev/null +++ b/hardware/panel/cad/models/production/Same_Sky_SD-50BV/BOM.txt @@ -0,0 +1,3 @@ +3DX_Same_Sky_Supplier: Same Sky +3DX_Same_Sky_Description: Din Receptacle, Vertical, PCB 5P +3DX_Same_Sky_Model Number: SD-50BV diff --git a/hardware/panel/design/controls.kicad_sch b/hardware/panel/design/controls.kicad_sch new file mode 100644 index 0000000..51224df --- /dev/null +++ b/hardware/panel/design/controls.kicad_sch @@ -0,0 +1,3121 @@ +(kicad_sch + (version 20231120) + (generator "radian_panel_generator") + (uuid "457489a2-9460-526e-a43d-77e41ace7837") + (paper "A2") + (title_block + (title "02 | FRONT-PANEL CONTROLS") + (date "2026-09-15") + (rev "P1 DRAFT") + (comment 1 "Native ERC, footprint verification and hardware testing REQUIRED")) + (lib_symbols + (symbol "RadianPanel:J100" + (pin_names + (offset 0.508)) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 29.209999999999997 0) + (effects + (font + (size 1.27 1.27)))) + (property "Value" "IPS1-110-01-L-D" + (at 0 -29.209999999999997 0) + (effects + (font + (size 1.27 1.27)))) + (property "Footprint" "RadianPanel:Stack_2x10_P2.54" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (symbol "J100_0_1" + (rectangle + (start -10.16 26.669999999999998) + (end 10.16 -26.669999999999998) + (stroke + (width 0.254) + (type default)) + (fill + (type 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Set flange height with assembly jig; envelope is not seated LED height." + (at 219.71 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "Kingbright" + (at 219.71 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 209.55 199.39) + (xy 204.47 199.39)) + (stroke + (width 0) + (type default)) + (uuid "e6ff21ee-51c8-5e90-b95a-87e56a2d0576")) + (global_label "GND" + (shape bidirectional) + (at 204.47 199.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "069b74bf-d299-5271-8364-1855e60ef048")) + (wire + (pts + (xy 229.87 199.39) + (xy 234.95 199.39)) + (stroke + (width 0) + (type default)) + (uuid "c95580d0-6c86-5e40-bf2d-8c378b9fa415")) + (global_label "LED0_A" + (shape bidirectional) + (at 234.95 199.39 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "b7fcf4ac-d86b-591e-a65a-fc641577aa28")) + (symbol + (lib_id "RadianPanel:D11") + (at 360.68 199.39 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "b36d9fe8-1d28-5e73-9188-b569959c7a35") + (property "Reference" "D11" + (at 360.68 190.31 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "VOICE 2" + (at 360.68 208.47 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:LED_D3.0_P2.54" + (at 360.68 199.39 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "L-934GD" + (at 360.68 199.39 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "113595dc-c7f4-529f-807b-d5f414844c40")) + (pin "2" + (uuid "89652a53-cad3-563b-bb01-5a66092af042")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/fe425aa9-89e9-5e5b-9592-3f1bdae47718" + (reference "D11") + (unit 1)))) + (property "Description" "3 mm LED, anode pad 2, cathode pad 1. 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Set flange height with assembly jig; envelope is not seated LED height." + (at 360.68 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "Kingbright" + (at 360.68 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 350.52 199.39) + (xy 345.44 199.39)) + (stroke + (width 0) + (type default)) + (uuid "fb86d0bc-db9c-5748-b878-62a8d04631e2")) + (global_label "GND" + (shape bidirectional) + (at 345.44 199.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "ab1a9d31-5e69-5a10-8682-70e5e9881ac9")) + (wire + (pts + (xy 370.84 199.39) + (xy 375.92 199.39)) + (stroke + (width 0) + (type default)) + (uuid "171bb763-3fea-5a8c-8a0b-6e7c0e564228")) + (global_label "LED1_A" + (shape bidirectional) + (at 375.92 199.39 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "fac1ac4c-7474-55c9-927c-eb59bb5acde1")) + (symbol + (lib_id "RadianPanel:D12") + (at 501.65 199.39 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "8581a420-1ba2-5d16-a609-c9a592c237c5") + (property "Reference" "D12" + (at 501.65 190.31 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "VOICE 3" + (at 501.65 208.47 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:LED_D3.0_P2.54" + (at 501.65 199.39 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "L-934GD" + (at 501.65 199.39 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "93846911-8b2d-5024-b8e6-3c4fde2f7fbb")) + (pin "2" + (uuid "83eb9c20-8928-5fe6-a52e-b6022580fc85")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/fe425aa9-89e9-5e5b-9592-3f1bdae47718" + (reference "D12") + (unit 1)))) + (property "Description" "3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." + (at 501.65 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "Kingbright" + (at 501.65 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 491.49 199.39) + (xy 486.41 199.39)) + (stroke + (width 0) + (type default)) + (uuid "1e559ea4-3e2c-5bcd-b3d8-95da1d197ced")) + (global_label "GND" + (shape bidirectional) + (at 486.41 199.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "4f08cd1f-5d88-58ac-83cb-08c37eca50ec")) + (wire + (pts + (xy 511.81 199.39) + (xy 516.89 199.39)) + (stroke + (width 0) + (type default)) + (uuid "1da79964-e68c-59a8-ac12-2853cf023a82")) + (global_label "LED2_A" + (shape bidirectional) + (at 516.89 199.39 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "2e856806-c28f-5e2f-a4ae-743b02dfb99c")) + (symbol + (lib_id "RadianPanel:D13") + (at 78.74 264.16 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "cb84da0a-7689-587d-8688-e97d2e4c3449") + (property "Reference" "D13" + (at 78.74 255.08 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "VOICE 4" + (at 78.74 273.24 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:LED_D3.0_P2.54" + (at 78.74 264.16 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "L-934GD" + (at 78.74 264.16 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "53f06f5d-2665-5ec2-8c1a-23d830d70e68")) + (pin "2" + (uuid "389c1e1e-baf0-52e3-a4e2-f321f578255e")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/fe425aa9-89e9-5e5b-9592-3f1bdae47718" + (reference "D13") + (unit 1)))) + (property "Description" "3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." + (at 78.74 264.16 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "Kingbright" + (at 78.74 264.16 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 68.58 264.16) + (xy 63.5 264.16)) + (stroke + (width 0) + (type default)) + (uuid "cfbefef9-8d7e-5fa0-a0da-146ea9c2bac7")) + (global_label "GND" + (shape bidirectional) + (at 63.5 264.16 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "c0e520e4-bf30-50e5-a765-ee9fcabef13c")) + (wire + (pts + (xy 88.9 264.16) + (xy 93.98 264.16)) + (stroke + (width 0) + (type default)) + (uuid "025358f0-b9cc-5e85-beec-64900091af12")) + (global_label "LED3_A" + (shape bidirectional) + (at 93.98 264.16 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "41855ab2-749e-5c76-a9c7-52324d9d6539")) + (text "No additional pot wiper RC or LED series resistors: these are already on the RADIAN mainboard." + (at 20 365 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "788a3fdc-0e51-59f7-8d4a-723b8b10eec3")) + (text "RV physical pin 1 = CCW/GND; physical pin 3 = CW/VREF25. This is not the main header pin order." + (at 20 373 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "6a3962b5-0d4b-5977-8162-19203822c196")) + (text "Encoder part changes to 20 mm shaft / 7 mm bushing. Match knob heights and verify turn direction." + (at 20 381 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "3b4643f5-8ec6-53ca-9005-596db171b081")) + (text "SW1 logic mapping depends on installed orientation and firmware. Mechanical tab pins are intentionally NC." + (at 20 389 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "c6eccb55-c407-59a5-baca-1cb3cb0fe48e"))) diff --git a/hardware/panel/design/design.json b/hardware/panel/design/design.json new file mode 100644 index 0000000..c635b19 --- /dev/null +++ b/hardware/panel/design/design.json @@ -0,0 +1,8454 @@ +{ + "config": { + "name": "RADIAN Panel / Interface", + "revision": "P1", + "status": "ENGINEERING PROTOTYPE - NOT FABRICATION RELEASE", + "pcb_front_z": -8.0, + "pcb_thickness": 1.6, + "panel_size": [ + 202.8, + 128.5, + 2.0 + ], + "mainboard_unchanged": false, + "direct_stack_revision": "STACK-P2", + "direct_stack_gap_mm": 19.99, + "layers": [ + "F.Cu", + "In1.Cu", + "In2.Cu", + "B.Cu" + ], + "inner_layers": "GND planes (native refill and DRC required)", + "outline": [ + [ + 18, + 10 + ], + [ + 162.5, + 10 + ], + [ + 162.5, + 19.5 + ], + [ + 171.5, + 19.5 + ], + [ + 171.5, + 10 + ], + [ + 198.5, + 10 + ], + [ + 198.5, + 118 + ], + [ + 171.5, + 118 + ], + [ + 171.5, + 109 + ], + [ + 162.5, + 109 + ], + [ + 162.5, + 118 + ], + [ + 18, + 118 + ] + ], + "windows": [ + [ + [ + 61, + 25 + ], + [ + 109, + 25 + ], + [ + 109, + 61 + ], + [ + 61, + 61 + ] + ], + [ + [ + 116.5, + 35.5 + ], + [ + 149.5, + 35.5 + ], + [ + 149.5, + 48.5 + ], + [ + 116.5, + 48.5 + ] + ] + ], + "mounts": [ + [ + 25, + 73, + 2.7 + ], + [ + 135, + 73, + 2.7 + ], + [ + 25, + 97, + 2.7 + ], + [ + 135, + 97, + 2.7 + ], + [ + 176.5, + 15.5, + 2.7 + ], + [ + 196.5, + 15.5, + 2.7 + ], + [ + 176.5, + 112.5, + 2.7 + ], + [ + 196.5, + 112.5, + 2.7 + ], + [ + 24, + 14, + 2.7 + ], + [ + 55, + 14, + 2.7 + ] + ], + "desktop_input": "12V regulated, centre positive via chassis-mounted Switchcraft 722A; short 2-wire harness to Molex J201", + "power_target": "5.08V nominal, up to 3A IC target, system current capability UNTESTED", + "default_mod_mode": "JP1 pin 1 common to pin 3 MOD_RAW = unipolar bypass", + "bipolar_mod": "JP1 pin 1 common to pin 2 MOD_BIPOLAR: ideal output 0.5*input+VREF25; firmware/calibration required", + "line_outputs": "Direct LINE_L and LINE_R from existing mainboard, not amplified Eurorack level", + "midi": "Same Sky SDS-50J right-angle DIN receptacle in enclosure; short 2-wire harness to Molex J306, no extra custom PCB" + }, + "parts": [ + { + "ref": "J100", + "value": "IPS1-110-01-L-D", + "x": 124.0, + "y": 61.75, + "fp": { + "pads": [ + { + "n": "1", + "x": 1.27, + "y": 11.43, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "rect", + "name": "1" + }, + { + "n": "2", + "x": -1.27, + "y": 11.43, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + }, + { + "n": "3", + "x": 1.27, + "y": 8.89, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "3" + }, + { + "n": "4", + "x": -1.27, + "y": 8.89, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "4" + }, + { + "n": "5", + "x": 1.27, + "y": 6.35, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "5" + }, + { + "n": "6", + "x": -1.27, + "y": 6.35, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "6" + }, + { + "n": "7", + "x": 1.27, + "y": 3.81, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "7" + }, + { + "n": "8", + "x": -1.27, + "y": 3.81, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "8" + }, + { + "n": "9", + "x": 1.27, + "y": 1.27, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "9" + }, + { + "n": "10", + "x": -1.27, + "y": 1.27, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "10" + }, + { + "n": "11", + "x": 1.27, + "y": -1.27, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "11" + }, + { + "n": "12", + "x": -1.27, + "y": -1.27, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "12" + }, + { + "n": "13", + "x": 1.27, + "y": -3.81, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "13" + }, + { + "n": "14", + "x": -1.27, + "y": -3.81, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "14" + }, + { + "n": "15", + "x": 1.27, + "y": -6.35, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "15" + }, + { + "n": "16", + "x": -1.27, + "y": -6.35, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "16" + }, + { + "n": "17", + "x": 1.27, + "y": -8.89, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "17" + }, + { + "n": "18", + "x": -1.27, + "y": -8.89, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "18" + }, + { + "n": "19", + "x": 1.27, + "y": -11.43, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "19" + }, + { + "n": "20", + "x": -1.27, + "y": -11.43, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "20" + } + ], + "body": [ + 4.95, + 25.78 + ], + "height": 8.51, + "name": "Stack_2x10_P2.54" + }, + "nets": { + "1": "GND", + "2": "VIN5", + "3": "VIN5", + "4": "VREF25", + "5": "GND", + "6": "POT_PITCH_RAW", + "7": "POT_DECAY_RAW", + "8": "POT_TIMBRE_RAW", + "9": "POT_DRIVE_RAW", + "10": "POT_DELAY_RAW", + "11": "POT_REVERB_RAW", + "12": "GND", + "13": "PITCH_IN", + "14": "MOD_IN", + "15": "GATE_IN", + "16": "GND", + "17": "LINE_L", + "18": "GND", + "19": "LINE_R", + "20": "GND" + }, + "side": "B", + "angle": 0, + "block": "controls", + "mpn": "IPS1-110-01-L-D", + "maker": "Samtec", + "notes": "Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity.", + "dnp": false, + "uuid": "8d29a3b6-4dc8-5d80-8428-86e24030d339" + }, + { + "ref": "J101", + "value": "IPS1-110-01-L-D", + "x": 43.0, + "y": 72.25, + "fp": { + "pads": [ + { + "n": "1", + "x": 1.27, + "y": 11.43, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "rect", + "name": "1" + }, + { + "n": "2", + "x": -1.27, + "y": 11.43, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + }, + { + "n": "3", + "x": 1.27, + "y": 8.89, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "3" + }, + { + "n": "4", + "x": -1.27, + "y": 8.89, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "4" + }, + { + "n": "5", + "x": 1.27, + "y": 6.35, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "5" + }, + { + "n": "6", + "x": -1.27, + "y": 6.35, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "6" + }, + { + "n": "7", + "x": 1.27, + "y": 3.81, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "7" + }, + { + "n": "8", + "x": -1.27, + "y": 3.81, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "8" + }, + { + "n": "9", + "x": 1.27, + "y": 1.27, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "9" + }, + { + "n": "10", + "x": -1.27, + "y": 1.27, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "10" + }, + { + "n": "11", + "x": 1.27, + "y": -1.27, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "11" + }, + { + "n": "12", + "x": -1.27, + "y": -1.27, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "12" + }, + { + "n": "13", + "x": 1.27, + "y": -3.81, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "13" + }, + { + "n": "14", + "x": -1.27, + "y": -3.81, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "14" + }, + { + "n": "15", + "x": 1.27, + "y": -6.35, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "15" + }, + { + "n": "16", + "x": -1.27, + "y": -6.35, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "16" + }, + { + "n": "17", + "x": 1.27, + "y": -8.89, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "17" + }, + { + "n": "18", + "x": -1.27, + "y": -8.89, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "18" + }, + { + "n": "19", + "x": 1.27, + "y": -11.43, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "19" + }, + { + "n": "20", + "x": -1.27, + "y": -11.43, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "20" + } + ], + "body": [ + 4.95, + 25.78 + ], + "height": 8.51, + "name": "Stack_2x10_P2.54" + }, + "nets": { + "1": "GND", + "2": "V3V3", + "3": "GND", + "4": "ENC_A_RAW", + "5": "ENC_B_RAW", + "6": "ENC_SW_RAW", + "7": "cv_select", + "8": "LED0_A", + "9": "LED1_A", + "10": "LED2_A", + "11": "LED3_A", + "12": "GND", + "13": "MIDI4", + "14": "MIDI5", + "15": "PROGRAM_B", + "16": "reset_n", + "17": "JTAG_TCK", + "18": "JTAG_TDO", + "19": "JTAG_TDI", + "20": "JTAG_TMS" + }, + "side": "B", + "angle": 90, + "block": "service", + "mpn": "IPS1-110-01-L-D", + "maker": "Samtec", + "notes": "Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity.", + "dnp": false, + "uuid": "37c3ba3a-67a8-53b0-9b31-8f009dd72af4" + }, + { + "ref": "RV1", + "value": "10k linear / TENSION", + "x": 38, + "y": 96, + "fp": { + "pads": [ + { + "n": "1", + "x": -2.5, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "1" + }, + { + "n": "2", + "x": 0, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + }, + { + "n": "3", + "x": 2.5, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "3" + }, + { + "n": "MP1", + "x": -5.3, + "y": 0, + "sx": 2.8, + "sy": 3.2, + "drill": [ + 1.8, + 2.2 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "MP1" + }, + { + "n": "MP2", + "x": 5.3, + "y": 0, + "sx": 2.8, + "sy": 3.2, + "drill": [ + 1.8, + 2.2 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "MP2" + } + ], + "body": [ + 11.4, + 11.0 + ], + "height": 7.4, + "name": "Bourns_PTV09A4_RearFacing" + }, + "nets": { + "1": "GND", + "2": "POT_PITCH_RAW", + "3": "VREF25", + "MP1": null, + "MP2": null + }, + "side": "F", + "angle": 0, + "block": "controls", + "mpn": "PTV09A-4020F-B103", + "maker": "Bourns", + "notes": "Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC.", + "dnp": false, + "uuid": "7509de8e-e60c-5e1e-9ec3-c1c2df981adc" + }, + { + "ref": "RV2", + "value": "10k linear / DECAY", + "x": 76, + "y": 96, + "fp": { + "pads": [ + { + "n": "1", + "x": -2.5, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "1" + }, + { + "n": "2", + "x": 0, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + }, + { + "n": "3", + "x": 2.5, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "3" + }, + { + "n": "MP1", + "x": -5.3, + "y": 0, + "sx": 2.8, + "sy": 3.2, + "drill": [ + 1.8, + 2.2 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "MP1" + }, + { + "n": "MP2", + "x": 5.3, + "y": 0, + "sx": 2.8, + "sy": 3.2, + "drill": [ + 1.8, + 2.2 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "MP2" + } + ], + "body": [ + 11.4, + 11.0 + ], + "height": 7.4, + "name": "Bourns_PTV09A4_RearFacing" + }, + "nets": { + "1": "GND", + "2": "POT_DECAY_RAW", + "3": "VREF25", + "MP1": null, + "MP2": null + }, + "side": "F", + "angle": 0, + "block": "controls", + "mpn": "PTV09A-4020F-B103", + "maker": "Bourns", + "notes": "Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC.", + "dnp": false, + "uuid": "feaf009e-cdb0-5dd4-a19f-e89862601cfb" + }, + { + "ref": "RV3", + "value": "10k linear / CHAOS", + "x": 114, + "y": 96, + "fp": { + "pads": [ + { + "n": "1", + "x": -2.5, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "1" + }, + { + "n": "2", + "x": 0, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + }, + { + "n": "3", + "x": 2.5, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "3" + }, + { + "n": "MP1", + "x": -5.3, + "y": 0, + "sx": 2.8, + "sy": 3.2, + "drill": [ + 1.8, + 2.2 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "MP1" + }, + { + "n": "MP2", + "x": 5.3, + "y": 0, + "sx": 2.8, + "sy": 3.2, + "drill": [ + 1.8, + 2.2 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "MP2" + } + ], + "body": [ + 11.4, + 11.0 + ], + "height": 7.4, + "name": "Bourns_PTV09A4_RearFacing" + }, + "nets": { + "1": "GND", + "2": "POT_TIMBRE_RAW", + "3": "VREF25", + "MP1": null, + "MP2": null + }, + "side": "F", + "angle": 0, + "block": "controls", + "mpn": "PTV09A-4020F-B103", + "maker": "Bourns", + "notes": "Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC.", + "dnp": false, + "uuid": "6050cafe-321e-5010-9ad6-cdd72088f2d6" + }, + { + "ref": "RV4", + "value": "10k linear / DRIVE", + "x": 66, + "y": 70, + "fp": { + "pads": [ + { + "n": "1", + "x": -2.5, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "1" + }, + { + "n": "2", + "x": 0, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + }, + { + "n": "3", + "x": 2.5, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "3" + }, + { + "n": "MP1", + "x": -5.3, + "y": 0, + "sx": 2.8, + "sy": 3.2, + "drill": [ + 1.8, + 2.2 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "MP1" + }, + { + "n": "MP2", + "x": 5.3, + "y": 0, + "sx": 2.8, + "sy": 3.2, + "drill": [ + 1.8, + 2.2 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "MP2" + } + ], + "body": [ + 11.4, + 11.0 + ], + "height": 7.4, + "name": "Bourns_PTV09A4_RearFacing" + }, + "nets": { + "1": "GND", + "2": "POT_DRIVE_RAW", + "3": "VREF25", + "MP1": null, + "MP2": null + }, + "side": "F", + "angle": 0, + "block": "controls", + "mpn": "PTV09A-4020F-B103", + "maker": "Bourns", + "notes": "Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC.", + "dnp": false, + "uuid": "cb6c0109-b436-5916-be99-c5b95f57a16b" + }, + { + "ref": "RV5", + "value": "10k linear / DELAY", + "x": 88, + "y": 70, + "fp": { + "pads": [ + { + "n": "1", + "x": -2.5, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "1" + }, + { + "n": "2", + "x": 0, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + }, + { + "n": "3", + "x": 2.5, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "3" + }, + { + "n": "MP1", + "x": -5.3, + "y": 0, + "sx": 2.8, + "sy": 3.2, + "drill": [ + 1.8, + 2.2 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "MP1" + }, + { + "n": "MP2", + "x": 5.3, + "y": 0, + "sx": 2.8, + "sy": 3.2, + "drill": [ + 1.8, + 2.2 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "MP2" + } + ], + "body": [ + 11.4, + 11.0 + ], + "height": 7.4, + "name": "Bourns_PTV09A4_RearFacing" + }, + "nets": { + "1": "GND", + "2": "POT_DELAY_RAW", + "3": "VREF25", + "MP1": null, + "MP2": null + }, + "side": "F", + "angle": 0, + "block": "controls", + "mpn": "PTV09A-4020F-B103", + "maker": "Bourns", + "notes": "Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC.", + "dnp": false, + "uuid": "a77ff7f6-ae92-50bd-b28b-442cd55be9b6" + }, + { + "ref": "RV6", + "value": "10k linear / REVERB", + "x": 110, + "y": 70, + "fp": { + "pads": [ + { + "n": "1", + "x": -2.5, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "1" + }, + { + "n": "2", + "x": 0, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + }, + { + "n": "3", + "x": 2.5, + "y": -7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "3" + }, + { + "n": "MP1", + "x": -5.3, + "y": 0, + "sx": 2.8, + "sy": 3.2, + "drill": [ + 1.8, + 2.2 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "MP1" + }, + { + "n": "MP2", + "x": 5.3, + "y": 0, + "sx": 2.8, + "sy": 3.2, + "drill": [ + 1.8, + 2.2 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "MP2" + } + ], + "body": [ + 11.4, + 11.0 + ], + "height": 7.4, + "name": "Bourns_PTV09A4_RearFacing" + }, + "nets": { + "1": "GND", + "2": "POT_REVERB_RAW", + "3": "VREF25", + "MP1": null, + "MP2": null + }, + "side": "F", + "angle": 0, + "block": "controls", + "mpn": "PTV09A-4020F-B103", + "maker": "Bourns", + "notes": "Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC.", + "dnp": false, + "uuid": "0849b9e4-ac33-55b8-87e2-939f457734af" + }, + { + "ref": "ENC1", + "value": "24 PPR / PUSH", + "x": 42, + "y": 43, + "fp": { + "pads": [ + { + "n": "A", + "x": -2.5, + "y": -7.5, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "A" + }, + { + "n": "C", + "x": 0, + "y": -7.5, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "C" + }, + { + "n": "B", + "x": 2.5, + "y": -7.5, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "B" + }, + { + "n": "S1", + "x": -2.5, + "y": 7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "S1" + }, + { + "n": "S2", + "x": 2.5, + "y": 7, + "sx": 1.8, + "sy": 1.8, + "drill": 1.0, + "kind": "thru_hole", + "shape": "circle", + "name": "S2" + }, + { + "n": "MP1", + "x": -6.6, + "y": 0, + "sx": 2.8, + "sy": 3.6, + "drill": [ + 1.8, + 2.6 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "MP1" + }, + { + "n": "MP2", + "x": 6.6, + "y": 0, + "sx": 2.8, + "sy": 3.6, + "drill": [ + 1.8, + 2.6 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "MP2" + } + ], + "body": [ + 14, + 16 + ], + "height": 6.5, + "name": "Bourns_PEC11R4_RearFacing_Switch" + }, + "nets": { + "A": "ENC_A_RAW", + "B": "ENC_B_RAW", + "C": "GND", + "S1": "ENC_SW_RAW", + "S2": "GND", + "MP1": null, + "MP2": null + }, + "side": "F", + "angle": 0, + "block": "controls", + "mpn": "PEC11R-4220F-S0024", + "maker": "Bourns", + "notes": "20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack.", + "dnp": false, + "uuid": "82881ed2-d2b6-51a6-9dad-cffbe9d62def" + }, + { + "ref": "SW1", + "value": "MODE / SPDT ON-ON", + "x": 150.5, + "y": 84.5, + "fp": { + "pads": [ + { + "n": "1", + "x": 0, + "y": -4.7, + "sx": 2.8, + "sy": 2.8, + "drill": 1.85, + "kind": "thru_hole", + "shape": "circle", + "name": "1" + }, + { + "n": "2", + "x": 0, + "y": 0, + "sx": 2.8, + "sy": 2.8, + "drill": 1.85, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + }, + { + "n": "3", + "x": 0, + "y": 4.7, + "sx": 2.8, + "sy": 2.8, + "drill": 1.85, + "kind": "thru_hole", + "shape": "circle", + "name": "3" + } + ], + "body": [ + 6.86, + 12.7 + ], + "height": 8.89, + "name": "E_Switch_100SP_M2" + }, + "nets": { + "1": "GND", + "2": "cv_select", + "3": "V3V3" + }, + "side": "F", + "angle": 0, + "block": "controls", + "mpn": "100SP1T1B1M2REH", + "maker": "E-Switch", + "notes": "Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required.", + "dnp": false, + "uuid": "f5afaab2-c860-5fc4-9b76-5a05e19eaa7a" + }, + { + "ref": "D10", + "value": "VOICE 1", + "x": 124, + "y": 108, + "fp": { + "pads": [ + { + "n": "1", + "x": -1.27, + "y": 0, + "sx": 1.6, + "sy": 1.6, + "drill": 0.9, + "kind": "thru_hole", + "shape": "circle", + "name": "1" + }, + { + "n": "2", + "x": 1.27, + "y": 0, + "sx": 1.6, + "sy": 1.6, + "drill": 0.9, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + } + ], + "body": [ + 3.8, + 3.8 + ], + "height": 12.5, + "name": "LED_D3.0_P2.54" + }, + "nets": { + "1": "GND", + "2": "LED0_A" + }, + "side": "F", + "angle": 0, + "block": "controls", + "mpn": "L-934GD", + "maker": "Kingbright", + "notes": "3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height.", + "dnp": false, + "uuid": "fe276ab0-ff85-5ab2-898b-ed8075966655" + }, + { + "ref": "D11", + "value": "VOICE 2", + "x": 134, + "y": 108, + "fp": { + "pads": [ + { + "n": "1", + "x": -1.27, + "y": 0, + "sx": 1.6, + "sy": 1.6, + "drill": 0.9, + "kind": "thru_hole", + "shape": "circle", + "name": "1" + }, + { + "n": "2", + "x": 1.27, + "y": 0, + "sx": 1.6, + "sy": 1.6, + "drill": 0.9, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + } + ], + "body": [ + 3.8, + 3.8 + ], + "height": 12.5, + "name": "LED_D3.0_P2.54" + }, + "nets": { + "1": "GND", + "2": "LED1_A" + }, + "side": "F", + "angle": 0, + "block": "controls", + "mpn": "L-934GD", + "maker": "Kingbright", + "notes": "3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height.", + "dnp": false, + "uuid": "b36d9fe8-1d28-5e73-9188-b569959c7a35" + }, + { + "ref": "D12", + "value": "VOICE 3", + "x": 144, + "y": 108, + "fp": { + "pads": [ + { + "n": "1", + "x": -1.27, + "y": 0, + "sx": 1.6, + "sy": 1.6, + "drill": 0.9, + "kind": "thru_hole", + "shape": "circle", + "name": "1" + }, + { + "n": "2", + "x": 1.27, + "y": 0, + "sx": 1.6, + "sy": 1.6, + "drill": 0.9, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + } + ], + "body": [ + 3.8, + 3.8 + ], + "height": 12.5, + "name": "LED_D3.0_P2.54" + }, + "nets": { + "1": "GND", + "2": "LED2_A" + }, + "side": "F", + "angle": 0, + "block": "controls", + "mpn": "L-934GD", + "maker": "Kingbright", + "notes": "3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height.", + "dnp": false, + "uuid": "8581a420-1ba2-5d16-a609-c9a592c237c5" + }, + { + "ref": "D13", + "value": "VOICE 4", + "x": 154, + "y": 108, + "fp": { + "pads": [ + { + "n": "1", + "x": -1.27, + "y": 0, + "sx": 1.6, + "sy": 1.6, + "drill": 0.9, + "kind": "thru_hole", + "shape": "circle", + "name": "1" + }, + { + "n": "2", + "x": 1.27, + "y": 0, + "sx": 1.6, + "sy": 1.6, + "drill": 0.9, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + } + ], + "body": [ + 3.8, + 3.8 + ], + "height": 12.5, + "name": "LED_D3.0_P2.54" + }, + "nets": { + "1": "GND", + "2": "LED3_A" + }, + "side": "F", + "angle": 0, + "block": "controls", + "mpn": "L-934GD", + "maker": "Kingbright", + "notes": "3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height.", + "dnp": false, + "uuid": "cb84da0a-7689-587d-8688-e97d2e4c3449" + }, + { + "ref": "J301", + "value": "PITCH 0-5V", + "x": 186.5, + "y": 99, + "fp": { + "pads": [ + { + "n": "1", + "x": 0, + "y": -6.48, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "SLEEVE" + }, + { + "n": "2", + "x": 0, + "y": -3.38, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "NORMAL" + }, + { + "n": "3", + "x": 0, + "y": 4.92, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "TIP" + }, + { + "n": "", + "x": 0, + "y": 0, + "sx": 3, + "sy": 3, + "drill": 3, + "kind": "np_thru_hole", + "shape": "circle", + "name": "" + } + ], + "body": [ + 9, + 10.5 + ], + "height": 9, + "name": "WQP518MA_PJ398SM_Vertical" + }, + "nets": { + "1": "GND", + "2": "GND", + "3": "PITCH_IN" + }, + "side": "F", + "angle": 0, + "block": "io", + "mpn": "WQP518MA (Thonkiconn/PJ398SM)", + "maker": "QingPu / Thonk", + "notes": "Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check.", + "dnp": false, + "uuid": "1d1426a6-6ee9-5869-8b4b-7ecb976e988e" + }, + { + "ref": "J302", + "value": "MOD", + "x": 186.5, + "y": 81, + "fp": { + "pads": [ + { + "n": "1", + "x": 0, + "y": -6.48, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "SLEEVE" + }, + { + "n": "2", + "x": 0, + "y": -3.38, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "NORMAL" + }, + { + "n": "3", + "x": 0, + "y": 4.92, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "TIP" + }, + { + "n": "", + "x": 0, + "y": 0, + "sx": 3, + "sy": 3, + "drill": 3, + "kind": "np_thru_hole", + "shape": "circle", + "name": "" + } + ], + "body": [ + 9, + 10.5 + ], + "height": 9, + "name": "WQP518MA_PJ398SM_Vertical" + }, + "nets": { + "1": "GND", + "2": "GND", + "3": "MOD_RAW" + }, + "side": "F", + "angle": 0, + "block": "io", + "mpn": "WQP518MA (Thonkiconn/PJ398SM)", + "maker": "QingPu / Thonk", + "notes": "Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check.", + "dnp": false, + "uuid": "c1806fec-6f4c-552c-ac14-80ec675f5a36" + }, + { + "ref": "J303", + "value": "GATE", + "x": 186.5, + "y": 63, + "fp": { + "pads": [ + { + "n": "1", + "x": 0, + "y": -6.48, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "SLEEVE" + }, + { + "n": "2", + "x": 0, + "y": -3.38, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "NORMAL" + }, + { + "n": "3", + "x": 0, + "y": 4.92, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "TIP" + }, + { + "n": "", + "x": 0, + "y": 0, + "sx": 3, + "sy": 3, + "drill": 3, + "kind": "np_thru_hole", + "shape": "circle", + "name": "" + } + ], + "body": [ + 9, + 10.5 + ], + "height": 9, + "name": "WQP518MA_PJ398SM_Vertical" + }, + "nets": { + "1": "GND", + "2": "GND", + "3": "GATE_IN" + }, + "side": "F", + "angle": 0, + "block": "io", + "mpn": "WQP518MA (Thonkiconn/PJ398SM)", + "maker": "QingPu / Thonk", + "notes": "Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check.", + "dnp": false, + "uuid": "be78fd5a-3121-50f1-a6c8-33469a59e66e" + }, + { + "ref": "J304", + "value": "LINE L", + "x": 186.5, + "y": 45, + "fp": { + "pads": [ + { + "n": "1", + "x": 0, + "y": -6.48, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "SLEEVE" + }, + { + "n": "2", + "x": 0, + "y": -3.38, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "NORMAL" + }, + { + "n": "3", + "x": 0, + "y": 4.92, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "TIP" + }, + { + "n": "", + "x": 0, + "y": 0, + "sx": 3, + "sy": 3, + "drill": 3, + "kind": "np_thru_hole", + "shape": "circle", + "name": "" + } + ], + "body": [ + 9, + 10.5 + ], + "height": 9, + "name": "WQP518MA_PJ398SM_Vertical" + }, + "nets": { + "1": "GND", + "2": null, + "3": "LINE_L" + }, + "side": "F", + "angle": 0, + "block": "io", + "mpn": "WQP518MA (Thonkiconn/PJ398SM)", + "maker": "QingPu / Thonk", + "notes": "Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check.", + "dnp": false, + "uuid": "20a12c22-8872-522b-8afe-80cd0acffe87" + }, + { + "ref": "J305", + "value": "LINE R", + "x": 186.5, + "y": 27, + "fp": { + "pads": [ + { + "n": "1", + "x": 0, + "y": -6.48, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "SLEEVE" + }, + { + "n": "2", + "x": 0, + "y": -3.38, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "NORMAL" + }, + { + "n": "3", + "x": 0, + "y": 4.92, + "sx": 2.3, + "sy": 2.6, + "drill": [ + 1.0, + 1.9 + ], + "kind": "thru_hole", + "shape": "oval", + "name": "TIP" + }, + { + "n": "", + "x": 0, + "y": 0, + "sx": 3, + "sy": 3, + "drill": 3, + "kind": "np_thru_hole", + "shape": "circle", + "name": "" + } + ], + "body": [ + 9, + 10.5 + ], + "height": 9, + "name": "WQP518MA_PJ398SM_Vertical" + }, + "nets": { + "1": "GND", + "2": null, + "3": "LINE_R" + }, + "side": "F", + "angle": 0, + "block": "io", + "mpn": "WQP518MA (Thonkiconn/PJ398SM)", + "maker": "QingPu / Thonk", + "notes": "Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check.", + "dnp": false, + "uuid": "39bd0795-f68c-5b3f-83ac-033c8b0bcb76" + }, + { + "ref": "J306", + "value": "22-27-2021", + "x": 57.5, + "y": 39, + "fp": { + "pads": [ + { + "n": "1", + "x": -1.27, + "y": 0, + "sx": 1.6, + "sy": 1.6, + "drill": 1.1, + "kind": "thru_hole", + "shape": "rect", + "name": "1" + }, + { + "n": "2", + "x": 1.27, + "y": 0, + "sx": 1.6, + "sy": 1.6, + "drill": 1.1, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + } + ], + "body": [ + 5.3, + 6.02 + ], + "height": 8.0, + "name": "Molex_22-27-2021_J306_B" + }, + "nets": { + "1": "MIDI4", + "2": "MIDI5" + }, + "side": "B", + "angle": 0, + "block": "io", + "mpn": "22-27-2021", + "maker": "Molex", + "notes": "Exact KK-254 2-circuit friction-lock header to retained Same Sky SDS-50J MIDI DIN pins 4 and 5. No DIN 2/shield-to-GND connection.", + "dnp": false, + "uuid": "f536e084-c6a1-57ea-8653-b1afeea3b2ff" + }, + { + "ref": "J200", + "value": "61201021621", + "x": 174, + "y": 64, + "fp": { + "pads": [ + { + "n": "1", + "x": -1.27, + "y": 5.08, + "sx": 1.65, + "sy": 1.65, + "drill": 1.1, + "kind": "thru_hole", + "shape": "rect", + "name": "1" + }, + { + "n": "2", + "x": 1.27, + "y": 5.08, + "sx": 1.65, + "sy": 1.65, + "drill": 1.1, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + }, + { + "n": "3", + "x": -1.27, + "y": 2.54, + "sx": 1.65, + "sy": 1.65, + "drill": 1.1, + "kind": "thru_hole", + "shape": "circle", + "name": "3" + }, + { + "n": "4", + "x": 1.27, + "y": 2.54, + "sx": 1.65, + "sy": 1.65, + "drill": 1.1, + "kind": "thru_hole", + "shape": "circle", + "name": "4" + }, + { + "n": "5", + "x": -1.27, + "y": 0.0, + "sx": 1.65, + "sy": 1.65, + "drill": 1.1, + "kind": "thru_hole", + "shape": "circle", + "name": "5" + }, + { + "n": "6", + "x": 1.27, + "y": 0.0, + "sx": 1.65, + "sy": 1.65, + "drill": 1.1, + "kind": "thru_hole", + "shape": "circle", + "name": "6" + }, + { + "n": "7", + "x": -1.27, + "y": -2.54, + "sx": 1.65, + "sy": 1.65, + "drill": 1.1, + "kind": "thru_hole", + "shape": "circle", + "name": "7" + }, + { + "n": "8", + "x": 1.27, + "y": -2.54, + "sx": 1.65, + "sy": 1.65, + "drill": 1.1, + "kind": "thru_hole", + "shape": "circle", + "name": "8" + }, + { + "n": "9", + "x": -1.27, + "y": -5.08, + "sx": 1.65, + "sy": 1.65, + "drill": 1.1, + "kind": "thru_hole", + "shape": "circle", + "name": "9" + }, + { + "n": "10", + "x": 1.27, + "y": -5.08, + "sx": 1.65, + "sy": 1.65, + "drill": 1.1, + "kind": "thru_hole", + "shape": "circle", + "name": "10" + } + ], + "body": [ + 9.85, + 21.36 + ], + "height": 12.1, + "name": "Wurth_61201021621_Exact_B" + }, + "nets": { + "1": null, + "2": null, + "3": "GND", + "4": "GND", + "5": "GND", + "6": "GND", + "7": "GND", + "8": "GND", + "9": "RACK_12V", + "10": "RACK_12V" + }, + "side": "B", + "angle": 0, + "block": "power", + "mpn": "61201021621", + "maker": "Wurth Elektronik", + "notes": "Exact keyed WR-BHD 2x5 2.54 mm header. Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections.", + "dnp": false, + "uuid": "22b1fffe-abd6-5915-b500-c63f9c0cc768" + }, + { + "ref": "J201", + "value": "22-27-2021", + "x": 26, + "y": 52, + "fp": { + "pads": [ + { + "n": "1", + "x": -1.27, + "y": 0, + "sx": 1.6, + "sy": 1.6, + "drill": 1.1, + "kind": "thru_hole", + "shape": "rect", + "name": "1" + }, + { + "n": "2", + "x": 1.27, + "y": 0, + "sx": 1.6, + "sy": 1.6, + "drill": 1.1, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + } + ], + "body": [ + 5.3, + 6.02 + ], + "height": 8.0, + "name": "Molex_22-27-2021_J201_B" + }, + "nets": { + "1": "DESKTOP_12V", + "2": "GND" + }, + "side": "B", + "angle": 0, + "block": "power", + "mpn": "22-27-2021", + "maker": "Molex", + "notes": "Exact KK-254 2-circuit friction-lock header from the chassis-mounted 12 V DC inlet. NOT a 5 V inlet.", + "dnp": false, + "uuid": "a47c0ef6-62da-55f1-9de0-f66bd495a11a" + }, + { + "ref": "F1", + "value": "2A FUSE / >=32V", + "x": 53, + "y": 65, + "fp": { + "pads": [ + { + "n": "1", + "x": -1.5, + "y": 0, + "sx": 1.3, + "sy": 1.8, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1" + }, + { + "n": "2", + "x": 1.5, + "y": 0, + "sx": 1.3, + "sy": 1.8, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "2" + } + ], + "body": [ + 3.2, + 1.6 + ], + "height": 1.1, + "name": "Fuse_1206" + }, + "nets": { + "1": "RACK_12V", + "2": "RACK_FUSED" + }, + "side": "F", + "angle": 0, + "block": "power", + "mpn": "SELECT 2 A >=32 V 1206 fuse", + "maker": "", + "notes": "Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate.", + "dnp": false, + "uuid": "cf3fecca-7a96-5152-8905-52011939431b" + }, + { + "ref": "F2", + "value": "2A FUSE / >=32V", + "x": 26, + "y": 59, + "fp": { + "pads": [ + { + "n": "1", + "x": -1.5, + "y": 0, + "sx": 1.3, + "sy": 1.8, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1" + }, + { + "n": "2", + "x": 1.5, + "y": 0, + "sx": 1.3, + "sy": 1.8, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "2" + } + ], + "body": [ + 3.2, + 1.6 + ], + "height": 1.1, + "name": "Fuse_1206" + }, + "nets": { + "1": "DESKTOP_12V", + "2": "DESKTOP_FUSED" + }, + "side": "F", + "angle": 0, + "block": "power", + "mpn": "SELECT 2 A >=32 V 1206 fuse", + "maker": "", + "notes": "Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate.", + "dnp": false, + "uuid": "2c15d3f7-621c-571d-bae0-d9bc20f3166d" + }, + { + "ref": "D1", + "value": "SS54 / OR", + "x": 44, + "y": 65, + "fp": { + "pads": [ + { + "n": "1", + "x": -2.7, + "y": 0, + "sx": 2.2, + "sy": 2.8, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1" + }, + { + "n": "2", + "x": 2.7, + "y": 0, + "sx": 2.2, + "sy": 2.8, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "2" + } + ], + "body": [ + 5.4, + 3.6 + ], + "height": 2.6, + "name": "D_SMB" + }, + "nets": { + "1": "VRAW", + "2": "RACK_FUSED" + }, + "side": "F", + "angle": 0, + "block": "power", + "mpn": "SS54-E3/57T", + "maker": "Vishay", + "notes": "Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature.", + "dnp": false, + "uuid": "2491e415-d4d3-5f05-adc4-96f2585667c3" + }, + { + "ref": "D2", + "value": "SS54 / OR", + "x": 35, + "y": 59, + "fp": { + "pads": [ + { + "n": "1", + "x": -2.7, + "y": 0, + "sx": 2.2, + "sy": 2.8, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1" + }, + { + "n": "2", + "x": 2.7, + "y": 0, + "sx": 2.2, + "sy": 2.8, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "2" + } + ], + "body": [ + 5.4, + 3.6 + ], + "height": 2.6, + "name": "D_SMB" + }, + "nets": { + "1": "VRAW", + "2": "DESKTOP_FUSED" + }, + "side": "F", + "angle": 0, + "block": "power", + "mpn": "SS54-E3/57T", + "maker": "Vishay", + "notes": "Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature.", + "dnp": false, + "uuid": "22451254-ce41-55ee-8e90-c20756e02fe9" + }, + { + "ref": "D3", + "value": "SMBJ15A", + "x": 25, + "y": 46, + "fp": { + "pads": [ + { + "n": "1", + "x": -2.7, + "y": 0, + "sx": 2.2, + "sy": 2.8, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1" + }, + { + "n": "2", + "x": 2.7, + "y": 0, + "sx": 2.2, + "sy": 2.8, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "2" + } + ], + "body": [ + 5.4, + 3.6 + ], + "height": 2.6, + "name": "D_SMB" + }, + "nets": { + "1": "VRAW", + "2": "GND" + }, + "side": "F", + "angle": 0, + "block": "power", + "mpn": "SMBJ15A-E3/52", + "maker": "Vishay", + "notes": "Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test.", + "dnp": false, + "uuid": "e3db311e-a848-59dd-b0da-759dab706442" + }, + { + "ref": "U1", + "value": "TPS54302DDCR", + "x": 34, + "y": 25, + "fp": { + "pads": [ + { + "n": "1", + "x": -1.1, + "y": 0.95, + "sx": 1.0, + "sy": 0.6, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "GND" + }, + { + "n": "2", + "x": -1.1, + "y": 0, + "sx": 1.0, + "sy": 0.6, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "SW" + }, + { + "n": "3", + "x": -1.1, + "y": -0.95, + "sx": 1.0, + "sy": 0.6, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "VIN" + }, + { + "n": "4", + "x": 1.1, + "y": -0.95, + "sx": 1.0, + "sy": 0.6, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "FB" + }, + { + "n": "5", + "x": 1.1, + "y": 0, + "sx": 1.0, + "sy": 0.6, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "EN" + }, + { + "n": "6", + "x": 1.1, + "y": 0.95, + "sx": 1.0, + "sy": 0.6, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "BOOT" + } + ], + "body": [ + 1.6, + 2.9 + ], + "height": 1.1, + "name": "TI_DDC0006A_SOT23_6" + }, + "nets": { + "1": "GND", + "2": "SW", + "3": "VRAW", + "4": "FB", + "5": "EN", + "6": "BOOT" + }, + "side": "F", + "angle": 0, + "block": "power", + "mpn": "TPS54302DDCR", + "maker": "Texas Instruments", + "notes": "3 A IC rating is a design target, not validated system delivery. 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verify effective capacitance at DC bias", + "dnp": false, + "uuid": "9d21645e-6e9c-5499-9690-93108325ef0e" + }, + { + "ref": "C4", + "value": "22uF", + "x": 23, + "y": 33, + "fp": { + "pads": [ + { + "n": "1", + "x": -1.65, + "y": 0, + "sx": 1.5, + "sy": 2.9, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1" + }, + { + "n": "2", + "x": 1.65, + "y": 0, + "sx": 1.5, + "sy": 2.9, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "2" + } + ], + "body": [ + 3.2, + 2.5 + ], + "height": 2.5, + "name": "C_1210" + }, + "nets": { + "1": "VIN5", + "2": "GND" + }, + "side": "F", + "angle": 90, + "block": "power", + "mpn": "SELECT 22uF 25V X7R 1210", + "maker": "", + "notes": "25V X7R; verify effective capacitance at DC bias", + "dnp": false, + "uuid": "6e2ec867-0c4b-5305-84d8-cdacb8e45221" + }, + { + "ref": "C5", + "value": "22uF", + "x": 29, + "y": 33, + "fp": { + "pads": [ + { + "n": "1", + "x": -1.65, + "y": 0, + "sx": 1.5, + "sy": 2.9, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1" + }, + { + "n": "2", + "x": 1.65, + "y": 0, + "sx": 1.5, + "sy": 2.9, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "2" + } + ], + "body": [ + 3.2, + 2.5 + ], + "height": 2.5, + "name": "C_1210" + }, + "nets": { + "1": "VIN5", + "2": "GND" + }, + "side": "F", + "angle": 90, + "block": "power", + "mpn": "SELECT 22uF 25V X7R 1210", + "maker": "", + "notes": "25V X7R; verify effective capacitance at DC bias", + "dnp": false, + "uuid": "fe6c420e-f8ee-519a-9963-1ced568e4ce0" + }, + { + "ref": "R1", + "value": "100k", + "x": 39.5, + "y": 27, + "fp": { + "pads": [ + { + "n": "1", + "x": -0.825, + "y": 0, + "sx": 0.85, + "sy": 0.95, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1" + }, + { + "n": "2", + "x": 0.825, + "y": 0, + "sx": 0.85, + "sy": 0.95, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "2" + } + ], + "body": [ + 1.6, + 0.8 + ], + "height": 0.6, + "name": "R_0603" + }, + "nets": { + "1": "FF_TOP", + "2": "FB" + }, + "side": "F", + "angle": 0, + "block": "power", + "mpn": "SELECT 100k 1% 0603", + "maker": "", + "notes": "Resistor 1%", + "dnp": false, + "uuid": "e06fed5c-7bac-525d-a94d-7c4fb1b320ac" + }, + { + "ref": "R2", + "value": "13.3k", + "x": 39, + "y": 20, + "fp": { + "pads": [ + { + "n": "1", + "x": -0.825, + "y": 0, + "sx": 0.85, + "sy": 0.95, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1" + }, + { + "n": "2", + "x": 0.825, + "y": 0, + "sx": 0.85, + "sy": 0.95, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "2" + } + ], + "body": [ + 1.6, + 0.8 + ], + "height": 0.6, + "name": "R_0603" + }, + "nets": { + "1": "FB", + "2": "GND" + }, + "side": "F", + "angle": 0, + "block": "power", + "mpn": "SELECT 13.3k 1% 0603", + "maker": "", + "notes": "Resistor 1%", + "dnp": false, + "uuid": "1ed808a6-f40e-5015-9e0e-5d2f703996c9" + }, + { + "ref": "R3", + "value": "511k", + "x": 46, + "y": 23, + "fp": { + "pads": [ + { + "n": "1", + "x": -0.825, + "y": 0, + "sx": 0.85, + "sy": 0.95, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1" + }, + { + "n": "2", + "x": 0.825, + "y": 0, + "sx": 0.85, + "sy": 0.95, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "2" + } + ], + "body": [ + 1.6, + 0.8 + ], + "height": 0.6, + "name": "R_0603" + }, + "nets": { + "1": "VRAW", + "2": "EN" + }, + "side": "F", + "angle": 90, + "block": "power", + "mpn": "SELECT 511k 1% 0603", + "maker": "", + "notes": "Resistor 1%", + "dnp": false, + "uuid": "9c543196-dbb2-5183-8db6-93df2d3af013" + }, + { + "ref": "R4", + "value": "105k", + "x": 43, + "y": 19, + "fp": { + "pads": [ + { + "n": "1", + "x": -0.825, + "y": 0, + "sx": 0.85, + "sy": 0.95, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1" + }, + { + "n": "2", + "x": 0.825, + "y": 0, + "sx": 0.85, + "sy": 0.95, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "2" + } + ], + "body": [ + 1.6, + 0.8 + ], + "height": 0.6, + "name": "R_0603" + }, + "nets": { + "1": "EN", + "2": "GND" + }, + "side": "F", + "angle": 0, + "block": "power", + "mpn": "SELECT 105k 1% 0603", + "maker": "", + "notes": "Resistor 1%", + "dnp": false, + "uuid": "a7ef9d11-82b6-59ca-b368-2f515d0c5c24" + }, + { + "ref": "R5", + "value": "49.9", + "x": 39, + "y": 32, + "fp": { + "pads": [ + { + "n": "1", + "x": -0.825, + "y": 0, + "sx": 0.85, + "sy": 0.95, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1" + }, + { + "n": "2", + "x": 0.825, + "y": 0, + "sx": 0.85, + "sy": 0.95, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "2" + } + ], + "body": [ + 1.6, + 0.8 + ], + "height": 0.6, + "name": "R_0603" + }, + "nets": { + "1": "VIN5", + "2": "FF_TOP" + }, + "side": "F", + "angle": 0, + "block": "power", + "mpn": "SELECT 49.9 1% 0603", + "maker": "", + "notes": "Resistor 1%", + "dnp": false, + "uuid": "cb3d6d3e-3504-5797-b2cb-7095c94b674c" + }, + { + "ref": "C6", + "value": "75pF", + "x": 43, + "y": 27, + "fp": { + "pads": [ + { + "n": "1", + "x": -0.825, + "y": 0, + "sx": 0.85, + "sy": 0.95, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1" + }, + { + "n": "2", + "x": 0.825, + "y": 0, + "sx": 0.85, + "sy": 0.95, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "2" + } + ], + "body": [ + 1.6, + 0.8 + ], + "height": 0.6, + "name": "C_0603" + }, + "nets": { + "1": "FF_TOP", + "2": "FB" + }, + "side": "F", + "angle": 0, + "block": "power", + "mpn": "SELECT 75pF 50V C0G 0603", + "maker": "", + "notes": "50V C0G; verify effective capacitance at DC bias", + "dnp": false, + "uuid": "659e71f7-093e-5d1c-89c4-9d3cd026407d" + }, + { + "ref": "C7", + "value": "10uF", + "x": 43, + "y": 59, + "fp": { + "pads": [ + { + "n": "1", + "x": -1.65, + "y": 0, + "sx": 1.5, + "sy": 2.9, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1" + }, + { + "n": "2", + "x": 1.65, + "y": 0, + "sx": 1.5, + "sy": 2.9, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "2" + } + ], + "body": [ + 3.2, + 2.5 + ], + "height": 2.5, + "name": "C_1210" + }, + "nets": { + "1": "VRAW", + "2": "GND" + }, + "side": "F", + "angle": 0, + "block": "power", + "mpn": "SELECT 10uF 50V X7R 1210", + "maker": "", + "notes": "50V X7R; verify effective capacitance at DC bias", + "dnp": false, + "uuid": "4a089892-03db-5c15-98b2-fdc052063e20" + }, + { + "ref": "JP1", + "value": "450301014042", + "x": 165.5, + "y": 88, + "fp": { + "pads": [ + { + "n": "1", + "x": 0, + "y": 0, + "sx": 1.3, + "sy": 1.3, + "drill": 0.8, + "kind": "thru_hole", + "shape": "rect", + "name": "1" + }, + { + "n": "2", + "x": 2.54, + "y": 0, + "sx": 1.3, + "sy": 1.3, + "drill": 0.8, + "kind": "thru_hole", + "shape": "circle", + "name": "2" + }, + { + "n": "3", + "x": -2.54, + "y": 0, + "sx": 1.3, + "sy": 1.3, + "drill": 0.8, + "kind": "thru_hole", + "shape": "circle", + "name": "3" + } + ], + "body": [ + 10.5, + 3.0 + ], + "height": 6.4, + "name": "Wurth_450301014042_Exact_B" + }, + "nets": { + "1": "MOD_IN", + "2": "MOD_BIPOLAR", + "3": "MOD_RAW" + }, + "side": "B", + "angle": 0, + "block": "mod", + "mpn": "450301014042", + "maker": "Wurth Elektronik", + "notes": "Actual SPDT configuration switch replaces the removable shunt. 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+ "Y": 61.0, + "side": "B", + "angle": 0, + "uuid": "a3c24aea-1601-5f4c-b1d5-478af197ec60" + } + ], + "legacy_mainboard_map": { + "1": [ + "VIN5", + "GND" + ], + "2": [ + "V3V3", + "GND", + "JTAG_TCK", + "JTAG_TDO", + "JTAG_TDI", + "JTAG_TMS" + ], + "3": [ + "PROGRAM_B", + "GND" + ], + "4": [ + "reset_n", + "GND" + ], + "5": [ + "LINE_L", + "GND", + "LINE_R" + ], + "6": [ + "VREF25", + "POT_PITCH_RAW", + "GND" + ], + "7": [ + "VREF25", + "POT_DECAY_RAW", + "GND" + ], + "8": [ + "VREF25", + "POT_TIMBRE_RAW", + "GND" + ], + "9": [ + "ENC_A_RAW", + "GND", + "ENC_B_RAW", + "ENC_SW_RAW", + "GND" + ], + "10": [ + "V3V3", + "cv_select", + "GND" + ], + "11": [ + "GND", + "LED0_A", + "LED1_A", + "LED2_A", + "LED3_A" + ], + "12": [ + "PITCH_IN", + "GND" + ], + "13": [ + "MOD_IN", + "GND" + ], + "14": [ + "GATE_IN", + "GND" + ], + "15": [ + "MIDI4", + "MIDI5" + ], + "16": [ + "VREF25", + "POT_DRIVE_RAW", + "POT_DELAY_RAW", + "POT_REVERB_RAW", + "GND" + ] + }, + "direct_stack": { + "revision": "STACK-P2", + "description": "Direct panel-to-mainboard Samtec IPT1/IPS1 mezzanine interface; no per-function harnesses", + "nominal_board_gap_mm": 19.99, + "mainboard_product_offset_mm": { + "x": 88.0, + "y": 64.25 + }, + "panel_product_center_mm": { + "x": 103.25, + "y": 64.25 + }, + "connector_footprint": { + "rows": 2, + "positions_per_row": 10, + "pitch_mm": 2.54, + "row_spacing_mm": 2.54, + "pad_diameter_mm": 1.8, + "main": { + "manufacturer": "Samtec", + "mpn": "IPT1-110-06-L-D", + "hole_mm": 1.02, + "body_mm": { + "x": 5.08, + "y": 25.91 + }, + "body_height_mm": 6.35, + "mounting": "vertical through-hole terminal strip", + "insulation_height_mm": 15.3, + "shroud_lower_face_mm": 8.95, + "post_tail_mm": 2.35, + "mating_contact_length_mm": 3.94, + "pin_square_mm": 0.64, + "drawing_reference_model": "models/Samtec_IPT1-110-06-L-D_drawing_reference.step" + }, + "panel": { + "manufacturer": "Samtec", + "mpn": "IPS1-110-01-L-D", + "hole_mm": 1.04, + "body_mm": { + "x": 4.95, + "y": 25.78 + }, + "body_height_mm": 8.51, + "mounting": "vertical through-hole socket strip", + "socket_tower_height_mm": 3.81, + "post_tail_mm": 2.54, + "tail_section_mm": { + "x": 0.79, + "y": 0.41 + }, + "drawing_reference_model": "models/Samtec_IPS1-110-01-L-D_drawing_reference.step" + } + }, + "connectors": [ + { + "id": "A", + "role": "power / analog controls / CV-gate / stereo audio", + "main_ref": "J17", + "panel_ref": "J100", + "main_xy_mm": { + "x": 36.0, + "y": -2.5 + }, + "panel_xy_mm": { + "x": 124.0, + "y": 61.75 + }, + "rotation_deg": 0, + "signals": [ + "GND", + "VIN5", + "VIN5", + "VREF25", + "GND", + "POT_PITCH_RAW", + "POT_DECAY_RAW", + "POT_TIMBRE_RAW", + "POT_DRIVE_RAW", + "POT_DELAY_RAW", + "POT_REVERB_RAW", + "GND", + "PITCH_IN", + "MOD_IN", + "GATE_IN", + "GND", + "LINE_L", + "GND", + "LINE_R", + "GND" + ] + }, + { + "id": "B", + "role": "digital controls / LEDs / MIDI / configuration / JTAG", + "main_ref": "J18", + "panel_ref": "J101", + "main_xy_mm": { + "x": -45.0, + "y": 8.0 + }, + "panel_xy_mm": { + "x": 43.0, + "y": 72.25 + }, + "rotation_deg": 90, + "signals": [ + "GND", + "V3V3", + "GND", + "ENC_A_RAW", + "ENC_B_RAW", + "ENC_SW_RAW", + "cv_select", + "LED0_A", + "LED1_A", + "LED2_A", + "LED3_A", + "GND", + "MIDI4", + "MIDI5", + "PROGRAM_B", + "reset_n", + "JTAG_TCK", + "JTAG_TDO", + "JTAG_TDI", + "JTAG_TMS" + ] + } + ], + "mechanical": { + "load_path": "mounting standoffs; mezzanine connectors are electrical/alignment only", + "panel_side": "bottom", + "mainboard_side": "top", + "panel_footprint_mirror_x": true, + "main_connector": "Samtec IPT1-110-06-L-D", + "panel_connector": "Samtec IPS1-110-01-L-D", + "fully_mated_gap_mm": 19.99, + "max_mated_gap_mm": 20.45, + "assembly_release_gate": "bench-fit connector seating and 20.0 mm standoff tolerance stack before production quantity", + "model_status": "Samtec drawing-derived reference geometry; official vendor STEP download remains gated by Samtec email access" + }, + "mating": { + "fully_mated_gap_mm": 19.99, + "max_gap_mm": 20.45, + "fully_mated_wipe_mm": 0.84, + "min_wipe_at_max_gap_mm": 0.38, + "assembly_standoff_target_mm": 20.0, + "note": "Use 20.0 mm nominal standoffs/spacing and verify assembled seating; 19.99 mm is Samtec nominal fully-mated PCB gap for IPT1 lead style -06 with IPS1 lead style -01.", + "drawing_verified": true, + "drawing_source": "Samtec IPX1 MATED DOCUMENT Rev C, Table 1: IPT1 -06 with IPS1 -01", + "geometric_insertion_fully_mated_mm": 3.82, + "geometric_insertion_at_max_gap_mm": 3.36 + }, + "native_coordinate_transform": { + "panel": { + "product_x": "pcb_x", + "product_y": "128.5 - pcb_y", + "pcb_thickness_mm": 1.6 + }, + "mainboard": { + "product_x": "pcb_x - 12.0", + "product_y": "164.25 - pcb_y", + "pcb_thickness_mm": 1.6 + } + } + } +} \ No newline at end of file diff --git a/hardware/panel/design/fp-lib-table b/hardware/panel/design/fp-lib-table new file mode 100644 index 0000000..3487e2e --- /dev/null +++ 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Verify powered and unpowered fault behavior." + (at 501.65 135.89 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "Nexperia" + (at 501.65 135.89 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 488.95 134.62) + (xy 483.87 134.62)) + (stroke + (width 0) + (type default)) + (uuid "5f038c3b-7850-58e2-a7b2-6bda57e43f60")) + (global_label "GND" + (shape bidirectional) + (at 483.87 134.62 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "35db33ca-610d-5f25-b531-26697355ff97")) + (wire + (pts + (xy 488.95 137.16) + (xy 483.87 137.16)) + (stroke + (width 0) + (type default)) + (uuid "ac1fa494-d099-5265-b788-fe7564eb59bd")) + (global_label "VIN5" + (shape bidirectional) + (at 483.87 137.16 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "94df686a-57f9-5d67-b88f-788a8ba1ff4d")) + (wire + (pts + (xy 514.35 135.89) + (xy 519.43 135.89)) + (stroke + (width 0) + (type default)) + (uuid "09180d71-3f8d-547e-9197-f15555e006b2")) + (global_label "MOD_SUM" + (shape bidirectional) + (at 519.43 135.89 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "cce35c50-da66-5e56-acb7-6a2f701353f5")) + (symbol + (lib_id "RadianPanel:C20") + (at 78.74 199.39 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "60f3a6c1-6f01-5457-bd28-d2f52e211c96") + (property "Reference" "C20" + (at 78.74 190.31 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "100nF" + (at 78.74 208.47 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:C_0603" + (at 78.74 199.39 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "SELECT 100nF 16V X7R 0603" + (at 78.74 199.39 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "0927cc37-4567-523e-8b88-a9985b7cd066")) + (pin "2" + (uuid "48c27119-79ce-5e72-bf24-9974516a30b4")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/a353e908-e1f3-5887-a37d-be1463de1afa" + (reference "C20") + (unit 1)))) + (property "Description" "16V X7R; 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verify effective capacitance at DC bias" + (at 219.71 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "" + (at 219.71 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 209.55 199.39) + (xy 204.47 199.39)) + (stroke + (width 0) + (type default)) + (uuid "92038c36-dd9c-5220-a51e-1a52eec72fb5")) + (global_label "VIN5" + (shape bidirectional) + (at 204.47 199.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "cccdfe0b-f559-5a35-9656-b7d81d1ee184")) + (wire + (pts + (xy 229.87 199.39) + (xy 234.95 199.39)) + (stroke + (width 0) + (type default)) + (uuid "3cbb3317-68fb-59ca-a17a-6af067d64ac8")) + (global_label "GND" + (shape bidirectional) + (at 234.95 199.39 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "c0dd7b7a-b0b2-5cab-99b7-bce53a19d519")) + (symbol + (lib_id "RadianPanel:TP4") + (at 360.68 199.39 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "9a57579e-c67c-5118-aa2a-a9574281fbeb") + (property "Reference" "TP4" + (at 360.68 190.31 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "VREF25" + (at 360.68 208.47 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:TestPoint_D2" + (at 360.68 199.39 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "PCB test pad" + (at 360.68 199.39 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "9fe26028-336f-51f2-be4d-0991fb7b7f4a")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/a353e908-e1f3-5887-a37d-be1463de1afa" + (reference "TP4") + (unit 1)))) + (property "Description" "Exposed soldermask aperture, no component." + (at 360.68 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "" + (at 360.68 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 350.52 199.39) + (xy 345.44 199.39)) + (stroke + (width 0) + (type default)) + (uuid "900a9d99-6875-542f-9e32-51802380b40a")) + (global_label "VREF25" + (shape bidirectional) + (at 345.44 199.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "0f806622-af09-57cc-8763-377aea8d2e98")) + (symbol + (lib_id "RadianPanel:TP5") + (at 501.65 199.39 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "2d0eae80-797a-549c-a27f-4473fbcee434") + (property "Reference" "TP5" + (at 501.65 190.31 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "MOD_BIPOLAR" + (at 501.65 208.47 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:TestPoint_D2" + (at 501.65 199.39 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "PCB test pad" + (at 501.65 199.39 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "fcd5c1a3-e915-52d2-bf6c-6f2e14641155")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/a353e908-e1f3-5887-a37d-be1463de1afa" + (reference "TP5") + (unit 1)))) + (property "Description" "Exposed soldermask aperture, no component." + (at 501.65 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "" + (at 501.65 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 491.49 199.39) + (xy 486.41 199.39)) + (stroke + (width 0) + (type default)) + (uuid "a9e2ce91-6b3e-52c3-8c5e-436ed2905da9")) + (global_label "MOD_BIPOLAR" + (shape bidirectional) + (at 486.41 199.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "6654fa26-404b-5d1e-adba-648711604406")) + (text "JP1 is an SPDT configuration switch: one throw selects direct unipolar MOD_RAW; the other selects MOD_BIPOLAR." + (at 20 365 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "7b4fd508-b5b2-5b07-a689-d7b3c79560be")) + (text "JP1 pin 1 common to pin 2 selects MOD_BIPOLAR. Ideal Vout = 0.5*Vin + VREF25. -5/0/+5 V -> 0/2.5/5 V." + (at 20 373 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "80fe7b41-6f2a-594b-9af8-0ccef96fee07")) + (text "5 V op-amp cannot reach exact rails under load. Endpoints, tolerance, saturation and calibration need testing." + (at 20 381 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "bfcafe52-723e-50e4-8f4c-e66cc98f2f45")) + (text "Do not rescale the PITCH input implicitly. Bipolar MOD requires a matching firmware range/zero configuration." + (at 20 389 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "7bbf9558-4806-565e-baf8-58c797d11d3b"))) diff --git a/hardware/panel/design/power.kicad_sch b/hardware/panel/design/power.kicad_sch new file mode 100644 index 0000000..eab2ec4 --- /dev/null +++ b/hardware/panel/design/power.kicad_sch @@ -0,0 +1,4449 @@ +(kicad_sch + (version 20231120) + (generator "radian_panel_generator") + (uuid "c6d6c3a3-edd3-53cf-85a7-68fcc04adacf") + (paper "A2") + (title_block + (title "01 | POWER INPUTS AND 5 V CONVERTER") + (date "2026-09-15") + (rev "P1 DRAFT") + (comment 1 "Native ERC, footprint verification and hardware testing REQUIRED")) + (lib_symbols + (symbol "RadianPanel:J200" + (pin_names + (offset 0.508)) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 16.509999999999998 0) + (effects + (font + (size 1.27 1.27)))) + (property "Value" "61201021621" + (at 0 -16.509999999999998 0) + (effects + (font + (size 1.27 1.27)))) + (property "Footprint" "RadianPanel:Wurth_61201021621_Exact_B" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (symbol "J200_0_1" + (rectangle + (start -10.16 13.969999999999999) + (end 10.16 -13.969999999999999) + (stroke + (width 0.254) + (type default)) + (fill + (type background)))) + (symbol "J200_1_1" + (pin passive line + (at -12.7 11.43 0) + (length 2.54) + (name "1" + (effects + (font + (size 1.0 1.0)))) + (number "1" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 8.89 0) + (length 2.54) + (name "2" + (effects + (font + (size 1.0 1.0)))) + (number "2" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 6.35 0) + (length 2.54) + (name "3" + (effects + (font + (size 1.0 1.0)))) + (number "3" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 3.81 0) + (length 2.54) + (name "4" + (effects + (font + (size 1.0 1.0)))) + (number "4" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 1.27 0) + (length 2.54) + (name "5" + (effects + (font + (size 1.0 1.0)))) + (number "5" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -1.27 0) + (length 2.54) + (name "6" + (effects + (font + (size 1.0 1.0)))) + (number "6" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -3.81 0) + (length 2.54) + (name "7" + (effects + (font + (size 1.0 1.0)))) + (number "7" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -6.35 0) + (length 2.54) + (name "8" + (effects + (font + (size 1.0 1.0)))) + (number "8" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -8.89 0) + (length 2.54) + (name "9" + (effects + (font + (size 1.0 1.0)))) + (number "9" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -11.43 0) + (length 2.54) + (name "10" + (effects + (font + (size 1.0 1.0)))) + (number "10" + (effects + (font + (size 1.0 1.0)))))) + (property "Description" "Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. 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Existing FPGA mainboard unchanged. 40 HP / 3U + removable desktop dock." + (at 30 38 0) + (effects + (font + (size 2 2)) + (justify left top)) + (uuid "6c4850e6-ab80-5d5a-a069-82f7299bd4cd")) + (sheet + (at 30 65) + (size 235 50) + (stroke + (width 0.3) + (type default)) + (fill + (color 0 0 0 0)) + (uuid "fd872eb1-5f1f-55eb-8327-3584154f3e1b") + (property "Sheetname" "01 | POWER INPUTS AND 5 V CONVERTER" + (at 30 63 0) + (effects + (font + (size 2 2)) + (justify left bottom))) + (property "Sheetfile" "power.kicad_sch" + (at 30 117 0) + (effects + (font + (size 1.5 1.5)) + (justify left top))) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276" + (page "2"))))) + (sheet + (at 295 65) + (size 235 50) + (stroke + (width 0.3) + (type default)) + (fill + (color 0 0 0 0)) + (uuid "fe425aa9-89e9-5e5b-9592-3f1bdae47718") + (property "Sheetname" "02 | FRONT-PANEL CONTROLS" + (at 295 63 0) + (effects + (font + (size 2 2)) + (justify left bottom))) + (property "Sheetfile" "controls.kicad_sch" + (at 295 117 0) + (effects + (font + (size 1.5 1.5)) + (justify left top))) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276" + (page "3"))))) + (sheet + (at 30 140) + (size 235 50) + (stroke + (width 0.3) + (type default)) + (fill + (color 0 0 0 0)) + (uuid "1578ecd5-bea0-5ad2-8ccb-a84196c400b8") + (property "Sheetname" "03 | PATCH JACKS AND MIDI" + (at 30 138 0) + (effects + (font + (size 2 2)) + (justify left bottom))) + (property "Sheetfile" "io.kicad_sch" + (at 30 192 0) + (effects + (font + (size 1.5 1.5)) + (justify left top))) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276" + (page "4"))))) + (sheet + (at 295 140) + (size 235 50) + (stroke + (width 0.3) + (type default)) + (fill + (color 0 0 0 0)) + (uuid "a353e908-e1f3-5887-a37d-be1463de1afa") + (property "Sheetname" "04 | OPTIONAL BIPOLAR MODULATION" + (at 295 138 0) + (effects + (font + (size 2 2)) + (justify left bottom))) + (property "Sheetfile" "mod.kicad_sch" + (at 295 192 0) + (effects + (font + (size 1.5 1.5)) + (justify left top))) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276" + (page "5"))))) + (sheet + (at 30 215) + (size 235 50) + (stroke + (width 0.3) + (type default)) + (fill + (color 0 0 0 0)) + (uuid "dd60d741-95e3-5383-9836-1c68c07ca20b") + (property "Sheetname" "05 | INTERNAL SERVICE ACCESS" + (at 30 213 0) + (effects + (font + (size 2 2)) + (justify left bottom))) + (property "Sheetfile" "service.kicad_sch" + (at 30 267 0) + (effects + (font + (size 1.5 1.5)) + (justify left top))) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276" + (page "6"))))) + (text "ENGINEERING DRAFT: not a fabrication release. Consult the latest native ERC/DRC reports." + (at 30 320 0) + (effects + (font + (size 2 2)) + (justify left top)) + (uuid "3171a586-c249-5a1c-956b-d3b9b68cab12")) + (text "Default build: unipolar PITCH and MOD; line-level outputs; 12 V desktop / rack +12 V to onboard 5 V conversion." + (at 30 337 0) + (effects + (font + (size 1.65 1.65)) + (justify left top)) + (uuid "a4637d84-b1af-59ed-b660-c344957affda")) + (text "DIN and dock inlet are the two intentional off-board cable connections. No extra custom carrier PCB is required." + (at 30 350 0) + (effects + (font + (size 1.65 1.65)) + (justify left top)) + (uuid "7375b84d-6bbe-5f91-be0d-7bacd1401d65")) + (text "See ../docs/README.md for explicit unverified items and the bring-up procedure." + (at 30 363 0) + (effects + (font + (size 1.65 1.65)) + (justify left top)) + (uuid "cc73f245-4024-56a6-8898-449e62fd6de7")) + (sheet_instances + (path "/" + (page "1")))) diff --git a/hardware/panel/design/radian_panel_explicit_graph.net b/hardware/panel/design/radian_panel_explicit_graph.net new file mode 100644 index 0000000..28929d4 --- /dev/null +++ b/hardware/panel/design/radian_panel_explicit_graph.net @@ -0,0 +1,3101 @@ + + + + /home/ik/ChatGPT/Courant/hardware/panel/design/radian_panel.kicad_sch + 2026-09-18T06:03:44 + Eeschema 10.0.6-1.fc44 + + + RADIAN | SINGLE PANEL / INTERFACE PCB + + P1 DRAFT + 2026-09-15 + radian_panel.kicad_sch + + + + + + + + + + + + + + 01 | POWER INPUTS AND 5 V CONVERTER + + P1 DRAFT + 2026-09-15 + power.kicad_sch + + + + + + + + + + + + + + 02 | FRONT-PANEL CONTROLS + + P1 DRAFT + 2026-09-15 + controls.kicad_sch + + + + + + + + + + + + + + 03 | PATCH JACKS AND MIDI + + P1 DRAFT + 2026-09-15 + io.kicad_sch + + + + + + + + + + + + + + 04 | OPTIONAL BIPOLAR MODULATION + + P1 DRAFT + 2026-09-15 + mod.kicad_sch + + + + + + + + + + + + + + 05 | INTERNAL SERVICE ACCESS + + P1 DRAFT + 2026-09-15 + service.kicad_sch + + + + + + + + + + + + + + + 10uF + RadianPanel:C_1210 + 50V X7R; verify effective capacitance at DC bias + + SELECT 10uF 50V X7R 1210 + + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + e235e9e9-27d8-5bc5-9979-aa61676bbb5e + + + + + + + + + + + 100nF + RadianPanel:C_0603 + 50V X7R; verify effective capacitance at DC bias + + SELECT 100nF 50V X7R 0603 + + RadianPanel:C_0603 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + f0dfa655-1c0e-52c4-8e96-ff7485b903fa + + + + + + + + + + + 100nF + RadianPanel:C_0603 + 16V X7R; verify effective capacitance at DC bias + + SELECT 100nF 16V X7R 0603 + + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + 9d21645e-6e9c-5499-9690-93108325ef0e + + + + + + + + + + + 22uF + RadianPanel:C_1210 + 25V X7R; verify effective capacitance at DC bias + + SELECT 22uF 25V X7R 1210 + + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + 6e2ec867-0c4b-5305-84d8-cdacb8e45221 + + + + + + + + + + + 22uF + RadianPanel:C_1210 + 25V X7R; verify effective capacitance at DC bias + + SELECT 22uF 25V X7R 1210 + + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + fe6c420e-f8ee-519a-9963-1ced568e4ce0 + + + + + + + + + + + 75pF + RadianPanel:C_0603 + 50V C0G; verify effective capacitance at DC bias + + SELECT 75pF 50V C0G 0603 + + RadianPanel:C_0603 + + 50V C0G; verify effective capacitance at DC bias + + + + + + + + 659e71f7-093e-5d1c-89c4-9d3cd026407d + + + + + + + + + + + 10uF + RadianPanel:C_1210 + 50V X7R; verify effective capacitance at DC bias + + SELECT 10uF 50V X7R 1210 + + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + 4a089892-03db-5c15-98b2-fdc052063e20 + + + + + + + + + + + SS54 / OR + RadianPanel:D_SMB + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + SS54-E3/57T + Vishay + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + + + + + + + 2491e415-d4d3-5f05-adc4-96f2585667c3 + + + + + + + + + + + SS54 / OR + RadianPanel:D_SMB + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + SS54-E3/57T + Vishay + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + + + + + + + 22451254-ce41-55ee-8e90-c20756e02fe9 + + + + + + + + + + + SMBJ15A + RadianPanel:D_SMB + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + + SMBJ15A-E3/52 + Vishay + RadianPanel:D_SMB + + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + + + + + + + + e3db311e-a848-59dd-b0da-759dab706442 + + + + + + + + + + + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + SELECT 2 A >=32 V 1206 fuse + + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + cf3fecca-7a96-5152-8905-52011939431b + + + + + + + + + + + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + SELECT 2 A >=32 V 1206 fuse + + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + 2c15d3f7-621c-571d-bae0-d9bc20f3166d + + + + + + + + + + + 61201021621 + RadianPanel:Wurth_61201021621_Exact_B + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + 61201021621 + + RadianPanel:Wurth_61201021621_Exact_B + + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + + + + + + + 22b1fffe-abd6-5915-b500-c63f9c0cc768 + + + + + + + + + + + + + + + + + + + 22-27-2021 + RadianPanel:Molex_22-27-2021_J201_B + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + 22-27-2021 + + RadianPanel:Molex_22-27-2021_J201_B + + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + + + + + + + a47c0ef6-62da-55f1-9de0-f66bd495a11a + + + + + + + + + + + 10uH 4A / Isat7.5A + RadianPanel:Bourns_SRP7050TA + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + + SRP7050TA-100M + Bourns + RadianPanel:Bourns_SRP7050TA + + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + + + + + + + + cf417c35-4329-5b7a-949c-57d34d609287 + + + + + + + + + + + 100k + RadianPanel:R_0603 + Resistor 1% + + SELECT 100k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + e06fed5c-7bac-525d-a94d-7c4fb1b320ac + + + + + + + + + + + 13.3k + RadianPanel:R_0603 + Resistor 1% + + SELECT 13.3k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + 1ed808a6-f40e-5015-9e0e-5d2f703996c9 + + + + + + + + + + + 511k + RadianPanel:R_0603 + Resistor 1% + + SELECT 511k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + 9c543196-dbb2-5183-8db6-93df2d3af013 + + + + + + + + + + + 105k + RadianPanel:R_0603 + Resistor 1% + + SELECT 105k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + a7ef9d11-82b6-59ca-b368-2f515d0c5c24 + + + + + + + + + + + 49.9 + RadianPanel:R_0603 + Resistor 1% + + SELECT 49.9 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + cb3d6d3e-3504-5797-b2cb-7095c94b674c + + + + + + + + + + + GND + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 30e5f418-53cd-5bd6-83da-5313e82697f5 + + + + + + + + + + VIN5 + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 6efe25b9-68ef-56d7-aaa2-7cb82610ed50 + + + + + + + + + + VRAW + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + bfc78a37-02e3-5618-a8bf-e2932365b2e3 + + + + + + + + + + TPS54302DDCR + RadianPanel:TI_DDC0006A_SOT23_6 + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + + TPS54302DDCR + Texas Instruments + RadianPanel:TI_DDC0006A_SOT23_6 + + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + + + + + + + + d5d17bcd-d73f-574d-ad30-191a495b187f + + + + + + + + + + + + + + + VOICE 1 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + fe276ab0-ff85-5ab2-898b-ed8075966655 + + + + + + + + + + + VOICE 2 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + b36d9fe8-1d28-5e73-9188-b569959c7a35 + + + + + + + + + + + VOICE 3 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + 8581a420-1ba2-5d16-a609-c9a592c237c5 + + + + + + + + + + + VOICE 4 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + cb84da0a-7689-587d-8688-e97d2e4c3449 + + + + + + + + + + + 24 PPR / PUSH + RadianPanel:Bourns_PEC11R4_RearFacing_Switch + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + + PEC11R-4220F-S0024 + Bourns + RadianPanel:Bourns_PEC11R4_RearFacing_Switch + + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + + + + + + + + 82881ed2-d2b6-51a6-9dad-cffbe9d62def + + + + + + + + + + + + + + + + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + IPS1-110-01-L-D + Samtec + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + + + + + + + 8d29a3b6-4dc8-5d80-8428-86e24030d339 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10k linear / TENSION + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + 7509de8e-e60c-5e1e-9ec3-c1c2df981adc + + + + + + + + + + + + + + 10k linear / DECAY + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + feaf009e-cdb0-5dd4-a19f-e89862601cfb + + + + + + + + + + + + + + 10k linear / CHAOS + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + 6050cafe-321e-5010-9ad6-cdd72088f2d6 + + + + + + + + + + + + + + 10k linear / DRIVE + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + cb6c0109-b436-5916-be99-c5b95f57a16b + + + + + + + + + + + + + + 10k linear / DELAY + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + a77ff7f6-ae92-50bd-b28b-442cd55be9b6 + + + + + + + + + + + + + + 10k linear / REVERB + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + 0849b9e4-ac33-55b8-87e2-939f457734af + + + + + + + + + + + + + + MODE / SPDT ON-ON + RadianPanel:E_Switch_100SP_M2 + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + + 100SP1T1B1M2REH + E-Switch + RadianPanel:E_Switch_100SP_M2 + + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + + + + + + + + f5afaab2-c860-5fc4-9b76-5a05e19eaa7a + + + + + + + + + + + + PITCH 0-5V + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + 1d1426a6-6ee9-5869-8b4b-7ecb976e988e + + + + + + + + + + + + MOD + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + c1806fec-6f4c-552c-ac14-80ec675f5a36 + + + + + + + + + + + + GATE + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + be78fd5a-3121-50f1-a6c8-33469a59e66e + + + + + + + + + + + + LINE L + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + 20a12c22-8872-522b-8afe-80cd0acffe87 + + + + + + + + + + + + LINE R + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + 39bd0795-f68c-5b3f-83ac-033c8b0bcb76 + + + + + + + + + + + + 22-27-2021 + RadianPanel:Molex_22-27-2021_J306_B + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + 22-27-2021 + + RadianPanel:Molex_22-27-2021_J306_B + + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + + + + + + + f536e084-c6a1-57ea-8653-b1afeea3b2ff + + + + + + + + + + + 100nF + RadianPanel:C_0603 + 16V X7R; verify effective capacitance at DC bias + + SELECT 100nF 16V X7R 0603 + + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + 60f3a6c1-6f01-5457-bd28-d2f52e211c96 + + + + + + + + + + + 1uF + RadianPanel:C_0805 + 16V X7R; verify effective capacitance at DC bias + + SELECT 1uF 16V X7R 0805 + + RadianPanel:C_0805 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + 9b8308d0-0230-537b-ac42-dd90818e7824 + + + + + + + + + + + BAT54S + RadianPanel:SOT23_BAT54S + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + + BAT54S,215 + Nexperia + RadianPanel:SOT23_BAT54S + + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + + + + + + + + 0a9cb6cd-78cb-5760-9975-5324be4a7a45 + + + + + + + + + + + + 450301014042 + RadianPanel:Wurth_450301014042_Exact_B + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + 450301014042 + + RadianPanel:Wurth_450301014042_Exact_B + + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + + + + + + + 7a1dc449-3659-51a2-b518-7001903ac8ef + + + + + + + + + + + + 200k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 200k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 4f0fc251-9961-5f36-90aa-92cff98b7d48 + + + + + + + + + + + 100k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 100k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 8186e4ec-ba27-5931-9775-980ea06efde9 + + + + + + + + + + + 200k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 200k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 86815e7d-c360-516d-afff-46eb3b0d64c0 + + + + + + + + + + + 10k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 10k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 45109df0-d108-5e40-988e-420c2d961340 + + + + + + + + + + + 10k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 10k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 5a1e97fe-608e-588b-abb0-73dfd93ea8dd + + + + + + + + + + + VREF25 + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 9a57579e-c67c-5118-aa2a-a9574281fbeb + + + + + + + + + + MOD_BIPOLAR + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 2d0eae80-797a-549c-a27f-4473fbcee434 + + + + + + + + + + OPA2192ID + RadianPanel:SOIC8_3.9x4.9_P1.27 + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + + OPA2192ID + Texas Instruments + RadianPanel:SOIC8_3.9x4.9_P1.27 + + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + + + + + + + + 76da6519-7887-5b94-ad4a-2323d80f01ec + + + + + + + + + + + + + + + + + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + IPS1-110-01-L-D + Samtec + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + + + + + + + 37c3ba3a-67a8-53b0-9b31-8f009dd72af4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 22-27-2061 + RadianPanel:Molex_22-27-2061_J202_B + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + 22-27-2061 + + RadianPanel:Molex_22-27-2061_J202_B + + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + + + + + + + 6e352fab-9100-5920-bc40-ba528cdf06e9 + + + + + + + + + + + + + + + PROGRAM / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + Internal service push button, accessible after module removal. + + B3F-1000 + Omron + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + Internal service push button, accessible after module removal. + + + + + + + + 6ac8d041-74b6-51e1-b114-8a9f2fd7723c + + + + + + + + + + + RESET / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + B3F-1000 + Omron + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + + + + + + + + + ac438e8b-9f2d-50a4-ab02-b0bd7ac6245f + + + + + + + + + + + + + 50V X7R; verify effective capacitance at DC bias + + C + 10uF + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + + 50V X7R; verify effective capacitance at DC bias + + C + 100nF + RadianPanel:C_0603 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + + 16V X7R; verify effective capacitance at DC bias + + C + 100nF + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + + 16V X7R; verify effective capacitance at DC bias + + C + 1uF + RadianPanel:C_0805 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + + 16V X7R; verify effective capacitance at DC bias + + C + 100nF + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + + 25V X7R; verify effective capacitance at DC bias + + C + 22uF + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + + 25V X7R; verify effective capacitance at DC bias + + C + 22uF + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + + 50V C0G; verify effective capacitance at DC bias + + C + 75pF + RadianPanel:C_0603 + + 50V C0G; verify effective capacitance at DC bias + + + + + + + + + 50V X7R; verify effective capacitance at DC bias + + C + 10uF + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + D + SS54 / OR + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + Vishay + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 1 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 2 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 3 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 4 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + D + SS54 / OR + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + Vishay + + + + + + + + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + + D + SMBJ15A + RadianPanel:D_SMB + + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + Vishay + + + + + + + + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + + D + BAT54S + RadianPanel:SOT23_BAT54S + + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + Nexperia + + + + + + + + + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + + ENC + 24 PPR / PUSH + RadianPanel:Bourns_PEC11R4_RearFacing_Switch + + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + Bourns + + + + + + + + + + + + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + F + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + F + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + J + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + Samtec + + + + + + + + + + + + + + + + + + + + + + + + + + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + J + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + Samtec + + + + + + + + + + + + + + + + + + + + + + + + + + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + J + 61201021621 + RadianPanel:Wurth_61201021621_Exact_B + + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + + + + + + + + + + + + + + + + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + J + 22-27-2021 + RadianPanel:Molex_22-27-2021_J201_B + + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + + + + + + + + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + J + 22-27-2061 + RadianPanel:Molex_22-27-2061_J202_B + + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + + + + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + PITCH 0-5V + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + MOD + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + GATE + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + LINE L + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + LINE R + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + J + 22-27-2021 + RadianPanel:Molex_22-27-2021_J306_B + + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + + + + + + + + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + JP + 450301014042 + RadianPanel:Wurth_450301014042_Exact_B + + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + + + + + + + + + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + + L + 10uH 4A / Isat7.5A + RadianPanel:Bourns_SRP7050TA + + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + Bourns + + + + + + + + Resistor 1% + + R + 100k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 1% + + R + 13.3k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 0.1% + + R + 200k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 100k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 200k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 10k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 10k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 1% + + R + 511k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 1% + + R + 105k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 1% + + R + 49.9 + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / TENSION + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / DECAY + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / CHAOS + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / DRIVE + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / DELAY + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / REVERB + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + + SW + MODE / SPDT ON-ON + RadianPanel:E_Switch_100SP_M2 + + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + E-Switch + + + + + + + + + Internal service push button, accessible after module removal. + + SW + PROGRAM / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + Internal service push button, accessible after module removal. + Omron + + + + + + + + + SW + RESET / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + + Omron + + + + + + + + Exposed soldermask aperture, no component. + + TP + GND + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + VIN5 + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + VRAW + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + VREF25 + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + MOD_BIPOLAR + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + + U + TPS54302DDCR + RadianPanel:TI_DDC0006A_SOT23_6 + + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + Texas Instruments + + + + + + + + + + + + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + + U + OPA2192ID + RadianPanel:SOIC8_3.9x4.9_P1.27 + + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + Texas Instruments + + + + + + + + + + + + + + + + ${KIPRJMOD}/../library/RadianPanel.kicad_sym + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/panel/design/routing.json b/hardware/panel/design/routing.json new file mode 100644 index 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J100/J17 is the regulated 5 V direct-stack feed to the mainboard.", + "Diode OR prevents positive-rail backfeed; shared GND is not galvanic isolation. Unused rack pins are NC.", + "TPS54302 3 A rating is NOT a measured system current rating. Fuse selection / inrush / TVS / thermal review required.", + "Native plane refill and DRC required. 5.08 V nominal TI feedback values; never connect +12 V to main J1." + ], + "controls": [ + "No additional pot wiper RC or LED series resistors: these are already on the RADIAN mainboard.", + "RV physical pin 1 = CCW/GND; physical pin 3 = CW/VREF25. This is not the main header pin order.", + "Encoder part changes to 20 mm shaft / 7 mm bushing. Match knob heights and verify turn direction.", + "SW1 logic mapping depends on installed orientation and firmware. Mechanical tab pins are intentionally NC." + ], + "io": [ + "Pitch and Gate follow the existing mainboard front ends. LINE L/R are NOT new modular-level or headphone drivers.", + "WQP518MA: 1=SLEEVE, 2=NORMAL, 3=TIP. Inputs normal to ground; output normal pins intentionally NC.", + "MIDI uses exact Molex 22-27-2021 J306 to a short two-wire lead into the enclosure-mounted Same Sky SDS-50J. Keep DIN pin 2/shield isolated from board GND.", + "Input overvoltage, unpowered behavior, jack insertion shorts and output back-drive still need bench validation." + ], + "mod": [ + "JP1 is Wurth 450301014042 SPDT: pin 1 common to pin 3 selects direct unipolar MOD_RAW.", + "JP1 pin 1 common to pin 2 selects MOD_BIPOLAR. Ideal Vout = 0.5*Vin + VREF25. -5/0/+5 V -> 0/2.5/5 V.", + "5 V op-amp cannot reach exact rails under load. Endpoints, tolerance, saturation and calibration need testing.", + "Do not rescale the PITCH input implicitly. Bipolar MOD requires a matching firmware range/zero configuration." + ], + "service": [ + "Internal-only JTAG, PROGRAM and RESET. J202 is exact Molex 22-27-2061; no additional exterior cutouts assumed.", + "Keep programming cables short and verify the actual programmer pinout. No level shifting is added." + ] + }, + "titles": { + "power": "01 | POWER INPUTS AND 5 V CONVERTER", + "controls": "02 | FRONT-PANEL CONTROLS", + "io": "03 | PATCH JACKS AND MIDI", + "mod": "04 | OPTIONAL BIPOLAR MODULATION", + "service": "05 | INTERNAL SERVICE ACCESS" + } +} \ No newline at end of file diff --git a/hardware/panel/design/service.kicad_sch b/hardware/panel/design/service.kicad_sch new file mode 100644 index 0000000..f4a8595 --- /dev/null +++ b/hardware/panel/design/service.kicad_sch @@ -0,0 +1,1269 @@ +(kicad_sch + (version 20231120) + (generator "radian_panel_generator") + (uuid "5b54220b-44a3-599b-82a2-32b92902b7db") + (paper "A2") + (title_block + (title "05 | INTERNAL SERVICE ACCESS") + (date "2026-09-15") + (rev "P1 DRAFT") + (comment 1 "Native ERC, footprint verification and hardware testing REQUIRED")) + (lib_symbols + (symbol "RadianPanel:J101" + (pin_names + (offset 0.508)) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 29.209999999999997 0) + (effects + (font + (size 1.27 1.27)))) + (property "Value" "IPS1-110-01-L-D" + (at 0 -29.209999999999997 0) + (effects + (font + (size 1.27 1.27)))) + (property "Footprint" "RadianPanel:Stack_2x10_P2.54" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (symbol "J101_0_1" + (rectangle + (start -10.16 26.669999999999998) + (end 10.16 -26.669999999999998) + (stroke + (width 0.254) + (type default)) + (fill + (type background)))) + (symbol "J101_1_1" + (pin passive line + (at -12.7 24.13 0) + (length 2.54) + (name "1" + (effects + (font + (size 1.0 1.0)))) + (number "1" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 21.59 0) + (length 2.54) + (name "2" + (effects + (font + (size 1.0 1.0)))) + (number "2" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 19.05 0) + (length 2.54) + (name "3" + (effects + (font + (size 1.0 1.0)))) + (number "3" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 16.51 0) + (length 2.54) + (name "4" + (effects + (font + (size 1.0 1.0)))) + (number "4" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 13.97 0) + (length 2.54) + (name "5" + (effects + (font + (size 1.0 1.0)))) + (number "5" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 11.43 0) + (length 2.54) + (name "6" + (effects + (font + (size 1.0 1.0)))) + (number "6" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 8.89 0) + (length 2.54) + (name "7" + (effects + (font + (size 1.0 1.0)))) + (number "7" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 6.35 0) + (length 2.54) + (name "8" + (effects + (font + (size 1.0 1.0)))) + (number "8" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 3.81 0) + (length 2.54) + (name "9" + (effects + (font + (size 1.0 1.0)))) + (number "9" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 1.27 0) + (length 2.54) + (name "10" + (effects + (font + (size 1.0 1.0)))) + (number "10" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -1.27 0) + (length 2.54) + (name "11" + (effects + (font + (size 1.0 1.0)))) + (number "11" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -3.81 0) + (length 2.54) + (name "12" + (effects + (font + (size 1.0 1.0)))) + (number "12" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -6.35 0) + (length 2.54) + (name "13" + (effects + (font + (size 1.0 1.0)))) + (number "13" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -8.89 0) + (length 2.54) + (name "14" + (effects + (font + (size 1.0 1.0)))) + (number "14" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -11.43 0) + (length 2.54) + (name "15" + (effects + (font + (size 1.0 1.0)))) + (number "15" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -13.97 0) + (length 2.54) + (name "16" + (effects + (font + (size 1.0 1.0)))) + (number "16" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -16.51 0) + (length 2.54) + (name "17" + (effects + (font + (size 1.0 1.0)))) + (number "17" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -19.05 0) + (length 2.54) + (name "18" + (effects + (font + (size 1.0 1.0)))) + (number "18" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -21.59 0) + (length 2.54) + (name "19" + (effects + (font + (size 1.0 1.0)))) + (number "19" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -24.13 0) + (length 2.54) + (name "20" + (effects + (font + (size 1.0 1.0)))) + (number "20" + (effects + (font + (size 1.0 1.0)))))) + (property "Description" "Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. 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Short cable, validate JTAG frequency." + (at 219.71 72.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "" + (at 219.71 72.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 207.01 66.04) + (xy 201.93 66.04)) + (stroke + (width 0) + (type default)) + (uuid "70101bd5-7f73-5e15-b83e-9e4c2df89f65")) + (global_label "V3V3" + (shape bidirectional) + (at 201.93 66.04 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "0a7059a4-9ade-50af-a919-c75817eadfc0")) + (wire + (pts + (xy 207.01 68.58) + (xy 201.93 68.58)) + (stroke + (width 0) + (type default)) + (uuid "0fe7f572-07f6-517e-8262-f4ed3f925e82")) + (global_label "GND" + (shape bidirectional) + (at 201.93 68.58 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "c724b6f5-ddae-5b70-8768-493a5c6e285d")) + (wire + (pts + (xy 207.01 71.12) + (xy 201.93 71.12)) + (stroke + (width 0) + (type default)) + (uuid "bdf4b630-d10d-5f2f-a893-1297349a2863")) + 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bidirectional) + (at 201.93 78.74 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "e8265240-b892-5d2c-9dae-f4f1b959dad5")) + (symbol + (lib_id "RadianPanel:SW3") + (at 360.68 72.39 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "6ac8d041-74b6-51e1-b114-8a9f2fd7723c") + (property "Reference" "SW3" + (at 360.68 63.31 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "PROGRAM / SERVICE" + (at 360.68 81.47 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:SW_PUSH_6x6_P6.5x4.5" + (at 360.68 72.39 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "B3F-1000" + (at 360.68 72.39 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "3f0f9bc2-46a4-52c5-9c65-a24bb2e3e043")) + (pin "2" + (uuid "284544d9-cc6d-52a4-a849-cc0e8637627d")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/dd60d741-95e3-5383-9836-1c68c07ca20b" + (reference "SW3") + (unit 1)))) + (property "Description" "Internal service push button, accessible after module removal." + (at 360.68 72.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "Omron" + (at 360.68 72.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 347.98 72.39) + (xy 342.9 72.39)) + (stroke + (width 0) + (type default)) + (uuid "6378f22e-4cef-5262-b215-e1294c752c62")) + (global_label "PROGRAM_B" + (shape bidirectional) + (at 342.9 72.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "60961659-7bb6-53e1-a42b-947b20ee5728")) + (wire + (pts + (xy 373.38 72.39) + (xy 378.46 72.39)) + (stroke + (width 0) + (type default)) + (uuid "85949e38-a730-5e23-b9a3-5c7292147b55")) + (global_label "GND" + (shape bidirectional) + (at 378.46 72.39 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "df6eb7f2-fe20-55b0-a627-23e6069ce9f4")) + (symbol + (lib_id "RadianPanel:SW4") + (at 501.65 72.39 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "ac438e8b-9f2d-50a4-ab02-b0bd7ac6245f") + (property "Reference" "SW4" + (at 501.65 63.31 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "RESET / SERVICE" + (at 501.65 81.47 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:SW_PUSH_6x6_P6.5x4.5" + (at 501.65 72.39 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "B3F-1000" + (at 501.65 72.39 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "5611b965-f527-586d-829d-002c94ca8eab")) + (pin "2" + (uuid "cc1e170b-c9f2-5e95-afe4-b92d3192a23b")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/dd60d741-95e3-5383-9836-1c68c07ca20b" + (reference "SW4") + (unit 1)))) + (property "Description" "" + (at 501.65 72.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "Omron" + (at 501.65 72.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 488.95 72.39) + (xy 483.87 72.39)) + (stroke + (width 0) + (type default)) + (uuid "92fdda4e-f82a-54d1-9b30-d77bcadc6a3e")) + (global_label "reset_n" + (shape bidirectional) + (at 483.87 72.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "a452af3b-43bf-522d-88ce-df742d2899de")) + (wire + (pts + (xy 514.35 72.39) + (xy 519.43 72.39)) + (stroke + (width 0) + (type default)) + (uuid "e6de8948-eb33-5cbc-b13f-3949e741cf7d")) + (global_label "GND" + (shape bidirectional) + (at 519.43 72.39 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "c12a8b28-4967-5280-8423-3e2a5e09b3f8")) + (text "Internal-only JTAG, PROGRAM and RESET. No additional exterior cutouts assumed." + (at 20 365 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "1d38c6c8-fa65-57f4-9568-c8bbae38da96")) + (text "Keep programming cables short and verify the actual programmer pinout. No level shifting is added." + (at 20 373 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "8a0077e8-a3e1-58f5-bedc-11425b2109e2"))) diff --git a/hardware/panel/design/sym-lib-table b/hardware/panel/design/sym-lib-table new file mode 100644 index 0000000..644d9ed --- /dev/null +++ b/hardware/panel/design/sym-lib-table @@ -0,0 +1 @@ +(sym_lib_table (version 7) (lib (name "RadianPanel") (type "KiCad") (uri "${KIPRJMOD}/../library/RadianPanel.kicad_sym") (options "") (descr "Embedded exact pin graph for RADIAN Panel P1"))) diff --git a/hardware/panel/docs/BOM.csv b/hardware/panel/docs/BOM.csv new file mode 100644 index 0000000..0f5955d --- /dev/null +++ b/hardware/panel/docs/BOM.csv @@ -0,0 +1,60 @@ +Reference,Value,Manufacturer,MPN_or_selection_gate,Footprint,Side,X_panel_mm,Y_panel_mm,DNP,Notes +J100,IPS1-110-01-L-D,Samtec,IPS1-110-01-L-D,RadianPanel:Stack_2x10_P2.54,B,124.0,61.75,False,Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. +J101,IPS1-110-01-L-D,Samtec,IPS1-110-01-L-D,RadianPanel:Stack_2x10_P2.54,B,43.0,72.25,False,Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. +RV1,10k linear / TENSION,Bourns,PTV09A-4020F-B103,RadianPanel:Bourns_PTV09A4_RearFacing,F,38.0,96.0,False,"Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC." +RV2,10k linear / DECAY,Bourns,PTV09A-4020F-B103,RadianPanel:Bourns_PTV09A4_RearFacing,F,76.0,96.0,False,"Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC." +RV3,10k linear / CHAOS,Bourns,PTV09A-4020F-B103,RadianPanel:Bourns_PTV09A4_RearFacing,F,114.0,96.0,False,"Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC." +RV4,10k linear / DRIVE,Bourns,PTV09A-4020F-B103,RadianPanel:Bourns_PTV09A4_RearFacing,F,66.0,70.0,False,"Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC." +RV5,10k linear / DELAY,Bourns,PTV09A-4020F-B103,RadianPanel:Bourns_PTV09A4_RearFacing,F,88.0,70.0,False,"Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC." +RV6,10k linear / REVERB,Bourns,PTV09A-4020F-B103,RadianPanel:Bourns_PTV09A4_RearFacing,F,110.0,70.0,False,"Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC." +ENC1,24 PPR / PUSH,Bourns,PEC11R-4220F-S0024,RadianPanel:Bourns_PEC11R4_RearFacing_Switch,F,42.0,43.0,False,20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. +SW1,MODE / SPDT ON-ON,E-Switch,100SP1T1B1M2REH,RadianPanel:E_Switch_100SP_M2,F,150.5,84.5,False,"Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required." +D10,VOICE 1,Kingbright,L-934GD,RadianPanel:LED_D3.0_P2.54,F,124.0,108.0,False,"3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." +D11,VOICE 2,Kingbright,L-934GD,RadianPanel:LED_D3.0_P2.54,F,134.0,108.0,False,"3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." +D12,VOICE 3,Kingbright,L-934GD,RadianPanel:LED_D3.0_P2.54,F,144.0,108.0,False,"3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." +D13,VOICE 4,Kingbright,L-934GD,RadianPanel:LED_D3.0_P2.54,F,154.0,108.0,False,"3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." +J301,PITCH 0-5V,QingPu / Thonk,WQP518MA (Thonkiconn/PJ398SM),RadianPanel:WQP518MA_PJ398SM_Vertical,F,186.5,99.0,False,"Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check." +J302,MOD,QingPu / Thonk,WQP518MA (Thonkiconn/PJ398SM),RadianPanel:WQP518MA_PJ398SM_Vertical,F,186.5,81.0,False,"Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check." +J303,GATE,QingPu / Thonk,WQP518MA (Thonkiconn/PJ398SM),RadianPanel:WQP518MA_PJ398SM_Vertical,F,186.5,63.0,False,"Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check." +J304,LINE L,QingPu / Thonk,WQP518MA (Thonkiconn/PJ398SM),RadianPanel:WQP518MA_PJ398SM_Vertical,F,186.5,45.0,False,"Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check." +J305,LINE R,QingPu / Thonk,WQP518MA (Thonkiconn/PJ398SM),RadianPanel:WQP518MA_PJ398SM_Vertical,F,186.5,27.0,False,"Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check." +J306,22-27-2021,Molex,22-27-2021,RadianPanel:Molex_22-27-2021_J306_B,B,57.5,39.0,False,Exact KK-254 2-circuit friction-lock header to retained Same Sky SDS-50J MIDI DIN pins 4 and 5. No DIN 2/shield-to-GND connection. +J200,61201021621,Wurth Elektronik,61201021621,RadianPanel:Wurth_61201021621_Exact_B,B,174.0,64.0,False,"Exact keyed WR-BHD 2x5 2.54 mm header. Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections." +J201,22-27-2021,Molex,22-27-2021,RadianPanel:Molex_22-27-2021_J201_B,B,26.0,52.0,False,Exact KK-254 2-circuit friction-lock header from the chassis-mounted 12 V DC inlet. NOT a 5 V inlet. +F1,2A FUSE / >=32V,,SELECT 2 A >=32 V 1206 fuse,RadianPanel:Fuse_1206,F,53.0,65.0,False,"Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate." +F2,2A FUSE / >=32V,,SELECT 2 A >=32 V 1206 fuse,RadianPanel:Fuse_1206,F,26.0,59.0,False,"Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate." +D1,SS54 / OR,Vishay,SS54-E3/57T,RadianPanel:D_SMB,F,44.0,65.0,False,"Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature." +D2,SS54 / OR,Vishay,SS54-E3/57T,RadianPanel:D_SMB,F,35.0,59.0,False,"Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature." +D3,SMBJ15A,Vishay,SMBJ15A-E3/52,RadianPanel:D_SMB,F,25.0,46.0,False,Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. +U1,TPS54302DDCR,Texas Instruments,TPS54302DDCR,RadianPanel:TI_DDC0006A_SOT23_6,F,34.0,25.0,False,"3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit." +L1,10uH 4A / Isat7.5A,Bourns,SRP7050TA-100M,RadianPanel:Bourns_SRP7050TA,F,26.0,25.0,False,4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. +C1,10uF,,SELECT 10uF 50V X7R 1210,RadianPanel:C_1210,F,31.0,18.0,False,50V X7R; verify effective capacitance at DC bias +C2,100nF,,SELECT 100nF 50V X7R 0603,RadianPanel:C_0603,F,32.0,21.5,False,50V X7R; verify effective capacitance at DC bias +C3,100nF,,SELECT 100nF 16V X7R 0603,RadianPanel:C_0603,F,34.0,29.0,False,16V X7R; verify effective capacitance at DC bias +C4,22uF,,SELECT 22uF 25V X7R 1210,RadianPanel:C_1210,F,23.0,33.0,False,25V X7R; verify effective capacitance at DC bias +C5,22uF,,SELECT 22uF 25V X7R 1210,RadianPanel:C_1210,F,29.0,33.0,False,25V X7R; verify effective capacitance at DC bias +R1,100k,,SELECT 100k 1% 0603,RadianPanel:R_0603,F,39.5,27.0,False,Resistor 1% +R2,13.3k,,SELECT 13.3k 1% 0603,RadianPanel:R_0603,F,39.0,20.0,False,Resistor 1% +R3,511k,,SELECT 511k 1% 0603,RadianPanel:R_0603,F,46.0,23.0,False,Resistor 1% +R4,105k,,SELECT 105k 1% 0603,RadianPanel:R_0603,F,43.0,19.0,False,Resistor 1% +R5,49.9,,SELECT 49.9 1% 0603,RadianPanel:R_0603,F,39.0,32.0,False,Resistor 1% +C6,75pF,,SELECT 75pF 50V C0G 0603,RadianPanel:C_0603,F,43.0,27.0,False,50V C0G; verify effective capacitance at DC bias +C7,10uF,,SELECT 10uF 50V X7R 1210,RadianPanel:C_1210,F,43.0,59.0,False,50V X7R; verify effective capacitance at DC bias +JP1,450301014042,Wurth Elektronik,450301014042,RadianPanel:Wurth_450301014042_Exact_B,B,165.5,88.0,False,Actual SPDT configuration switch replaces the removable shunt. One throw selects direct unipolar MOD_RAW; the other selects MOD_BIPOLAR. NOT the front MODE switch. +U2,OPA2192ID,Texas Instruments,OPA2192ID,RadianPanel:SOIC8_3.9x4.9_P1.27,F,151.0,67.0,False,"A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping." +R20,200k,,SELECT 200k 0.1% 0603,RadianPanel:R_0603,F,164.0,75.0,False,Resistor 0.1% +R21,100k,,SELECT 100k 0.1% 0603,RadianPanel:R_0603,F,158.0,75.0,False,Resistor 0.1% +R22,200k,,SELECT 200k 0.1% 0603,RadianPanel:R_0603,F,164.0,71.0,False,Resistor 0.1% +R23,10k,,SELECT 10k 0.1% 0603,RadianPanel:R_0603,F,159.5,57.0,False,Resistor 0.1% +R24,10k,,SELECT 10k 0.1% 0603,RadianPanel:R_0603,F,163.0,59.0,False,Resistor 0.1% +D4,BAT54S,Nexperia,"BAT54S,215",RadianPanel:SOT23_BAT54S,F,166.0,65.0,False,"Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior." +C20,100nF,,SELECT 100nF 16V X7R 0603,RadianPanel:C_0603,F,157.0,69.0,False,16V X7R; verify effective capacitance at DC bias +C21,1uF,,SELECT 1uF 16V X7R 0805,RadianPanel:C_0805,F,149.0,74.0,False,16V X7R; verify effective capacitance at DC bias +J202,22-27-2061,Molex,22-27-2061,RadianPanel:Molex_22-27-2061_J202_B,B,131.0,29.0,False,Exact KK-254 6-circuit friction-lock service header; pin-for-pin to the JTAG nets already carried through J101/J18. No level conversion; validate JTAG frequency. +SW3,PROGRAM / SERVICE,Omron,B3F-1000,RadianPanel:SW_PUSH_6x6_P6.5x4.5,B,118.4,25.0,False,"Internal service push button, accessible after module removal." +SW4,RESET / SERVICE,Omron,B3F-1000,RadianPanel:SW_PUSH_6x6_P6.5x4.5,B,146.0,26.0,False, +TP1,GND,,PCB test pad,RadianPanel:TestPoint_D2,B,25.0,42.0,False,"Exposed soldermask aperture, no component." +TP2,VIN5,,PCB test pad,RadianPanel:TestPoint_D2,B,29.0,42.0,False,"Exposed soldermask aperture, no component." +TP3,VRAW,,PCB test pad,RadianPanel:TestPoint_D2,B,48.0,59.0,False,"Exposed soldermask aperture, no component." +TP4,VREF25,,PCB test pad,RadianPanel:TestPoint_D2,B,149.0,62.0,False,"Exposed soldermask aperture, no component." +TP5,MOD_BIPOLAR,,PCB test pad,RadianPanel:TestPoint_D2,B,165.0,61.0,False,"Exposed soldermask aperture, no component." diff --git a/hardware/panel/docs/README.md b/hardware/panel/docs/README.md new file mode 100644 index 0000000..db5f4b6 --- /dev/null +++ b/hardware/panel/docs/README.md @@ -0,0 +1,117 @@ +# RADIAN Panel / Interface P1 — engineering handoff + +Revision P1 direct-stack / production-connector update, 2026-09-18. Built around the existing oxide-red 40 HP / 3U RADIAN front panel and the Rev F.1 desktop dock. The mainboard is electrically extended for the direct stack and three FX-pot ADC channels. + +## 1. Honest completion status + +This is a **signal-routed electrical and mechanical prototype design**, not another set of blank carrier-board rectangles. There is one electrical graph, a native KiCad project with five child schematic sheets, explicit part-to-pad net assignments, actual copper segments/vias, panel drilling references, and a corresponding 3D reference assembly. + +It remains an engineering prototype. Native Backplane KiCad 10.0.6 has now loaded and checked the files: ERC, DRC, ground connectivity and schematic/PCB parity have zero findings. The inner GND zones are filled. Electrical function, component selection and physical/thermal/fault performance remain unverified. See `../reports/native/` and `../../REPAIR_STATUS.md`. + +The five schematic sheets use named global nets and exact pin-labelled blocks. The current PDF is exported by native KiCad; a signal-flow and circuit-function review is still required. + +## 2. What is on this single PCB + +**Controls:** RV1–RV6 are 10 kOhm linear Bourns PTV09A-4020F-B103 pots: TENSION, DECAY, CHAOS, DRIVE, DELAY and REVERB. ENC1 is a Bourns PEC11R-4220F-S0024 encoder with push switch. SW1 is an E-Switch 100-series SPDT ON-ON switch and D10–D13 are 3 mm status LEDs. All six pot wipers are filtered at the mainboard ADC inputs. + +**Patch connections:** J301 PITCH, J302 MOD, J303 GATE, J304 LINE L, J305 LINE R. All five use vertical WQP518MA/PJ398SM-style mono sockets. Input normal contacts are grounded when unplugged; output normal contacts are left unused. The mandatory under-barrel clearance hole is included in each footprint. The previous right-angle Same Sky jacks are not used in this planar board design. + +**MIDI:** J306 is now an exact Molex KK-254 **22-27-2021** 2-circuit friction-lock header rather than generic pins. A short two-wire harness goes to the enclosure-mounted Same Sky **SDS-50J** DIN receptacle, pins 4 and 5 respectively. Those nets reach the mainboard through J101↔J18. Do not connect DIN pin 2/shield to PCB ground: the mainboard optocoupler provides the intended input isolation. The old DIN carrier PCB remains retired; the SDS-50J retainer/case fit still needs first-article verification. + +**Power:** J200 is the exact Wurth **61201021621** keyed 2×5 WR-BHD Eurorack header. J201 is an exact Molex KK-254 **22-27-2021** 2-circuit friction-lock header for the short lead to the selected chassis-mounted Switchcraft **722A** 12 V DC inlet. Independent input fuses, diode-OR source combination, transient suppressor and the TPS54302 buck converter follow. Regulated VIN5 reaches the mainboard through J100↔J17. + +**Optional modulation conditioning:** OPA2192 buffer/summing/gain stage selected by the exact Wurth **450301014042** SPDT mini slide switch at JP1. The removable 3-pin shunt is gone. JP1 is not the front MODE switch. + +**Internal service:** J202 is an exact Molex KK-254 **22-27-2061** 6-circuit friction-lock JTAG header, alongside PROGRAM/RESET switches. These remain behind the panel; access requires removing the module. Their circuitry does not add level translation or new functions to the mainboard. + +## 3. Mainboard connection + +The former individual panel/mainboard cable headers are retired. Panel J100 mates directly with mainboard J17 and panel J101 mates with mainboard J18. Both are 2×10 2.54 mm Samtec mezzanine pairs defined by the shared `../stack/panel-stack.json` contract. + +J17/J100 carries VIN5, GND, VREF25, all six pot wipers, PITCH/MOD/GATE and LINE L/R. J18/J101 carries V3V3/GND, encoder, MODE, four LEDs, MIDI, PROGRAM/RESET and JTAG. The final native boards have all 40 physical pins matched by both net name and assembled XY coordinate. + +Mainboard connector MPN: **IPT1-110-06-L-D**. Panel connector MPN: **IPS1-110-01-L-D**. Fully mated PCB spacing is 19.99 mm, maximum specified spacing is 20.45 mm, and the mechanical support target is about 20.0 mm. Standoffs/supports carry structural load. `mainboard_harness.csv` is retained only as a deprecation pointer to `mainboard_stack.csv`. + +## 4. Power architecture and important change + +**Desktop input for P1 is regulated 12 V, not the earlier direct 5 V inlet proposal.** This choice lets the same protected conversion path serve rack and desktop operation. The selected chassis endpoint is a centre-positive Switchcraft **722A** 2.0 mm DC power jack; it connects to J201 with a short two-wire harness. The case opening/retention and harness strain relief still require first-article verification. The mainboard input remains regulated **5 V**; never connect either external 12 V source directly to main J1. + +J200 uses the exact Wurth **61201021621** keyed module-side **10-pin** WR-BHD header: + +| Pins | Connection | +|---|---| +| 1, 2 | −12 V position, intentionally NC | +| 3–8 | GND | +| 9, 10 | rack +12 V | + +Use a verified **16-pin bus to 10-pin module** ribbon cable. Red stripe identifies the −12 V edge even though this module does not consume that rail. Inspect and continuity-check both ends. The module uses none of the extra bus +5 V/CV/gate signals. A shroud alone is not an assurance that a third-party cable or bus header is wired correctly. This 10-pin choice also avoids bringing the extra 16-pin bus signals into a connector that could be incorrectly reversed. + +F1 and F2 precede Schottky OR diodes. Both source grounds are common. The diodes provide positive-rail backfeed blocking in their intended polarity; this is **not galvanic isolation**, not an ideal-diode power mux and not a complete certification against cable faults. The higher effective source voltage will carry the load. Avoid connecting both supplies during initial testing. + +The TPS54302 circuit uses the TI 5 V application topology with 10 uH inductance, two 22 uF output capacitors, boot capacitor, enable divider and feedback/feed-forward network. Ideal nominal feedback arithmetic gives about **5.079 V**, before component/IC tolerance and cable losses. The 3 A value is the converter IC's design target, **not a measured RADIAN load or guaranteed board rating**. The actual FPGA current, bus budget, dropout at startup, current-limit behavior, input diode losses, copper temperature and switcher stability require review and measurement. + +The default fuse entries are explicitly `SELECT 2 A >=32 V 1206 fuse`. Their final ordering codes, derating, inrush capability and coordination with the SMBJ15A TVS are unresolved. Capacitor rows marked SELECT similarly need exact parts, voltage/DC-bias capacitance checks and purchasing review. Do not treat a nominally correct footprint as selection of a safe part. + +## 5. Signal behavior + +PITCH keeps the existing mainboard input scaling and the original 0–5 V operating range. It is not silently divided by two or offset, so the existing pitch convention is preserved. Wider voltage/fault behavior still needs verification of the mainboard front end. + +JP1 selects MOD with a real SPDT switch: + +| JP1 contact | Behavior | +|---|---| +| **pin 1 ↔ pin 3** | `MOD_RAW` directly to `MOD_IN`; original unipolar 0–5 V behavior | +| **pin 1 ↔ pin 2** | `MOD_BIPOLAR` to `MOD_IN`; nominal `Vout = 0.5 × Vin + VREF25` | + +Nominal bipolar mapping is −5/0/+5 V → 0/2.5/5 V. The op-amp has finite output swing and the real stage cannot exactly reach its rails under load. The sampled resistor-only tolerance report is not a circuit simulation and does not include op-amp swing, offset, bandwidth, saturation, supply or ADC errors. Firmware must know that zero external modulation maps near ADC midscale. Change JP1 only with power off; calibrate the usable range on hardware. + +LINE L/R are the original DAC line outputs, not amplified modular outputs and not headphone drivers. A mono patch plug does not change their electrical level. Gate conditioning and MIDI optoisolation remain on the mainboard; this panel does not duplicate them. Test plug insertion, shorts, back-driven outputs, and powered/unpowered input faults before attaching other equipment. + +## 6. Mechanical interface + +Panel: 202.8 × 128.5 × 2 mm, current nominal 40 HP format. New board envelope: **180.5 × 108 × 1.6 mm**, with intentional DIN/cradle and ventilation windows and edge reliefs around the mainboard support columns. Board front is at **z = −8 mm** relative to the panel rear; board back is −9.6 mm. Coordinates in `design.json`, the DXF and CSV use x right/y up as seen from the front. Native KiCad uses a reflected y coordinate (`128.5 − y`). + +The active controls use two rows: TENSION/DECAY/CHAOS at **(38,96), (76,96), (114,96) mm** with 23 mm reference knobs, and DRIVE/DELAY/REVERB at **(66,70), (88,70), (110,70) mm** with 14 mm reference knobs. MODE is on the retained raised insert at **(150.5,84.5) mm**. The mainboard PCB plane moves 0.46 mm toward the panel so the Samtec pair sits at 19.99 mm fully mated; the four front supports are shortened and the rear spacers extended by the same amount. The rear guard and outer desktop dock body remain unchanged. + +**The CAD is a dimensional/reference study.** J200/J201/J306/J202/JP1 now use selected-part 3D geometry in the panel assembly (Wurth/Molex), while the Samtec direct-stack models remain drawing-derived. The enclosure-mounted Switchcraft 722A and SDS-50J interfaces are still case/reference interfaces rather than a claim of vendor-CAD-certified assembly. Cable plugs, thread/retention details, fastener torque, tolerances and insertion loads are not certified. The encoder rear spacer, jack rear shims and mode rear spacer are proposed mounting-stack allowances to be sample-tested. Knobs and nuts are only reference geometry; exact knobs, nuts/washers, screws and tapped/inserted support details are still to be selected. + +The dock remains included as the desktop configuration. Switchcraft 722A is now the selected 12 V inlet and Same Sky SDS-50J the selected MIDI DIN endpoint, but their enclosure retention, short-harness strain relief, feet/final hardware and thermal design still need physical first-article validation. + +A plain PCB fit-template STL is provided only for a mechanical test print. It is not a conductive PCB, a production drill master, or a substitute for a real board. + +## 7. Checks executed and not executed + +Executed: explicit graph generation; pad-to-pad placement clearance; geometric copper/pad/via and board-edge checking; native ERC/DRC/parity; direct-stack 40-pin net/XY comparison; independent parsing of emitted PCB pad/net assignments; ideal DC arithmetic; and reference CAD solid/intersection checks for the six controls, shifted support planes and Samtec body envelopes. Current case results are in `../reports/case_direct_stack_update.json` and `../reports/case_export_validation.json`. + +Not executed: manufacturer footprint approval, impedance/EMI analysis, power/analog SPICE macro-model simulations, real-component fit, thermal/load/dropout/fault tests, FPGA execution and listening/audio measurements. + +The custom checker uses a simplified nominal copper geometry model. It does not check every KiCad/manufacturer rule, soldermask web, drill plating specification, courtyard, silkscreen or thermal relief. Inner GND fills are deliberately missing from its test scope. + +## 8. Opening, rebuilding and native validation + +Open `design/radian_panel.kicad_pro` in KiCad 10. Keep its root and child schematics, `fp-lib-table`, `sym-lib-table` and sibling `library/`/`cad/` folders together. The embedded symbols make the net graph self-contained, and the local footprint library preserves the draft dimensions. + +`source/verify_native.sh` has been executed with Backplane KiCad 10.0.6. ERC and schematic-parity DRC both exit 0. Its current reports are in `reports/native/`. Rerun after edits; do not silence findings to obtain a passing result. + +Rebuild the generated draft only before doing manual edits, because generators overwrite their files: + +```sh +python source/design_data.py +python source/export_ecad.py +python source/check_placement.py +python source/route_board.py +python source/validate_design.py +python source/render_docs.py +python source/build_cad.py +python source/update_case_direct_stack.py # active P2 case synchronization; previews render when DISPLAY is available +# Optional case integration with your previous unzipped CAD package: +python source/build_cad.py --previous /path/to/RADIAN_RevF1_Desktop_and_Eurorack +``` + +Requirements are in `source/requirements.txt`; ReportLab previews also use locally installed DejaVu Sans fonts. No font files are distributed. The generator's net-labelled schematic is intentionally explicit rather than pretending to be a hand-drafted circuit sheet. See `sources.md` for design provenance. + +## 9. Before money is spent + +Finalize the exact electrical parts and off-board mechanics; run native tools and review the schematic/PCB; print the bare mechanical template and test real switches/jacks/knobs; review input protection, load budget and converter layout with the actual part data. Only then make fabrication exports from a reviewed native KiCad board. + +For first electrical tests, keep the expensive mainboard disconnected. Use current-limited low-voltage bench power, prove the panel converter output, polarity, no-load/load behavior and transients with a dummy load, and measure faults only using a planned safe procedure. Then mate the mainboard through the verified J17/J18 direct stack and bring up power, controls and audio one interface at a time. Do not put mains voltage inside this dock. diff --git a/hardware/panel/docs/drill_reference.csv b/hardware/panel/docs/drill_reference.csv new file mode 100644 index 0000000..7cf474c --- /dev/null +++ b/hardware/panel/docs/drill_reference.csv @@ -0,0 +1,130 @@ +Reference,Pin,X_panel_mm,Y_panel_mm,Drill_mm_or_slot_xy,Type +J101,1,28.27,38.0,1.0,thru_hole +J101,2,25.73,38.0,1.0,thru_hole +J102,1,137.35,22.0,1.0,thru_hole +J102,2,134.81,22.0,1.0,thru_hole +J102,3,132.27,22.0,1.0,thru_hole +J102,4,129.73,22.0,1.0,thru_hole +J102,5,127.19,22.0,1.0,thru_hole +J102,6,124.65,22.0,1.0,thru_hole +J103,1,123.27,16.0,1.0,thru_hole +J103,2,120.73,16.0,1.0,thru_hole +J104,1,146.27,16.0,1.0,thru_hole +J104,2,143.73,16.0,1.0,thru_hole +J105,1,144.54,59.0,1.0,thru_hole +J105,2,142.0,59.0,1.0,thru_hole +J105,3,139.46,59.0,1.0,thru_hole +J106,1,44.54,69.0,1.0,thru_hole +J106,2,42.0,69.0,1.0,thru_hole +J106,3,39.46,69.0,1.0,thru_hole +J107,1,82.54,66.0,1.0,thru_hole +J107,2,80.0,66.0,1.0,thru_hole +J107,3,77.46,66.0,1.0,thru_hole +J108,1,120.54,66.0,1.0,thru_hole +J108,2,118.0,66.0,1.0,thru_hole +J108,3,115.46,66.0,1.0,thru_hole +J109,1,57.08,56.0,1.0,thru_hole +J109,2,54.54,56.0,1.0,thru_hole +J109,3,52.0,56.0,1.0,thru_hole +J109,4,49.46,56.0,1.0,thru_hole +J109,5,46.92,56.0,1.0,thru_hole +J110,1,147.54,70.0,1.0,thru_hole +J110,2,145.0,70.0,1.0,thru_hole +J110,3,142.46,70.0,1.0,thru_hole +J111,1,130.08,99.0,1.0,thru_hole +J111,2,127.54,99.0,1.0,thru_hole +J111,3,125.0,99.0,1.0,thru_hole +J111,4,122.46,99.0,1.0,thru_hole +J111,5,119.92,99.0,1.0,thru_hole +J112,1,165.27,95.0,1.0,thru_hole +J112,2,162.73,95.0,1.0,thru_hole +J113,1,164.27,81.0,1.0,thru_hole +J113,2,161.73,81.0,1.0,thru_hole +J114,1,165.27,54.0,1.0,thru_hole +J114,2,162.73,54.0,1.0,thru_hole +J115,1,58.77,33.0,1.0,thru_hole +J115,2,56.23,33.0,1.0,thru_hole +RV1,1,39.5,77.0,1.0,thru_hole +RV1,2,42.0,77.0,1.0,thru_hole +RV1,3,44.5,77.0,1.0,thru_hole +RV1,MP1,36.7,84.0,"[1.8, 2.2]",thru_hole +RV1,MP2,47.3,84.0,"[1.8, 2.2]",thru_hole +RV2,1,77.5,77.0,1.0,thru_hole +RV2,2,80.0,77.0,1.0,thru_hole +RV2,3,82.5,77.0,1.0,thru_hole +RV2,MP1,74.7,84.0,"[1.8, 2.2]",thru_hole +RV2,MP2,85.3,84.0,"[1.8, 2.2]",thru_hole +RV3,1,115.5,77.0,1.0,thru_hole +RV3,2,118.0,77.0,1.0,thru_hole +RV3,3,120.5,77.0,1.0,thru_hole +RV3,MP1,112.7,84.0,"[1.8, 2.2]",thru_hole +RV3,MP2,123.3,84.0,"[1.8, 2.2]",thru_hole +ENC1,A,39.5,35.5,1.0,thru_hole +ENC1,C,42.0,35.5,1.0,thru_hole +ENC1,B,44.5,35.5,1.0,thru_hole +ENC1,S1,39.5,50.0,1.0,thru_hole +ENC1,S2,44.5,50.0,1.0,thru_hole +ENC1,MP1,35.4,43.0,"[1.8, 2.6]",thru_hole +ENC1,MP2,48.6,43.0,"[1.8, 2.6]",thru_hole +SW1,1,150.5,79.8,1.85,thru_hole +SW1,2,150.5,84.5,1.85,thru_hole +SW1,3,150.5,89.2,1.85,thru_hole +D10,1,122.73,108.0,0.9,thru_hole +D10,2,125.27,108.0,0.9,thru_hole +D11,1,132.73,108.0,0.9,thru_hole +D11,2,135.27,108.0,0.9,thru_hole +D12,1,142.73,108.0,0.9,thru_hole +D12,2,145.27,108.0,0.9,thru_hole +D13,1,152.73,108.0,0.9,thru_hole +D13,2,155.27,108.0,0.9,thru_hole +J301,1,186.5,92.52,"[1.0, 1.9]",thru_hole +J301,2,186.5,95.62,"[1.0, 1.9]",thru_hole +J301,3,186.5,103.92,"[1.0, 1.9]",thru_hole +J301,,186.5,99.0,3,np_thru_hole +J302,1,186.5,74.52,"[1.0, 1.9]",thru_hole +J302,2,186.5,77.62,"[1.0, 1.9]",thru_hole +J302,3,186.5,85.92,"[1.0, 1.9]",thru_hole +J302,,186.5,81.0,3,np_thru_hole +J303,1,186.5,56.52,"[1.0, 1.9]",thru_hole +J303,2,186.5,59.62,"[1.0, 1.9]",thru_hole +J303,3,186.5,67.92,"[1.0, 1.9]",thru_hole +J303,,186.5,63.0,3,np_thru_hole +J304,1,186.5,38.52,"[1.0, 1.9]",thru_hole +J304,2,186.5,41.62,"[1.0, 1.9]",thru_hole +J304,3,186.5,49.92,"[1.0, 1.9]",thru_hole +J304,,186.5,45.0,3,np_thru_hole +J305,1,186.5,20.52,"[1.0, 1.9]",thru_hole +J305,2,186.5,23.62,"[1.0, 1.9]",thru_hole +J305,3,186.5,31.92,"[1.0, 1.9]",thru_hole +J305,,186.5,27.0,3,np_thru_hole +J306,1,58.77,39.0,1.0,thru_hole +J306,2,56.23,39.0,1.0,thru_hole +J200,1,175.27,69.08,1.0,thru_hole +J200,2,172.73,69.08,1.0,thru_hole +J200,3,175.27,66.54,1.0,thru_hole +J200,4,172.73,66.54,1.0,thru_hole +J200,5,175.27,64.0,1.0,thru_hole +J200,6,172.73,64.0,1.0,thru_hole +J200,7,175.27,61.46,1.0,thru_hole +J200,8,172.73,61.46,1.0,thru_hole +J200,9,175.27,58.92,1.0,thru_hole +J200,10,172.73,58.92,1.0,thru_hole +J201,1,27.27,52.0,1.0,thru_hole +J201,2,24.73,52.0,1.0,thru_hole +JP1,1,164.54,88.0,1.0,thru_hole +JP1,2,162.0,88.0,1.0,thru_hole +JP1,3,159.46,88.0,1.0,thru_hole +J202,1,137.35,29.0,1.0,thru_hole +J202,2,134.81,29.0,1.0,thru_hole +J202,3,132.27,29.0,1.0,thru_hole +J202,4,129.73,29.0,1.0,thru_hole +J202,5,127.19,29.0,1.0,thru_hole +J202,6,124.65,29.0,1.0,thru_hole +SW3,1,122.25,22.75,1,thru_hole +SW3,1,122.25,27.25,1,thru_hole +SW3,2,115.75,22.75,1,thru_hole +SW3,2,115.75,27.25,1,thru_hole +SW4,1,149.25,23.75,1,thru_hole +SW4,1,149.25,28.25,1,thru_hole +SW4,2,142.75,23.75,1,thru_hole +SW4,2,142.75,28.25,1,thru_hole diff --git a/hardware/panel/docs/mainboard_harness.csv b/hardware/panel/docs/mainboard_harness.csv new file mode 100644 index 0000000..8e49309 --- /dev/null +++ b/hardware/panel/docs/mainboard_harness.csv @@ -0,0 +1,2 @@ +Status,Replacement +DEPRECATED - direct stack replaces J101..J116 cable harnesses,mainboard_stack.csv diff --git a/hardware/panel/docs/mainboard_stack.csv b/hardware/panel/docs/mainboard_stack.csv new file mode 100644 index 0000000..a5a6ab9 --- /dev/null +++ b/hardware/panel/docs/mainboard_stack.csv @@ -0,0 +1,41 @@ +Stack,Panel_connector,Mainboard_connector,Physical_pin,Net,Panel_X_mm,Panel_Y_mm,Main_X_mm,Main_Y_mm,Note +A,J100,J17,1,GND,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,2,VIN5,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,3,VIN5,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,4,VREF25,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,5,GND,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,6,POT_PITCH_RAW,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,7,POT_DECAY_RAW,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,8,POT_TIMBRE_RAW,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,9,POT_DRIVE_RAW,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,10,POT_DELAY_RAW,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,11,POT_REVERB_RAW,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,12,GND,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,13,PITCH_IN,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,14,MOD_IN,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,15,GATE_IN,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,16,GND,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,17,LINE_L,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,18,GND,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,19,LINE_R,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +A,J100,J17,20,GND,124.0,61.75,36.0,-2.5,Direct board-to-board mating site; no cable harness +B,J101,J18,1,GND,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,2,V3V3,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,3,GND,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,4,ENC_A_RAW,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,5,ENC_B_RAW,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,6,ENC_SW_RAW,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,7,cv_select,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,8,LED0_A,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,9,LED1_A,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,10,LED2_A,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,11,LED3_A,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,12,GND,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,13,MIDI4,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,14,MIDI5,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,15,PROGRAM_B,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,16,reset_n,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,17,JTAG_TCK,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,18,JTAG_TDO,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,19,JTAG_TDI,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness +B,J101,J18,20,JTAG_TMS,43.0,72.25,-45.0,8.0,Direct board-to-board mating site; no cable harness diff --git a/hardware/panel/docs/radian_panel-netlist.txt b/hardware/panel/docs/radian_panel-netlist.txt new file mode 100644 index 0000000..c822aa0 --- /dev/null +++ b/hardware/panel/docs/radian_panel-netlist.txt @@ -0,0 +1,336 @@ +Current repaired native board: radian_panel.kicad_pcb +64 nets + +BOOT (2) + C3.1 + U1.6 + +DESKTOP_12V (2) + F2.1 + J201.1 + +DESKTOP_FUSED (2) + D2.2 + F2.2 + +EN (3) + R3.2 + R4.1 + U1.5 + +ENC_A_RAW (2) + ENC1.A + J101.4 + +ENC_B_RAW (2) + ENC1.B + J101.5 + +ENC_SW_RAW (2) + ENC1.S1 + J101.6 + +FB (4) + C6.2 + R1.2 + R2.1 + U1.4 + +FF_TOP (3) + C6.1 + R1.1 + R5.2 + +GATE_IN (2) + J100.15 + J303.3 + +GND (58) + C1.2 + C2.2 + C20.2 + C21.2 + C4.2 + C5.2 + C7.2 + D10.1 + D11.1 + D12.1 + D13.1 + D3.2 + D4.1 + ENC1.C + ENC1.S2 + J100.1 + J100.12 + J100.16 + J100.18 + J100.20 + J100.5 + J101.1 + J101.12 + J101.3 + J200.3 + J200.4 + J200.5 + J200.6 + J200.7 + J200.8 + J201.2 + J202.2 + J301.1 + J301.2 + J302.1 + J302.2 + J303.1 + J303.2 + J304.1 + J305.1 + R2.2 + R22.2 + R23.2 + R4.2 + RV1.1 + RV2.1 + RV3.1 + RV4.1 + RV5.1 + RV6.1 + SW1.1 + SW3.2 + SW3.2 + SW4.2 + SW4.2 + TP1.1 + U1.1 + U2.4 + +JTAG_TCK (2) + J101.17 + J202.3 + +JTAG_TDI (2) + J101.19 + J202.5 + +JTAG_TDO (2) + J101.18 + J202.4 + +JTAG_TMS (2) + J101.20 + J202.6 + +LED0_A (2) + D10.2 + J101.8 + +LED1_A (2) + D11.2 + J101.9 + +LED2_A (2) + D12.2 + J101.10 + +LED3_A (2) + D13.2 + J101.11 + +LINE_L (2) + J100.17 + J304.3 + +LINE_R (2) + J100.19 + J305.3 + +MIDI4 (2) + J101.13 + J306.1 + +MIDI5 (2) + J101.14 + J306.2 + +MOD_BIPOLAR (4) + JP1.2 + R24.1 + TP5.1 + U2.7 + +MOD_FB (3) + R23.1 + R24.2 + U2.6 + +MOD_IN (2) + J100.14 + JP1.1 + +MOD_RAW (3) + J302.3 + JP1.3 + R20.1 + +MOD_SUM (5) + D4.3 + R20.2 + R21.2 + R22.1 + U2.5 + +PITCH_IN (2) + J100.13 + J301.3 + +POT_DECAY_RAW (2) + J100.7 + RV2.2 + +POT_DELAY_RAW (2) + J100.10 + RV5.2 + +POT_DRIVE_RAW (2) + J100.9 + RV4.2 + +POT_PITCH_RAW (2) + J100.6 + RV1.2 + +POT_REVERB_RAW (2) + J100.11 + RV6.2 + +POT_TIMBRE_RAW (2) + J100.8 + RV3.2 + +PROGRAM_B (3) + J101.15 + SW3.1 + SW3.1 + +RACK_12V (3) + F1.1 + J200.10 + J200.9 + +RACK_FUSED (2) + D1.2 + F1.2 + +SW (3) + C3.2 + L1.2 + U1.2 + +V3V3 (3) + J101.2 + J202.1 + SW1.3 + +VIN5 (11) + C20.1 + C21.1 + C4.1 + C5.1 + D4.2 + J100.2 + J100.3 + L1.1 + R5.1 + TP2.1 + U2.8 + +VRAW (9) + C1.1 + C2.1 + C7.1 + D1.1 + D2.1 + D3.1 + R3.1 + TP3.1 + U1.3 + +VREF25 (9) + J100.4 + RV1.3 + RV2.3 + RV3.3 + RV4.3 + RV5.3 + RV6.3 + TP4.1 + U2.3 + +VREF_BUF (3) + R21.1 + U2.1 + U2.2 + +cv_select (2) + J101.7 + SW1.2 + +reset_n (3) + J101.16 + SW4.1 + SW4.1 + +unconnected-(ENC1-PadMP1) (1) + ENC1.MP1 + +unconnected-(ENC1-PadMP2) (1) + ENC1.MP2 + +unconnected-(J200-Pad1) (1) + J200.1 + +unconnected-(J200-Pad2) (1) + J200.2 + +unconnected-(J304-NORMAL-Pad2) (1) + J304.2 + +unconnected-(J305-NORMAL-Pad2) (1) + J305.2 + +unconnected-(RV1-PadMP1) (1) + RV1.MP1 + +unconnected-(RV1-PadMP2) (1) + RV1.MP2 + +unconnected-(RV2-PadMP1) (1) + RV2.MP1 + +unconnected-(RV2-PadMP2) (1) + RV2.MP2 + +unconnected-(RV3-PadMP1) (1) + RV3.MP1 + +unconnected-(RV3-PadMP2) (1) + RV3.MP2 + +unconnected-(RV4-PadMP1) (1) + RV4.MP1 + +unconnected-(RV4-PadMP2) (1) + RV4.MP2 + +unconnected-(RV5-PadMP1) (1) + RV5.MP1 + +unconnected-(RV5-PadMP2) (1) + RV5.MP2 + +unconnected-(RV6-PadMP1) (1) + RV6.MP1 + +unconnected-(RV6-PadMP2) (1) + RV6.MP2 diff --git a/hardware/panel/docs/sources.md b/hardware/panel/docs/sources.md new file mode 100644 index 0000000..d4b1b02 --- /dev/null +++ b/hardware/panel/docs/sources.md @@ -0,0 +1,59 @@ +# Design sources and provenance + +Accessed/reviewed during P1 creation, 15 September 2026. This list separates user-supplied facts, external datasheets, design choices and unverified assumptions. Prices/stock are not established by this package. + +## User files + +`reference/input_manifest.json` records SHA-256 hashes of the original supplied mainboard files and key datasheets. Mainboard PCB and STEP files were not edited. The matching previous CAD-input hashes establish which hardware revision the fit study used. + +- `courant-panel-interface.csv`: 45 header pin/net entries; authoritative mainboard boundary for this panel. +- `courant-panel-hardware.md`: proposed off-board choices, mainboard 5 V input and 0–5 V CV limitations. These selections were proposals, not frozen purchases. +- `courant.kicad_pcb`, `courant-assembly.step`, `courant-bom.csv`: original board geometry/components. Prior CAD-aligned STEP used for assembly fit reference. +- `Bourns_PTV09_potentiometer.pdf`, pages 1–2: PTV09A configuration 4 bushingless/rear-facing footprint and shaft dimensions. Signal terminals span 5.0 mm with the wiper midway (2.5 mm pitch). Changed neither resistance nor pot variant. +- `Bourns_PEC11R_encoder.pdf`, pages 2–3: rear-facing switch encoder footprint and ordering code. P1 selects 20 mm shaft rather than the original proposed 15 mm shaft, explicitly changing the MPN to PEC11R-4220F-S0024. +- `SameSky_SDS-J_DIN5_socket.pdf`: retained right-angle off-board DIN dimensional context. P1 does not claim this part can mount on the single panel PCB. +- Original Rev F.1 CAD archive: retained panel centres, mainboard alignment, case and dock geometry. Original CAD mechanical-fit results are not reused as P1 validation results. + +## New external electrical/mechanical data + +1. **Texas Instruments, TPS54302 datasheet** (SLVSD79C, March 2026), pinout, 5 V/3 A typical application and layout guidance. Circuit topology and nominal passive values are based on that application; the resulting PCB is not claimed to be TI's validated layout. + https://www.ti.com/lit/ds/symlink/tps54302.pdf + +2. **Bourns SRP7050TA power inductor series**, SRP7050TA-100M row and recommended land pattern. Nominal 10 uH, 4 A Irms and 7.5 A Isat under datasheet conditions; these ratings do not establish the enclosure temperature or system current capability. + https://www.bourns.com/docs/Product-Datasheets/SRP7050TA.pdf + +3. **Texas Instruments OPAx192 datasheet**, OPA2192 pinout and single-supply operation. The modulation equation is a P1 design derivation, not a reproduced reference circuit. Output headroom and dynamics need testing. + https://www.ti.com/lit/ds/symlink/opa2192.pdf + +4. **Thonk WQP518MA/PJ398SM supplier drawing and product page**. This is a supplier's dimensional reference, not a vendor-approved P1 footprint or manufacturer STEP model. The under-barrel hole and three contact positions are derived from the drawing. + https://www.thonk.co.uk/shop/thonkiconn/ + https://www.thonk.co.uk/wp-content/uploads/2018/07/Thonkiconn_Jack_Datasheet-new.jpg + +5. **E-Switch 100-series configurator and family datasheet**. M2 straight PCB pins, T1 actuator, B1 bushing, SP1 ON-ON and proposed R gold-contact option. Exact variant availability and purchased dimensions need confirmation. + https://www.e-switch.com/product/100-series-miniature-toggle-switch/ + https://configured-product-images.s3.amazonaws.com/Datasheets/100.pdf + +6. **E-Switch ST110001 mechanical drawing** for the Q silver-contact version, hosted by Farnell. Used for the common M2 mechanical family (8.89 mm body, 6.35 mm bushing, 4.70 mm terminal pitch, 1.85 mm holes). It is not a specific approval of the selected R-contact variant. + https://www.farnell.com/cad/2341777.pdf + +7. **Doepfer A-100 technical documentation**, module-side 10-pin versus 16-pin connections and available rails/signals. P1 intentionally uses the 10-pin module form because it uses no bus +5/CV/gate. Bus-side connector remains 16-pin with an appropriate 16-to-10 cable. + https://doepfer.de/a100_man/a100t_e.htm + https://www2.doepfer.eu/index.php/en/faqs/item/orientation-of-bus-connection-cables + +8. **KiCad 10 CLI documentation**, native netlist/ERC/DRC and `--refill-zones --save-board` options. `source/verify_native.sh` uses documented commands, but was not executed in the creation environment. + https://docs.kicad.org/10.0/en/cli/cli.html + +## Explicit P1 choices, not facts supplied by the user + +- One four-layer interface PCB with two intended inner GND planes. +- Regulated 12 V desktop inlet rather than the earlier 5 V proposal. +- 10-pin module-side rack header and positive-rail diode OR, not a 16-pin module header or ideal-diode mux. +- Vertical mono patch jacks replacing the proposed right-angle TRS parts; separate L/R outputs retained. +- Longer encoder shaft, shared panel PCB plane at −8 mm and associated mounting spacers. +- Optional bipolar MOD circuitry and default bypass jumper; PITCH and line-level audio unchanged. +- Short DIN and desktop inlet harnesses; no extra custom carrier PCB. +- Proposed part substitutions/envelopes, unrated generic harnesses and unspecified fuse/passive entries are **release gates**, not verified purchasing selections. + +## Model and analysis limitations + +STEP component bodies were constructed from dimensions and simple pin shapes. They are reference geometry, not downloaded certified manufacturer models. Inner-plane connectivity, EMI, converter stability and toleranced mechanical fit remain unverified. The numerical DC report evaluates ideal resistor equations and a sampled tolerance distribution; it does not simulate the complete circuit. diff --git a/hardware/panel/fab/BOM.csv b/hardware/panel/fab/BOM.csv new file mode 100644 index 0000000..0f5955d --- /dev/null +++ b/hardware/panel/fab/BOM.csv @@ -0,0 +1,60 @@ +Reference,Value,Manufacturer,MPN_or_selection_gate,Footprint,Side,X_panel_mm,Y_panel_mm,DNP,Notes +J100,IPS1-110-01-L-D,Samtec,IPS1-110-01-L-D,RadianPanel:Stack_2x10_P2.54,B,124.0,61.75,False,Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. +J101,IPS1-110-01-L-D,Samtec,IPS1-110-01-L-D,RadianPanel:Stack_2x10_P2.54,B,43.0,72.25,False,Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. +RV1,10k linear / TENSION,Bourns,PTV09A-4020F-B103,RadianPanel:Bourns_PTV09A4_RearFacing,F,38.0,96.0,False,"Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC." +RV2,10k linear / DECAY,Bourns,PTV09A-4020F-B103,RadianPanel:Bourns_PTV09A4_RearFacing,F,76.0,96.0,False,"Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC." +RV3,10k linear / CHAOS,Bourns,PTV09A-4020F-B103,RadianPanel:Bourns_PTV09A4_RearFacing,F,114.0,96.0,False,"Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC." +RV4,10k linear / DRIVE,Bourns,PTV09A-4020F-B103,RadianPanel:Bourns_PTV09A4_RearFacing,F,66.0,70.0,False,"Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC." +RV5,10k linear / DELAY,Bourns,PTV09A-4020F-B103,RadianPanel:Bourns_PTV09A4_RearFacing,F,88.0,70.0,False,"Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC." +RV6,10k linear / REVERB,Bourns,PTV09A-4020F-B103,RadianPanel:Bourns_PTV09A4_RearFacing,F,110.0,70.0,False,"Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC." +ENC1,24 PPR / PUSH,Bourns,PEC11R-4220F-S0024,RadianPanel:Bourns_PEC11R4_RearFacing_Switch,F,42.0,43.0,False,20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. +SW1,MODE / SPDT ON-ON,E-Switch,100SP1T1B1M2REH,RadianPanel:E_Switch_100SP_M2,F,150.5,84.5,False,"Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required." +D10,VOICE 1,Kingbright,L-934GD,RadianPanel:LED_D3.0_P2.54,F,124.0,108.0,False,"3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." +D11,VOICE 2,Kingbright,L-934GD,RadianPanel:LED_D3.0_P2.54,F,134.0,108.0,False,"3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." +D12,VOICE 3,Kingbright,L-934GD,RadianPanel:LED_D3.0_P2.54,F,144.0,108.0,False,"3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." +D13,VOICE 4,Kingbright,L-934GD,RadianPanel:LED_D3.0_P2.54,F,154.0,108.0,False,"3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." +J301,PITCH 0-5V,QingPu / Thonk,WQP518MA (Thonkiconn/PJ398SM),RadianPanel:WQP518MA_PJ398SM_Vertical,F,186.5,99.0,False,"Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check." +J302,MOD,QingPu / Thonk,WQP518MA (Thonkiconn/PJ398SM),RadianPanel:WQP518MA_PJ398SM_Vertical,F,186.5,81.0,False,"Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check." +J303,GATE,QingPu / Thonk,WQP518MA (Thonkiconn/PJ398SM),RadianPanel:WQP518MA_PJ398SM_Vertical,F,186.5,63.0,False,"Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check." +J304,LINE L,QingPu / Thonk,WQP518MA (Thonkiconn/PJ398SM),RadianPanel:WQP518MA_PJ398SM_Vertical,F,186.5,45.0,False,"Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check." +J305,LINE R,QingPu / Thonk,WQP518MA (Thonkiconn/PJ398SM),RadianPanel:WQP518MA_PJ398SM_Vertical,F,186.5,27.0,False,"Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check." +J306,22-27-2021,Molex,22-27-2021,RadianPanel:Molex_22-27-2021_J306_B,B,57.5,39.0,False,Exact KK-254 2-circuit friction-lock header to retained Same Sky SDS-50J MIDI DIN pins 4 and 5. No DIN 2/shield-to-GND connection. +J200,61201021621,Wurth Elektronik,61201021621,RadianPanel:Wurth_61201021621_Exact_B,B,174.0,64.0,False,"Exact keyed WR-BHD 2x5 2.54 mm header. Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections." +J201,22-27-2021,Molex,22-27-2021,RadianPanel:Molex_22-27-2021_J201_B,B,26.0,52.0,False,Exact KK-254 2-circuit friction-lock header from the chassis-mounted 12 V DC inlet. NOT a 5 V inlet. +F1,2A FUSE / >=32V,,SELECT 2 A >=32 V 1206 fuse,RadianPanel:Fuse_1206,F,53.0,65.0,False,"Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate." +F2,2A FUSE / >=32V,,SELECT 2 A >=32 V 1206 fuse,RadianPanel:Fuse_1206,F,26.0,59.0,False,"Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate." +D1,SS54 / OR,Vishay,SS54-E3/57T,RadianPanel:D_SMB,F,44.0,65.0,False,"Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature." +D2,SS54 / OR,Vishay,SS54-E3/57T,RadianPanel:D_SMB,F,35.0,59.0,False,"Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature." +D3,SMBJ15A,Vishay,SMBJ15A-E3/52,RadianPanel:D_SMB,F,25.0,46.0,False,Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. +U1,TPS54302DDCR,Texas Instruments,TPS54302DDCR,RadianPanel:TI_DDC0006A_SOT23_6,F,34.0,25.0,False,"3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit." +L1,10uH 4A / Isat7.5A,Bourns,SRP7050TA-100M,RadianPanel:Bourns_SRP7050TA,F,26.0,25.0,False,4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. +C1,10uF,,SELECT 10uF 50V X7R 1210,RadianPanel:C_1210,F,31.0,18.0,False,50V X7R; verify effective capacitance at DC bias +C2,100nF,,SELECT 100nF 50V X7R 0603,RadianPanel:C_0603,F,32.0,21.5,False,50V X7R; verify effective capacitance at DC bias +C3,100nF,,SELECT 100nF 16V X7R 0603,RadianPanel:C_0603,F,34.0,29.0,False,16V X7R; verify effective capacitance at DC bias +C4,22uF,,SELECT 22uF 25V X7R 1210,RadianPanel:C_1210,F,23.0,33.0,False,25V X7R; verify effective capacitance at DC bias +C5,22uF,,SELECT 22uF 25V X7R 1210,RadianPanel:C_1210,F,29.0,33.0,False,25V X7R; verify effective capacitance at DC bias +R1,100k,,SELECT 100k 1% 0603,RadianPanel:R_0603,F,39.5,27.0,False,Resistor 1% +R2,13.3k,,SELECT 13.3k 1% 0603,RadianPanel:R_0603,F,39.0,20.0,False,Resistor 1% +R3,511k,,SELECT 511k 1% 0603,RadianPanel:R_0603,F,46.0,23.0,False,Resistor 1% +R4,105k,,SELECT 105k 1% 0603,RadianPanel:R_0603,F,43.0,19.0,False,Resistor 1% +R5,49.9,,SELECT 49.9 1% 0603,RadianPanel:R_0603,F,39.0,32.0,False,Resistor 1% +C6,75pF,,SELECT 75pF 50V C0G 0603,RadianPanel:C_0603,F,43.0,27.0,False,50V C0G; verify effective capacitance at DC bias +C7,10uF,,SELECT 10uF 50V X7R 1210,RadianPanel:C_1210,F,43.0,59.0,False,50V X7R; verify effective capacitance at DC bias +JP1,450301014042,Wurth Elektronik,450301014042,RadianPanel:Wurth_450301014042_Exact_B,B,165.5,88.0,False,Actual SPDT configuration switch replaces the removable shunt. One throw selects direct unipolar MOD_RAW; the other selects MOD_BIPOLAR. NOT the front MODE switch. +U2,OPA2192ID,Texas Instruments,OPA2192ID,RadianPanel:SOIC8_3.9x4.9_P1.27,F,151.0,67.0,False,"A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping." +R20,200k,,SELECT 200k 0.1% 0603,RadianPanel:R_0603,F,164.0,75.0,False,Resistor 0.1% +R21,100k,,SELECT 100k 0.1% 0603,RadianPanel:R_0603,F,158.0,75.0,False,Resistor 0.1% +R22,200k,,SELECT 200k 0.1% 0603,RadianPanel:R_0603,F,164.0,71.0,False,Resistor 0.1% +R23,10k,,SELECT 10k 0.1% 0603,RadianPanel:R_0603,F,159.5,57.0,False,Resistor 0.1% +R24,10k,,SELECT 10k 0.1% 0603,RadianPanel:R_0603,F,163.0,59.0,False,Resistor 0.1% +D4,BAT54S,Nexperia,"BAT54S,215",RadianPanel:SOT23_BAT54S,F,166.0,65.0,False,"Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior." +C20,100nF,,SELECT 100nF 16V X7R 0603,RadianPanel:C_0603,F,157.0,69.0,False,16V X7R; verify effective capacitance at DC bias +C21,1uF,,SELECT 1uF 16V X7R 0805,RadianPanel:C_0805,F,149.0,74.0,False,16V X7R; verify effective capacitance at DC bias +J202,22-27-2061,Molex,22-27-2061,RadianPanel:Molex_22-27-2061_J202_B,B,131.0,29.0,False,Exact KK-254 6-circuit friction-lock service header; pin-for-pin to the JTAG nets already carried through J101/J18. No level conversion; validate JTAG frequency. +SW3,PROGRAM / SERVICE,Omron,B3F-1000,RadianPanel:SW_PUSH_6x6_P6.5x4.5,B,118.4,25.0,False,"Internal service push button, accessible after module removal." +SW4,RESET / SERVICE,Omron,B3F-1000,RadianPanel:SW_PUSH_6x6_P6.5x4.5,B,146.0,26.0,False, +TP1,GND,,PCB test pad,RadianPanel:TestPoint_D2,B,25.0,42.0,False,"Exposed soldermask aperture, no component." +TP2,VIN5,,PCB test pad,RadianPanel:TestPoint_D2,B,29.0,42.0,False,"Exposed soldermask aperture, no component." +TP3,VRAW,,PCB test pad,RadianPanel:TestPoint_D2,B,48.0,59.0,False,"Exposed soldermask aperture, no component." +TP4,VREF25,,PCB test pad,RadianPanel:TestPoint_D2,B,149.0,62.0,False,"Exposed soldermask aperture, no component." +TP5,MOD_BIPOLAR,,PCB test pad,RadianPanel:TestPoint_D2,B,165.0,61.0,False,"Exposed soldermask aperture, no component." diff --git a/hardware/panel/fab/ENGINEERING_EXPORT_ONLY.txt b/hardware/panel/fab/ENGINEERING_EXPORT_ONLY.txt new file mode 100644 index 0000000..eab5d50 --- /dev/null +++ b/hardware/panel/fab/ENGINEERING_EXPORT_ONLY.txt @@ -0,0 +1,2 @@ +Synchronized from the native-checked repaired board. NOT a fabrication release, component certification or electrical/thermal test. +Source SHA-256: 5c37aa04e39cf2ce4aefce5373201c6c3f49c9220217e3084b0abb485bc1dad0 diff --git a/hardware/panel/fab/MANIFEST.json b/hardware/panel/fab/MANIFEST.json new file mode 100644 index 0000000..2d937e2 --- /dev/null +++ b/hardware/panel/fab/MANIFEST.json @@ -0,0 +1,28 @@ +{ + "source_board": "panel/design/radian_panel.kicad_pcb", + "source_sha256": "9ddd199c1c5e68db47bafff481415ce4db48de8bb185d7cad0d8c10a837b4292", + "review_only": true, + "files": { + "BOM.csv": "88546a7bb758061f861d802ea07d375900db7bbe989a469597b2af0365f2cb6b", + "ENGINEERING_EXPORT_ONLY.txt": "97adb51a0bdc14d21b92e00cf6947dd97f7bc1b8e5f09127c9ec5bb6ca0e7f91", + "REVIEW_ONLY.txt": "c18ed7dc993c2d3e53cea37a67fca2d8dc0d2e7a6f983d3b122dc1b0fdd8f3ca", + "radian_panel-B_Cu.gbl": "301a359634c024b1c5498f067dd537ec496a9a4459bd91363a2ca459b0e71672", + "radian_panel-B_Mask.gbs": "e24bafb2996e5b12dcb09d8e69361d1d9df9d1e60cab129db00931e69a472d42", + "radian_panel-B_Paste.gbp": "7517c1c8c140626b2974aa357e89d197084a5fb5e6a5d3d46ae260ce505ef788", + "radian_panel-B_Silkscreen.gbo": "e67c8d746b1e721100a97af52e50554c229308f68a8106b9dd25af09be220cb9", + "radian_panel-Edge_Cuts.gm1": "f0b6f6ca06ae5b3e4b47e2e3990f3173128328274785c59ca402c75b6d64d76f", + "radian_panel-F_Cu.gtl": "f41082a4e88df99de94f3c4dac2c5466511446425ed045cfafb5f645f17082a6", + "radian_panel-F_Mask.gts": "58ac7dd904d4f0df96afa4bc44630a45c6d8e14b0f677cc301af1bc0c800d9c1", + "radian_panel-F_Paste.gtp": "170b2c4305fbdd5f719d07b137b00d7606c6744d74977720ab8ce3e33ccd5bf1", + "radian_panel-F_Silkscreen.gto": "eee898fb6c61205a5d1a38b0e07e25075a8d6fc07ed3fd7bd84ff78c42e77eb9", + "radian_panel-In1_Cu.g1": "78142977a394434477aa40f30da268993cdaa27da3e522d0ae322ba0f6c9e333", + "radian_panel-In2_Cu.g2": "85f49333fab3b9c15d9282c69f807a1bfa78356d9b1bd126bf77be1d1b07b83a", + "radian_panel-NPTH-drl_map.pdf": "888075948592fe1871d156d739131470a893177541d5c4473a82c51732396c49", + "radian_panel-NPTH.drl": "0ad59fc539e305321cc7b8249361470ddb40824eab37ba576bf3151896c001c2", + "radian_panel-PTH-drl_map.pdf": "872c95cfa75ddb771a9b0fbe10553480a8e2a1311548bb240d6bdf494c5d5eb2", + "radian_panel-PTH.drl": "3e3f0414b971172ce6a7dba7f0db50eeadbfc755cf752d4d7d6041e528c76c8f", + "radian_panel-job.gbrjob": "c13c80333fdcd30c23233bc1fc2112fe644770de0929f2dbd31d238112c84d7c", + "radian_panel-pos.csv": "84b6ef6e1b81cf34f262c8a94688d8b6fb67e7cf80156e9bf489683b29a888dd", + "source_sha256.txt": "6f1074d98db6447d308e9b43de72b7a2f15d2b4985bbd0c23f348698b9942913" + } +} \ No newline at end of file diff --git a/hardware/panel/fab/REVIEW_ONLY.txt b/hardware/panel/fab/REVIEW_ONLY.txt new file mode 100644 index 0000000..dcaa890 --- /dev/null +++ b/hardware/panel/fab/REVIEW_ONLY.txt @@ -0,0 +1,2 @@ +Regenerated from the repaired native PCB. NOT a production release. +ERC/DRC do not establish component correctness, power/thermal/fault behaviour, FPGA operation or physical fit. diff --git a/hardware/panel/fab/radian_panel-B_Cu.gbl b/hardware/panel/fab/radian_panel-B_Cu.gbl new file mode 100644 index 0000000..8b5c0a1 --- /dev/null +++ b/hardware/panel/fab/radian_panel-B_Cu.gbl @@ -0,0 +1,1472 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,10.0.6-1.fc44*% +%TF.CreationDate,2026-09-18T16:13:14+02:00*% +%TF.ProjectId,radian_panel,72616469-616e-45f7-9061-6e656c2e6b69,P1 DRAFT*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Copper,L4,Bot*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 10.0.6-1.fc44) date 2026-09-18 16:13:14* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +G04 Aperture macros list end* +%TA.AperFunction,ComponentPad*% +%ADD10C,1.600000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD11C,1.800000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD12O,2.800000X3.200000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD13O,2.300000X2.600000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD14C,2.800000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD15O,2.800000X3.600000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD16R,1.650000X1.650000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD17C,1.650000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD18RoundRect,0.400000X0.600000X0.600000X-0.600000X0.600000X-0.600000X-0.600000X0.600000X-0.600000X0*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD19R,1.600000X1.600000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD20C,1.300000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD21R,1.300000X1.300000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD22R,1.800000X1.800000*% +%TD*% +%TA.AperFunction,ViaPad*% +%ADD23C,0.700000*% +%TD*% +%TA.AperFunction,ViaPad*% +%ADD24C,0.800000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD25C,0.250000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD26C,0.350000*% +%TD*% +G04 APERTURE END LIST* +D10* +%TO.P,D13,1*% +%TO.N,GND*% +X152730000Y-20500000D03* +%TO.P,D13,2*% +%TO.N,LED3_A*% +X155270000Y-20500000D03* +%TD*% +D11* +%TO.P,RV3,1*% +%TO.N,GND*% +X111500000Y-39500000D03* +%TO.P,RV3,2*% +%TO.N,POT_TIMBRE_RAW*% +X114000000Y-39500000D03* +%TO.P,RV3,3*% +%TO.N,VREF25*% +X116500000Y-39500000D03* +D12* +%TO.P,RV3,MP1*% +%TO.N,unconnected-(RV3-PadMP1)*% +X108700000Y-32500000D03* +%TO.P,RV3,MP2*% +%TO.N,unconnected-(RV3-PadMP2)*% +X119300000Y-32500000D03* +%TD*% +D13* +%TO.P,J305,1*% +%TO.N,GND*% +X186500000Y-107980000D03* +%TO.P,J305,2*% +%TO.N,unconnected-(J305-NORMAL-Pad2)*% +X186500000Y-104880000D03* +%TO.P,J305,3*% +%TO.N,LINE_R*% +X186500000Y-96580000D03* +%TD*% +%TO.P,J303,1*% +%TO.N,GND*% +X186500000Y-71980000D03* +%TO.P,J303,2*% +X186500000Y-68880000D03* +%TO.P,J303,3*% +%TO.N,GATE_IN*% +X186500000Y-60580000D03* +%TD*% +%TO.P,J304,1*% +%TO.N,GND*% +X186500000Y-89980000D03* +%TO.P,J304,2*% +%TO.N,unconnected-(J304-NORMAL-Pad2)*% +X186500000Y-86880000D03* +%TO.P,J304,3*% +%TO.N,LINE_L*% +X186500000Y-78580000D03* +%TD*% +%TO.P,J302,1*% +%TO.N,GND*% +X186500000Y-53980000D03* +%TO.P,J302,2*% +X186500000Y-50880000D03* +%TO.P,J302,3*% +%TO.N,MOD_RAW*% +X186500000Y-42580000D03* +%TD*% +D11* +%TO.P,RV4,1*% +%TO.N,GND*% +X63500000Y-65500000D03* +%TO.P,RV4,2*% +%TO.N,POT_DRIVE_RAW*% +X66000000Y-65500000D03* +%TO.P,RV4,3*% +%TO.N,VREF25*% +X68500000Y-65500000D03* +D12* +%TO.P,RV4,MP1*% +%TO.N,unconnected-(RV4-PadMP1)*% +X60700000Y-58500000D03* +%TO.P,RV4,MP2*% +%TO.N,unconnected-(RV4-PadMP2)*% +X71300000Y-58500000D03* +%TD*% +D11* +%TO.P,RV5,1*% +%TO.N,GND*% +X85500000Y-65500000D03* +%TO.P,RV5,2*% +%TO.N,POT_DELAY_RAW*% +X88000000Y-65500000D03* +%TO.P,RV5,3*% +%TO.N,VREF25*% +X90500000Y-65500000D03* +D12* +%TO.P,RV5,MP1*% +%TO.N,unconnected-(RV5-PadMP1)*% +X82700000Y-58500000D03* +%TO.P,RV5,MP2*% +%TO.N,unconnected-(RV5-PadMP2)*% +X93300000Y-58500000D03* +%TD*% +D10* +%TO.P,D11,1*% +%TO.N,GND*% +X132730000Y-20500000D03* +%TO.P,D11,2*% +%TO.N,LED1_A*% +X135270000Y-20500000D03* +%TD*% +D11* +%TO.P,RV1,1*% +%TO.N,GND*% +X35500000Y-39500000D03* +%TO.P,RV1,2*% +%TO.N,POT_PITCH_RAW*% +X38000000Y-39500000D03* +%TO.P,RV1,3*% +%TO.N,VREF25*% +X40500000Y-39500000D03* +D12* +%TO.P,RV1,MP1*% +%TO.N,unconnected-(RV1-PadMP1)*% +X32700000Y-32500000D03* +%TO.P,RV1,MP2*% +%TO.N,unconnected-(RV1-PadMP2)*% +X43300000Y-32500000D03* +%TD*% +D14* +%TO.P,SW1,1*% +%TO.N,GND*% +X150500000Y-48700000D03* +%TO.P,SW1,2*% +%TO.N,cv_select*% +X150500000Y-44000000D03* +%TO.P,SW1,3*% +%TO.N,V3V3*% +X150500000Y-39300000D03* +%TD*% +D10* +%TO.P,D12,1*% +%TO.N,GND*% +X142730000Y-20500000D03* +%TO.P,D12,2*% +%TO.N,LED2_A*% +X145270000Y-20500000D03* +%TD*% +D11* +%TO.P,ENC1,A*% +%TO.N,ENC_A_RAW*% +X39500000Y-93000000D03* +%TO.P,ENC1,B*% +%TO.N,ENC_B_RAW*% +X44500000Y-93000000D03* +%TO.P,ENC1,C*% +%TO.N,GND*% +X42000000Y-93000000D03* +D15* +%TO.P,ENC1,MP1*% +%TO.N,unconnected-(ENC1-PadMP1)*% +X35400000Y-85500000D03* +%TO.P,ENC1,MP2*% +%TO.N,unconnected-(ENC1-PadMP2)*% +X48600000Y-85500000D03* +D11* +%TO.P,ENC1,S1*% +%TO.N,ENC_SW_RAW*% +X39500000Y-78500000D03* +%TO.P,ENC1,S2*% +%TO.N,GND*% +X44500000Y-78500000D03* +%TD*% +%TO.P,RV6,1*% +%TO.N,GND*% +X107500000Y-65500000D03* +%TO.P,RV6,2*% +%TO.N,POT_REVERB_RAW*% +X110000000Y-65500000D03* +%TO.P,RV6,3*% +%TO.N,VREF25*% +X112500000Y-65500000D03* +D12* +%TO.P,RV6,MP1*% +%TO.N,unconnected-(RV6-PadMP1)*% +X104700000Y-58500000D03* +%TO.P,RV6,MP2*% +%TO.N,unconnected-(RV6-PadMP2)*% +X115300000Y-58500000D03* +%TD*% +D11* +%TO.P,RV2,1*% +%TO.N,GND*% +X73500000Y-39500000D03* +%TO.P,RV2,2*% +%TO.N,POT_DECAY_RAW*% +X76000000Y-39500000D03* +%TO.P,RV2,3*% +%TO.N,VREF25*% +X78500000Y-39500000D03* +D12* +%TO.P,RV2,MP1*% +%TO.N,unconnected-(RV2-PadMP1)*% +X70700000Y-32500000D03* +%TO.P,RV2,MP2*% +%TO.N,unconnected-(RV2-PadMP2)*% +X81300000Y-32500000D03* +%TD*% +D10* +%TO.P,D10,1*% +%TO.N,GND*% +X122730000Y-20500000D03* +%TO.P,D10,2*% +%TO.N,LED0_A*% +X125270000Y-20500000D03* +%TD*% +D13* +%TO.P,J301,1*% +%TO.N,GND*% +X186500000Y-35980000D03* +%TO.P,J301,2*% +X186500000Y-32880000D03* +%TO.P,J301,3*% +%TO.N,PITCH_IN*% +X186500000Y-24580000D03* +%TD*% +D16* +%TO.P,J200,1*% +%TO.N,unconnected-(J200-Pad1)*% +X175270000Y-59420000D03* +D17* +%TO.P,J200,2*% +%TO.N,unconnected-(J200-Pad2)*% +X172730000Y-59420000D03* +%TO.P,J200,3*% +%TO.N,GND*% +X175270000Y-61960000D03* +%TO.P,J200,4*% +X172730000Y-61960000D03* +%TO.P,J200,5*% +X175270000Y-64500000D03* +%TO.P,J200,6*% +X172730000Y-64500000D03* +%TO.P,J200,7*% +X175270000Y-67040000D03* +%TO.P,J200,8*% +X172730000Y-67040000D03* +%TO.P,J200,9*% +%TO.N,RACK_12V*% +X175270000Y-69580000D03* +%TO.P,J200,10*% +X172730000Y-69580000D03* +%TD*% +D18* +%TO.P,TP2,1*% +%TO.N,VIN5*% +X29000000Y-86500000D03* +%TD*% +%TO.P,TP4,1*% +%TO.N,VREF25*% +X149000000Y-66500000D03* +%TD*% +D19* +%TO.P,J201,1*% +%TO.N,DESKTOP_12V*% +X27270000Y-76500000D03* +D10* +%TO.P,J201,2*% +%TO.N,GND*% +X24730000Y-76500000D03* +%TD*% +D19* +%TO.P,J306,1*% +%TO.N,MIDI4*% +X58770000Y-89500000D03* +D10* +%TO.P,J306,2*% +%TO.N,MIDI5*% +X56230000Y-89500000D03* +%TD*% +D20* +%TO.P,JP1,1*% +%TO.N,MOD_IN*% +X165500000Y-40500000D03* +%TO.P,JP1,2*% +%TO.N,MOD_BIPOLAR*% +X162960000Y-40500000D03* +D21* +%TO.P,JP1,3*% +%TO.N,MOD_RAW*% +X168040000Y-40500000D03* +%TD*% +D22* +%TO.P,J101,1*% +%TO.N,GND*% +X31570000Y-57520000D03* +D11* +%TO.P,J101,2*% +%TO.N,V3V3*% +X31570000Y-54980000D03* +%TO.P,J101,3*% +%TO.N,GND*% +X34110000Y-57520000D03* +%TO.P,J101,4*% +%TO.N,ENC_A_RAW*% +X34110000Y-54980000D03* +%TO.P,J101,5*% +%TO.N,ENC_B_RAW*% +X36650000Y-57520000D03* +%TO.P,J101,6*% +%TO.N,ENC_SW_RAW*% +X36650000Y-54980000D03* +%TO.P,J101,7*% +%TO.N,cv_select*% +X39190000Y-57520000D03* +%TO.P,J101,8*% +%TO.N,LED0_A*% +X39190000Y-54980000D03* +%TO.P,J101,9*% +%TO.N,LED1_A*% +X41730000Y-57520000D03* +%TO.P,J101,10*% +%TO.N,LED2_A*% +X41730000Y-54980000D03* +%TO.P,J101,11*% +%TO.N,LED3_A*% +X44270000Y-57520000D03* +%TO.P,J101,12*% +%TO.N,GND*% +X44270000Y-54980000D03* +%TO.P,J101,13*% +%TO.N,MIDI4*% +X46810000Y-57520000D03* +%TO.P,J101,14*% +%TO.N,MIDI5*% +X46810000Y-54980000D03* +%TO.P,J101,15*% +%TO.N,PROGRAM_B*% +X49350000Y-57520000D03* +%TO.P,J101,16*% +%TO.N,reset_n*% +X49350000Y-54980000D03* +%TO.P,J101,17*% +%TO.N,JTAG_TCK*% +X51890000Y-57520000D03* +%TO.P,J101,18*% +%TO.N,JTAG_TDO*% +X51890000Y-54980000D03* +%TO.P,J101,19*% +%TO.N,JTAG_TDI*% +X54430000Y-57520000D03* +%TO.P,J101,20*% +%TO.N,JTAG_TMS*% +X54430000Y-54980000D03* +%TD*% +D18* +%TO.P,TP3,1*% +%TO.N,VRAW*% +X48000000Y-69500000D03* +%TD*% +D11* +%TO.P,SW4,1*% +%TO.N,reset_n*% +X149250000Y-104750000D03* +X149250000Y-100250000D03* +%TO.P,SW4,2*% +%TO.N,GND*% +X142750000Y-104750000D03* +X142750000Y-100250000D03* +%TD*% +D18* +%TO.P,TP1,1*% +%TO.N,GND*% +X25000000Y-86500000D03* +%TD*% +D19* +%TO.P,J202,1*% +%TO.N,V3V3*% +X137350000Y-99500000D03* +D10* +%TO.P,J202,2*% +%TO.N,GND*% +X134810000Y-99500000D03* +%TO.P,J202,3*% +%TO.N,JTAG_TCK*% +X132270000Y-99500000D03* +%TO.P,J202,4*% +%TO.N,JTAG_TDO*% +X129730000Y-99500000D03* +%TO.P,J202,5*% +%TO.N,JTAG_TDI*% +X127190000Y-99500000D03* +%TO.P,J202,6*% +%TO.N,JTAG_TMS*% +X124650000Y-99500000D03* +%TD*% +D22* +%TO.P,J100,1*% +%TO.N,GND*% +X122730000Y-55320000D03* +D11* +%TO.P,J100,2*% +%TO.N,VIN5*% +X125270000Y-55320000D03* +%TO.P,J100,3*% +X122730000Y-57860000D03* +%TO.P,J100,4*% +%TO.N,VREF25*% +X125270000Y-57860000D03* +%TO.P,J100,5*% +%TO.N,GND*% +X122730000Y-60400000D03* +%TO.P,J100,6*% +%TO.N,POT_PITCH_RAW*% +X125270000Y-60400000D03* +%TO.P,J100,7*% +%TO.N,POT_DECAY_RAW*% +X122730000Y-62940000D03* +%TO.P,J100,8*% +%TO.N,POT_TIMBRE_RAW*% +X125270000Y-62940000D03* +%TO.P,J100,9*% +%TO.N,POT_DRIVE_RAW*% +X122730000Y-65480000D03* +%TO.P,J100,10*% +%TO.N,POT_DELAY_RAW*% +X125270000Y-65480000D03* +%TO.P,J100,11*% +%TO.N,POT_REVERB_RAW*% +X122730000Y-68020000D03* +%TO.P,J100,12*% +%TO.N,GND*% +X125270000Y-68020000D03* +%TO.P,J100,13*% +%TO.N,PITCH_IN*% +X122730000Y-70560000D03* +%TO.P,J100,14*% +%TO.N,MOD_IN*% +X125270000Y-70560000D03* +%TO.P,J100,15*% +%TO.N,GATE_IN*% +X122730000Y-73100000D03* +%TO.P,J100,16*% +%TO.N,GND*% +X125270000Y-73100000D03* +%TO.P,J100,17*% +%TO.N,LINE_L*% +X122730000Y-75640000D03* +%TO.P,J100,18*% +%TO.N,GND*% +X125270000Y-75640000D03* +%TO.P,J100,19*% +%TO.N,LINE_R*% +X122730000Y-78180000D03* +%TO.P,J100,20*% +%TO.N,GND*% +X125270000Y-78180000D03* +%TD*% +D18* +%TO.P,TP5,1*% +%TO.N,MOD_BIPOLAR*% +X165000000Y-67500000D03* +%TD*% +D11* +%TO.P,SW3,1*% +%TO.N,PROGRAM_B*% +X121650000Y-105750000D03* +X121650000Y-101250000D03* +%TO.P,SW3,2*% +%TO.N,GND*% +X115150000Y-105750000D03* +X115150000Y-101250000D03* +%TD*% +D23* +%TO.N,VREF_BUF*% +X156000000Y-53000000D03* +X149750000Y-58250000D03* +%TO.N,MOD_SUM*% +X156500000Y-61000000D03* +X164000000Y-58500000D03* +X159500000Y-54750000D03* +X165750000Y-63500000D03* +D24* +%TO.N,GND*% +X33000000Y-107750000D03* +D23* +X151000000Y-54500000D03* +X158750000Y-59500000D03* +D24* +X23000000Y-95250000D03* +X33000000Y-101750000D03* +D23* +X148250000Y-64250000D03* +D24* +X26000000Y-82500000D03* +X29000000Y-95250000D03* +X34000000Y-110500000D03* +X29000000Y-92500000D03* +X29500000Y-82500000D03* +D23* +X40750000Y-108500000D03* +X165000000Y-61750000D03* +D24* +X43250000Y-69500000D03* +X31250000Y-110500000D03* +X23000000Y-92500000D03* +D23* +X165750000Y-57500000D03* +D24* +X31000000Y-107750000D03* +D23* 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APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +G04 Aperture macros list end* +%ADD10C,1.700000*% +%ADD11C,2.800000*% +%ADD12C,1.900000*% +%ADD13O,2.900000X3.300000*% +%ADD14C,3.100000*% +%ADD15O,2.400000X2.700000*% +%ADD16C,2.900000*% +%ADD17O,2.900000X3.700000*% +%ADD18RoundRect,0.050000X0.825000X0.825000X-0.825000X0.825000X-0.825000X-0.825000X0.825000X-0.825000X0*% +%ADD19C,1.750000*% +%ADD20RoundRect,0.450000X0.600000X0.600000X-0.600000X0.600000X-0.600000X-0.600000X0.600000X-0.600000X0*% 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+%TF.ProjectId,radian_panel,72616469-616e-45f7-9061-6e656c2e6b69,P1 DRAFT*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Paste,Bot*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 10.0.6-1.fc44) date 2026-09-18 16:13:14* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +G04 Aperture macros list end* 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macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +G04 Aperture macros list end* +%TA.AperFunction,SMDPad,CuDef*% +%ADD10RoundRect,0.170000X-0.255000X-0.305000X0.255000X-0.305000X0.255000X0.305000X-0.255000X0.305000X0*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD11RoundRect,0.120000X-0.380000X-0.180000X0.380000X-0.180000X0.380000X0.180000X-0.380000X0.180000X0*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD12C,1.600000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD13C,1.800000*% +%TD*% +%TA.AperFunction,ComponentPad*% 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diff --git a/hardware/panel/fab/radian_panel-F_Mask.gts b/hardware/panel/fab/radian_panel-F_Mask.gts new file mode 100644 index 0000000..06b9908 --- /dev/null +++ b/hardware/panel/fab/radian_panel-F_Mask.gts @@ -0,0 +1,482 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,10.0.6-1.fc44*% +%TF.CreationDate,2026-09-18T16:13:14+02:00*% +%TF.ProjectId,radian_panel,72616469-616e-45f7-9061-6e656c2e6b69,P1 DRAFT*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Soldermask,Top*% +%TF.FilePolarity,Negative*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 10.0.6-1.fc44) date 2026-09-18 16:13:14* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* 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+X115150000Y-105750000D03* +X115150000Y-101250000D03* +%TD*% +%LPD*% +M02* diff --git a/hardware/panel/fab/radian_panel-In1_Cu.g1 b/hardware/panel/fab/radian_panel-In1_Cu.g1 new file mode 100644 index 0000000..d359e2c --- /dev/null +++ b/hardware/panel/fab/radian_panel-In1_Cu.g1 @@ -0,0 +1,8401 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,10.0.6-1.fc44*% +%TF.CreationDate,2026-09-18T16:13:14+02:00*% +%TF.ProjectId,radian_panel,72616469-616e-45f7-9061-6e656c2e6b69,P1 DRAFT*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Copper,L2,Inr*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 10.0.6-1.fc44) date 2026-09-18 16:13:14* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +%TA.AperFunction,ComponentPad*% +%ADD10C,1.600000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD11C,1.800000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD12O,2.800000X3.200000*% +%TD*% +%TA.AperFunction,ComponentPad*% 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DRAFT*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Copper,L3,Inr*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 10.0.6-1.fc44) date 2026-09-18 16:13:14* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +%TA.AperFunction,ComponentPad*% +%ADD10C,1.600000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD11C,1.800000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD12O,2.800000X3.200000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD13O,2.300000X2.600000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD14C,2.800000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD15O,2.800000X3.600000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD16R,1.650000X1.650000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD17C,1.650000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD18R,1.600000X1.600000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD19C,1.300000*% +%TD*% +%TA.AperFunction,ComponentPad*% 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"FilePolarity": "Positive" + }, + { + "Path": "radian_panel-F_Paste.gtp", + "FileFunction": "SolderPaste,Top", + "FilePolarity": "Positive" + }, + { + "Path": "radian_panel-B_Paste.gbp", + "FileFunction": "SolderPaste,Bot", + "FilePolarity": "Positive" + }, + { + "Path": "radian_panel-F_Silkscreen.gto", + "FileFunction": "Legend,Top", + "FilePolarity": "Positive" + }, + { + "Path": "radian_panel-B_Silkscreen.gbo", + "FileFunction": "Legend,Bot", + "FilePolarity": "Positive" + }, + { + "Path": "radian_panel-F_Mask.gts", + "FileFunction": "SolderMask,Top", + "FilePolarity": "Negative" + }, + { + "Path": "radian_panel-B_Mask.gbs", + "FileFunction": "SolderMask,Bot", + "FilePolarity": "Negative" + }, + { + "Path": "radian_panel-Edge_Cuts.gm1", + "FileFunction": "Profile", + "FilePolarity": "Positive" + } + ], + "MaterialStackup": [ + { + "Type": "Legend", + "Name": "Top Silk Screen" + }, + { + "Type": "SolderPaste", + "Name": "Top Solder Paste" + }, + { + "Type": "SolderMask", + "Thickness": 0.01, + "Name": "Top Solder Mask" + }, + { + "Type": "Copper", + "Thickness": 0.035, + "Name": "F.Cu" + }, + { + "Type": "Dielectric", + "Thickness": 0.48, + "Material": "FR4", + "Name": "F.Cu/In1.Cu", + "Notes": "Type: dielectric layer 1 (from F.Cu to In1.Cu)" + }, + { + "Type": "Copper", + "Thickness": 0.035, + "Name": "In1.Cu" + }, + { + "Type": "Dielectric", + "Thickness": 0.48, + "Material": "FR4", + "Name": "In1.Cu/In2.Cu", + "Notes": "Type: dielectric layer 2 (from In1.Cu to In2.Cu)" + }, + { + "Type": "Copper", + "Thickness": 0.035, + "Name": "In2.Cu" + }, + { + "Type": "Dielectric", + "Thickness": 0.48, + "Material": "FR4", + "Name": "In2.Cu/B.Cu", + "Notes": "Type: dielectric layer 3 (from In2.Cu to B.Cu)" + }, + { + "Type": "Copper", + "Thickness": 0.035, + "Name": "B.Cu" + }, + { + "Type": "SolderMask", + "Thickness": 0.01, + "Name": "Bottom Solder Mask" + }, + { + "Type": "SolderPaste", + "Name": "Bottom Solder Paste" + }, + { + "Type": "Legend", + "Name": "Bottom Silk Screen" + } + ] +} diff --git a/hardware/panel/fab/radian_panel-pos.csv b/hardware/panel/fab/radian_panel-pos.csv new file mode 100644 index 0000000..c7bf86d --- /dev/null +++ b/hardware/panel/fab/radian_panel-pos.csv @@ -0,0 +1,60 @@ +Ref,Val,Package,PosX,PosY,Rot,Side +"J100","IPS1-110-01-L-D","Stack_2x10_P2.54",124.000000,-66.750000,180.000000,bottom +"J101","IPS1-110-01-L-D","Stack_2x10_P2.54",43.000000,-56.250000,-90.000000,bottom +"J200","61201021621","Wurth_61201021621_Exact_B",174.000000,-64.500000,180.000000,bottom +"J201","22-27-2021","Molex_22-27-2021_J201_B",26.000000,-76.500000,180.000000,bottom +"J202","22-27-2061","Molex_22-27-2061_J202_B",131.000000,-99.500000,180.000000,bottom +"J306","22-27-2021","Molex_22-27-2021_J306_B",57.500000,-89.500000,180.000000,bottom +"JP1","450301014042","Wurth_450301014042_Exact_B",165.500000,-40.500000,180.000000,bottom +"SW3","PROGRAM / SERVICE","SW_PUSH_6x6_P6.5x4.5",118.400000,-103.500000,180.000000,bottom +"SW4","RESET / SERVICE","SW_PUSH_6x6_P6.5x4.5",146.000000,-102.500000,180.000000,bottom +"TP1","GND","TestPoint_D2",25.000000,-86.500000,180.000000,bottom +"TP2","VIN5","TestPoint_D2",29.000000,-86.500000,180.000000,bottom +"TP3","VRAW","TestPoint_D2",48.000000,-69.500000,180.000000,bottom +"TP4","VREF25","TestPoint_D2",149.000000,-66.500000,180.000000,bottom +"TP5","MOD_BIPOLAR","TestPoint_D2",165.000000,-67.500000,180.000000,bottom +"C1","10uF","C_1210",31.000000,-110.500000,0.000000,top +"C2","100nF","C_0603",32.000000,-107.000000,-90.000000,top +"C3","100nF","C_0603",34.000000,-99.500000,0.000000,top +"C4","22uF","C_1210",23.000000,-95.500000,90.000000,top +"C5","22uF","C_1210",29.000000,-95.500000,90.000000,top +"C6","75pF","C_0603",43.000000,-101.500000,0.000000,top +"C7","10uF","C_1210",43.000000,-69.500000,0.000000,top +"C20","100nF","C_0603",157.000000,-59.500000,0.000000,top +"C21","1uF","C_0805",149.000000,-54.500000,0.000000,top +"D1","SS54 / OR","D_SMB",44.000000,-63.500000,0.000000,top +"D2","SS54 / OR","D_SMB",35.000000,-69.500000,0.000000,top +"D3","SMBJ15A","D_SMB",25.000000,-82.500000,0.000000,top +"D4","BAT54S","SOT23_BAT54S",166.000000,-63.500000,0.000000,top +"D10","VOICE 1","LED_D3.0_P2.54",124.000000,-20.500000,0.000000,top +"D11","VOICE 2","LED_D3.0_P2.54",134.000000,-20.500000,0.000000,top +"D12","VOICE 3","LED_D3.0_P2.54",144.000000,-20.500000,0.000000,top +"D13","VOICE 4","LED_D3.0_P2.54",154.000000,-20.500000,0.000000,top +"ENC1","24 PPR / PUSH","Bourns_PEC11R4_RearFacing_Switch",42.000000,-85.500000,0.000000,top +"F1","2A FUSE / >=32V","Fuse_1206",53.000000,-63.500000,0.000000,top +"F2","2A FUSE / >=32V","Fuse_1206",26.000000,-69.500000,0.000000,top +"J301","PITCH 0-5V","WQP518MA_PJ398SM_Vertical",186.500000,-29.500000,0.000000,top +"J302","MOD","WQP518MA_PJ398SM_Vertical",186.500000,-47.500000,0.000000,top +"J303","GATE","WQP518MA_PJ398SM_Vertical",186.500000,-65.500000,0.000000,top +"J304","LINE L","WQP518MA_PJ398SM_Vertical",186.500000,-83.500000,0.000000,top +"J305","LINE R","WQP518MA_PJ398SM_Vertical",186.500000,-101.500000,0.000000,top +"L1","10uH 4A / Isat7.5A","Bourns_SRP7050TA",26.000000,-103.500000,0.000000,top +"R1","100k","R_0603",39.500000,-101.500000,0.000000,top +"R2","13.3k","R_0603",39.000000,-108.500000,0.000000,top +"R3","511k","R_0603",46.000000,-105.500000,90.000000,top +"R4","105k","R_0603",43.000000,-109.500000,0.000000,top +"R5","49.9","R_0603",39.000000,-96.500000,0.000000,top +"R20","200k","R_0603",164.000000,-53.500000,0.000000,top +"R21","100k","R_0603",158.000000,-53.500000,0.000000,top +"R22","200k","R_0603",164.000000,-57.500000,0.000000,top +"R23","10k","R_0603",159.500000,-71.500000,0.000000,top +"R24","10k","R_0603",163.000000,-69.500000,0.000000,top +"RV1","10k linear / TENSION","Bourns_PTV09A4_RearFacing",38.000000,-32.500000,0.000000,top +"RV2","10k linear / DECAY","Bourns_PTV09A4_RearFacing",76.000000,-32.500000,0.000000,top +"RV3","10k linear / CHAOS","Bourns_PTV09A4_RearFacing",114.000000,-32.500000,0.000000,top +"RV4","10k linear / DRIVE","Bourns_PTV09A4_RearFacing",66.000000,-58.500000,0.000000,top +"RV5","10k linear / DELAY","Bourns_PTV09A4_RearFacing",88.000000,-58.500000,0.000000,top +"RV6","10k linear / REVERB","Bourns_PTV09A4_RearFacing",110.000000,-58.500000,0.000000,top +"SW1","MODE / SPDT ON-ON","E_Switch_100SP_M2",150.500000,-44.000000,0.000000,top +"U1","TPS54302DDCR","TI_DDC0006A_SOT23_6",34.000000,-103.500000,0.000000,top +"U2","OPA2192ID","SOIC8_3.9x4.9_P1.27",151.000000,-61.500000,0.000000,top diff --git a/hardware/panel/fab/source_sha256.txt b/hardware/panel/fab/source_sha256.txt new file mode 100644 index 0000000..ba219dd --- /dev/null +++ b/hardware/panel/fab/source_sha256.txt @@ -0,0 +1 @@ +5c37aa04e39cf2ce4aefce5373201c6c3f49c9220217e3084b0abb485bc1dad0 radian_panel.kicad_pcb diff --git a/hardware/panel/library/RadianPanel.kicad_sym b/hardware/panel/library/RadianPanel.kicad_sym new file mode 100644 index 0000000..127ca81 --- /dev/null +++ b/hardware/panel/library/RadianPanel.kicad_sym @@ -0,0 +1,5499 @@ +(kicad_symbol_lib + (version 20231120) + (generator "radian_panel_generator") + (symbol "J100" + (pin_names + (offset 0.508)) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 29.209999999999997 0) + (effects + (font + (size 1.27 1.27)))) + (property "Value" "IPS1-110-01-L-D" + (at 0 -29.209999999999997 0) + (effects + (font + (size 1.27 1.27)))) + (property "Footprint" "RadianPanel:Stack_2x10_P2.54" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (symbol "J100_0_1" + (rectangle + (start -10.16 26.669999999999998) + (end 10.16 -26.669999999999998) + (stroke + (width 0.254) + (type default)) + (fill + (type background)))) + (symbol "J100_1_1" + (pin passive line + (at -12.7 24.13 0) + (length 2.54) + (name "1" + (effects + (font + (size 1.0 1.0)))) + (number "1" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 21.59 0) + (length 2.54) + (name "2" + (effects + (font + (size 1.0 1.0)))) + (number "2" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 19.05 0) + (length 2.54) + (name "3" + (effects + (font + (size 1.0 1.0)))) + (number "3" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 16.51 0) + (length 2.54) + (name "4" + (effects + (font + (size 1.0 1.0)))) + (number "4" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 13.97 0) + (length 2.54) + (name "5" + (effects + (font + (size 1.0 1.0)))) + (number "5" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 11.43 0) + (length 2.54) + (name "6" + (effects + (font + (size 1.0 1.0)))) + (number "6" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 8.89 0) + (length 2.54) + (name "7" + (effects + (font + (size 1.0 1.0)))) + (number "7" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 6.35 0) + (length 2.54) + (name "8" + (effects + (font + (size 1.0 1.0)))) + (number "8" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 3.81 0) + (length 2.54) + (name "9" + (effects + (font + (size 1.0 1.0)))) + (number "9" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 1.27 0) + (length 2.54) + (name "10" + (effects + (font + (size 1.0 1.0)))) + (number "10" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -1.27 0) + (length 2.54) + (name "11" + (effects + (font + (size 1.0 1.0)))) + (number "11" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -3.81 0) + (length 2.54) + (name "12" + (effects + (font + (size 1.0 1.0)))) + (number "12" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -6.35 0) + (length 2.54) + (name "13" + (effects + (font + (size 1.0 1.0)))) + (number "13" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -8.89 0) + (length 2.54) + (name "14" + (effects + (font + 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1.0)))) + (number "20" + (effects + (font + (size 1.0 1.0)))))) + (property "Description" "Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity." + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "Samtec" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (symbol "J101" + (pin_names + (offset 0.508)) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 29.209999999999997 0) + (effects + (font + (size 1.27 1.27)))) + (property "Value" "IPS1-110-01-L-D" + (at 0 -29.209999999999997 0) + (effects + (font + (size 1.27 1.27)))) + (property "Footprint" "RadianPanel:Stack_2x10_P2.54" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (symbol "J101_0_1" + (rectangle + (start -10.16 26.669999999999998) + (end 10.16 -26.669999999999998) + (stroke + (width 0.254) + (type default)) + (fill + (type background)))) + (symbol "J101_1_1" + (pin passive line + (at -12.7 24.13 0) + (length 2.54) + (name "1" + (effects + (font + (size 1.0 1.0)))) + (number "1" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 21.59 0) + (length 2.54) + (name "2" + (effects + (font + (size 1.0 1.0)))) + (number "2" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 19.05 0) + (length 2.54) + (name "3" + (effects + (font + (size 1.0 1.0)))) + (number "3" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 16.51 0) + (length 2.54) + (name "4" + (effects + (font + (size 1.0 1.0)))) + (number "4" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 13.97 0) + (length 2.54) + (name "5" + (effects + (font + (size 1.0 1.0)))) + (number "5" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 11.43 0) + (length 2.54) + (name "6" + (effects + (font + (size 1.0 1.0)))) + (number "6" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 8.89 0) + (length 2.54) + (name "7" + (effects + (font + (size 1.0 1.0)))) + (number "7" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 6.35 0) + (length 2.54) + (name "8" + (effects + (font + (size 1.0 1.0)))) + (number "8" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 3.81 0) + (length 2.54) + (name "9" + (effects + (font + (size 1.0 1.0)))) + (number "9" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 1.27 0) + (length 2.54) + (name "10" + (effects + (font + (size 1.0 1.0)))) + (number "10" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -1.27 0) + (length 2.54) + (name "11" + (effects + (font + (size 1.0 1.0)))) + (number "11" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -3.81 0) + (length 2.54) + (name "12" + (effects + (font + (size 1.0 1.0)))) + (number "12" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -6.35 0) + (length 2.54) + (name "13" + (effects + (font + (size 1.0 1.0)))) + (number "13" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -8.89 0) + (length 2.54) + (name "14" + (effects + (font + (size 1.0 1.0)))) + (number "14" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -11.43 0) + (length 2.54) + (name "15" + (effects + (font + (size 1.0 1.0)))) + (number "15" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -13.97 0) + (length 2.54) + (name "16" + (effects + (font + (size 1.0 1.0)))) + (number "16" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -16.51 0) + (length 2.54) + (name "17" + (effects + (font + (size 1.0 1.0)))) + (number "17" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -19.05 0) + (length 2.54) + (name "18" + (effects + (font + (size 1.0 1.0)))) + (number "18" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -21.59 0) + (length 2.54) + (name "19" + (effects + (font + (size 1.0 1.0)))) + (number "19" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -24.13 0) + (length 2.54) + (name "20" + (effects + (font + (size 1.0 1.0)))) + (number "20" + (effects + (font + (size 1.0 1.0)))))) + (property "Description" "Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity." + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "Samtec" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (symbol "RV1" + (pin_names + (offset 0.508)) + (in_bom yes) + (on_board yes) + (property "Reference" "RV" + (at 0 7.62 0) + (effects + (font + (size 1.27 1.27)))) + (property "Value" "10k linear / TENSION" + (at 0 -7.62 0) + (effects + (font + (size 1.27 1.27)))) + (property "Footprint" "RadianPanel:Bourns_PTV09A4_RearFacing" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (symbol "RV1_0_1" + (rectangle + (start -10.16 5.08) + (end 10.16 -5.08) + (stroke + (width 0.254) + (type default)) + (fill + (type background)))) + (symbol "RV1_1_1" + (pin passive line + (at -12.7 2.54 0) + (length 2.54) + (name "1" + (effects + (font + (size 1.0 1.0)))) + (number "1" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 0.0 0) + (length 2.54) + (name "2" + (effects + (font + (size 1.0 1.0)))) + (number "2" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -2.54 0) + (length 2.54) + (name "3" + (effects + (font + (size 1.0 1.0)))) + (number "3" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at 12.7 1.27 180) + (length 2.54) + (name "MP1" + (effects + (font + (size 1.0 1.0)))) + (number "MP1" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at 12.7 -1.27 180) + (length 2.54) + (name "MP2" + (effects + (font + (size 1.0 1.0)))) + (number "MP2" + (effects + (font + (size 1.0 1.0)))))) + (property "Description" "Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. 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(in_bom yes) + (on_board yes) + (property "Reference" "TP" + (at 0 7.62 0) + (effects + (font + (size 1.27 1.27)))) + (property "Value" "MOD_BIPOLAR" + (at 0 -7.62 0) + (effects + (font + (size 1.27 1.27)))) + (property "Footprint" "RadianPanel:TestPoint_D2" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (symbol "TP5_0_1" + (circle + (center 0 0) + (radius 1) + (stroke + (width 0.15) + (type default)) + (fill + (type none)))) + (symbol "TP5_1_1" + (pin passive line + (at -10.16 0 0) + (length 2.54) + (name "1" + (effects + (font + (size 1.0 1.0)))) + (number "1" + (effects + (font + (size 1.0 1.0)))))) + (property "Description" "Exposed soldermask aperture, no component." + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (symbol "PWR_FLAG" + (power) + (pin_names + (offset 0) + hide) + (in_bom yes) + (on_board yes) + (property "Reference" "#FLG" + (at 0 1.905 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Value" "PWR_FLAG" + (at 0 3.81 0) + (effects + (font + (size 1.27 1.27)))) + (property "Footprint" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Datasheet" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Description" "ERC power-source declaration; not a physical regulator" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (symbol "PWR_FLAG_0_0" + (pin power_out line + (at 0 0 90) + (length 0) + (name "~" + (effects + (font + (size 1.27 1.27)))) + (number "1" + (effects + (font + (size 1.27 1.27)))))) + (symbol "PWR_FLAG_0_1" + (polyline + (pts + (xy 0 0) + (xy 0 1.27) + (xy -1.016 1.905) + (xy 0 2.54) + (xy 1.016 1.905) + (xy 0 1.27)) + (stroke + (width 0) + (type default)) + (fill + (type none)))))) diff --git a/hardware/panel/library/RadianPanel.pretty/Bourns_PEC11R4_RearFacing_Switch.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Bourns_PEC11R4_RearFacing_Switch.kicad_mod new file mode 100644 index 0000000..636d1c3 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Bourns_PEC11R4_RearFacing_Switch.kicad_mod @@ -0,0 +1,25 @@ +(footprint "Bourns_PEC11R4_RearFacing_Switch" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -9.5 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "24 PPR / PUSH" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "Bourns" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "PEC11R-4220F-S0024" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -7 -8) (end 7 8) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -8.25 -8.65) (end 8.25 8.65) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -7 -8) (end -6.4 -8) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 7 8) (end 6.4 8) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "A" thru_hole circle (at -2.5 7.5 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "1859fb2d-0c2d-568b-9adc-f0a72a6b944d") ) +(pad "C" thru_hole circle (at 0 7.5 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "93e544f1-031b-5a06-b8fa-d5c515557d7e") ) +(pad "B" thru_hole circle (at 2.5 7.5 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "56548674-8d68-5028-b074-7be76aa68369") ) +(pad "S1" thru_hole circle (at -2.5 -7 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "c6863ea1-6c3d-518c-8275-058a2742896a") ) +(pad "S2" thru_hole circle (at 2.5 -7 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "2673cace-b575-5335-af12-626f7abdfca0") ) +(pad "MP1" thru_hole oval (at -6.6 0 0) (size 2.8 3.6) (drill oval 1.8 2.6) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "2d603c39-a9c7-56e5-829e-1cf1ff857b1c") ) +(pad "MP2" thru_hole oval (at 6.6 0 0) (size 2.8 3.6) (drill oval 1.8 2.6) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "a5850a2e-b6b0-539b-9daa-319f133c9fbb") ) + + (model "${KIPRJMOD}/../cad/models/Bourns_PEC11R_4220F_S0024_drawing_reference.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Bourns_PTV09A4_RearFacing.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Bourns_PTV09A4_RearFacing.kicad_mod new file mode 100644 index 0000000..019b2a2 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Bourns_PTV09A4_RearFacing.kicad_mod @@ -0,0 +1,23 @@ +(footprint "Bourns_PTV09A4_RearFacing" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -7 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "10k linear / TENSION" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "Bourns" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "PTV09A-4020F-B103" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -5.7 -5.5) (end 5.7 5.5) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -6.95 -8.15) (end 6.95 8.15) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -5.7 -5.5) (end -5.1 -5.5) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 5.7 5.5) (end 5.1 5.5) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" thru_hole circle (at -2.5 7 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" thru_hole circle (at 0 7 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) +(pad "3" thru_hole circle (at 2.5 7 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "01e8bae5-0e19-5e9d-8c1d-7ac71e980461") ) +(pad "MP1" thru_hole oval (at -5.3 0 0) (size 2.8 3.2) (drill oval 1.8 2.2) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "4866c691-f0b9-55ff-8395-52be1761b3aa") ) +(pad "MP2" thru_hole oval (at 5.3 0 0) (size 2.8 3.2) (drill oval 1.8 2.2) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "2fea0f1d-a00d-58e4-999c-7d7748fcbdcd") ) + + (model "${KIPRJMOD}/../cad/models/Bourns_PTV09A_4020F_family_actual.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Bourns_SRP7050TA.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Bourns_SRP7050TA.kicad_mod new file mode 100644 index 0000000..6042357 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Bourns_SRP7050TA.kicad_mod @@ -0,0 +1,20 @@ +(footprint "Bourns_SRP7050TA" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -4.8 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "10uH 4A / Isat7.5A" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "Bourns" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "SRP7050TA-100M" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -3.65 -3.3) (end 3.65 3.3) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -4.45 -3.55) (end 4.45 3.55) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -3.65 -3.3) (end -3.05 -3.3) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 3.65 3.3) (end 3.05 3.3) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" smd roundrect (at -2.95 0 0) (size 2.5 3.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.20) (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" smd roundrect (at 2.95 0 0) (size 2.5 3.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.20) (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) + + (model "${KIPRJMOD}/../cad/models/Bourns_SRP7050TA_100M_drawing_reference.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/C_0603.kicad_mod b/hardware/panel/library/RadianPanel.pretty/C_0603.kicad_mod new file mode 100644 index 0000000..926a30d --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/C_0603.kicad_mod @@ -0,0 +1,80 @@ +(footprint "C_0603" + (layer "F.Cu") + (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") + (version 20260206) + (generator "radian_panel_generator") + (property "Reference" "REF**" + (at 0 -1.9 0) + (layer "F.SilkS") + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Value" "100nF" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Manufacturer" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "MPN" "SELECT 100nF 50V X7R 0603" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Description" "50V X7R; verify effective capacitance at DC bias" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (fp_rect + (start -0.8 -0.4) + (end 0.8 0.4) + (stroke + (width 0.1) + (type default)) + (fill none) + (layer "F.Fab")) + (fp_rect + (start -1.5 -0.725) + (end 1.5 0.725) + (stroke + (width 0.05) + (type default)) + (fill none) + (layer "F.CrtYd")) + (pad "1" smd roundrect + (at -0.825 0 0) + (size 0.85 0.95) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "333632a0-b57f-5011-9a6d-4df43b026673")) + (pad "2" smd roundrect + (at 0.825 0 0) + (size 0.85 0.95) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900")) + (model "${KIPRJMOD}/../cad/models/C_0603_package.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/library/RadianPanel.pretty/C_0805.kicad_mod b/hardware/panel/library/RadianPanel.pretty/C_0805.kicad_mod new file mode 100644 index 0000000..9b7fb48 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/C_0805.kicad_mod @@ -0,0 +1,80 @@ +(footprint "C_0805" + (layer "F.Cu") + (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") + (version 20260206) + (generator "radian_panel_generator") + (property "Reference" "REF**" + (at 0 -2.125 0) + (layer "F.SilkS") + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Value" "1uF" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Manufacturer" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "MPN" "SELECT 1uF 16V X7R 0805" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Description" "16V X7R; verify effective capacitance at DC bias" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (fp_rect + (start -1 -0.625) + (end 1 0.625) + (stroke + (width 0.1) + (type default)) + (fill none) + (layer "F.Fab")) + (fp_rect + (start -1.875 -0.95) + (end 1.875 0.95) + (stroke + (width 0.05) + (type default)) + (fill none) + (layer "F.CrtYd")) + (pad "1" smd roundrect + (at -1.05 0 0) + (size 1.15 1.4) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "333632a0-b57f-5011-9a6d-4df43b026673")) + (pad "2" smd roundrect + (at 1.05 0 0) + (size 1.15 1.4) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900")) + (model "${KIPRJMOD}/../cad/models/C_0805_package.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/library/RadianPanel.pretty/C_1210.kicad_mod b/hardware/panel/library/RadianPanel.pretty/C_1210.kicad_mod new file mode 100644 index 0000000..c3c776c --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/C_1210.kicad_mod @@ -0,0 +1,80 @@ +(footprint "C_1210" + (layer "F.Cu") + (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") + (version 20260206) + (generator "radian_panel_generator") + (property "Reference" "REF**" + (at 0 -2.75 0) + (layer "F.SilkS") + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Value" "10uF" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Manufacturer" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "MPN" "SELECT 10uF 50V X7R 1210" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Description" "50V X7R; verify effective capacitance at DC bias" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (fp_rect + (start -1.6 -1.25) + (end 1.6 1.25) + (stroke + (width 0.1) + (type default)) + (fill none) + (layer "F.Fab")) + (fp_rect + (start -2.65 -1.7) + (end 2.65 1.7) + (stroke + (width 0.05) + (type default)) + (fill none) + (layer "F.CrtYd")) + (pad "1" smd roundrect + (at -1.65 0 0) + (size 1.5 2.9) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "333632a0-b57f-5011-9a6d-4df43b026673")) + (pad "2" smd roundrect + (at 1.65 0 0) + (size 1.5 2.9) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900")) + (model "${KIPRJMOD}/../cad/models/C_1210_package.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/library/RadianPanel.pretty/D_SMB.kicad_mod b/hardware/panel/library/RadianPanel.pretty/D_SMB.kicad_mod new file mode 100644 index 0000000..7a1fb59 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/D_SMB.kicad_mod @@ -0,0 +1,20 @@ +(footprint "D_SMB" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -3.3 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "SS54 / OR" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "Vishay" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "SS54-E3/57T" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -2.7 -1.8) (end 2.7 1.8) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -4.05 -2.05) (end 4.05 2.05) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -2.7 -1.8) (end -2.1 -1.8) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 2.7 1.8) (end 2.1 1.8) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" smd roundrect (at -2.7 0 0) (size 2.2 2.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.20) (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" smd roundrect (at 2.7 0 0) (size 2.2 2.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.20) (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) + + (model "${KIPRJMOD}/../cad/models/D_SMB_package.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/E_Switch_100SP_M2.kicad_mod b/hardware/panel/library/RadianPanel.pretty/E_Switch_100SP_M2.kicad_mod new file mode 100644 index 0000000..312fcd6 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/E_Switch_100SP_M2.kicad_mod @@ -0,0 +1,21 @@ +(footprint "E_Switch_100SP_M2" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -7.85 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "MODE / SPDT ON-ON" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "E-Switch" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "100SP1T1B1M2REH" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -3.43 -6.35) (end 3.43 6.35) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -3.68 -6.6) (end 3.68 6.6) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -3.43 -6.35) (end -2.83 -6.35) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 3.43 6.35) (end 2.83 6.35) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" thru_hole circle (at 0 4.7 0) (size 2.8 2.8) (drill 1.85) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" thru_hole circle (at 0 0 0) (size 2.8 2.8) (drill 1.85) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) +(pad "3" thru_hole circle (at 0 -4.7 0) (size 2.8 2.8) (drill 1.85) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "01e8bae5-0e19-5e9d-8c1d-7ac71e980461") ) + + (model "${KIPRJMOD}/../cad/models/E_Switch_100SP1T1B1M2REH_drawing_reference.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Fuse_1206.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Fuse_1206.kicad_mod new file mode 100644 index 0000000..af73a3b --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Fuse_1206.kicad_mod @@ -0,0 +1,80 @@ +(footprint "Fuse_1206" + (layer "F.Cu") + (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") + (version 20260206) + (generator "radian_panel_generator") + (property "Reference" "REF**" + (at 0 -2.3 0) + (layer "F.SilkS") + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Value" "2A FUSE / >=32V" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Manufacturer" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "MPN" "SELECT 2 A >=32 V 1206 fuse" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Description" "Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate." + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (fp_rect + (start -1.6 -0.8) + (end 1.6 0.8) + (stroke + (width 0.1) + (type default)) + (fill none) + (layer "F.Fab")) + (fp_rect + (start -2.4 -1.15) + (end 2.4 1.15) + (stroke + (width 0.05) + (type default)) + (fill none) + (layer "F.CrtYd")) + (pad "1" smd roundrect + (at -1.5 0 0) + (size 1.3 1.8) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "333632a0-b57f-5011-9a6d-4df43b026673")) + (pad "2" smd roundrect + (at 1.5 0 0) + (size 1.3 1.8) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900")) + (model "${KIPRJMOD}/../cad/models/Fuse_1206_package.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/library/RadianPanel.pretty/Header_1x02_P2.54.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Header_1x02_P2.54.kicad_mod new file mode 100644 index 0000000..ad9e95b --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Header_1x02_P2.54.kicad_mod @@ -0,0 +1,14 @@ +(footprint "Header_1x02_P2.54" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -2.77 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "TO OFF-BOARD MIDI DIN" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "SELECT 2.54 mm 1x02 header" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -2.54 -1.27) (end 2.54 1.27) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -2.79 -1.52) (end 2.79 1.52) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -2.54 -1.27) (end -1.94 -1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 2.54 1.27) (end 1.94 1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" thru_hole rect (at -1.27 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" thru_hole circle (at 1.27 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Header_1x03_P2.54.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Header_1x03_P2.54.kicad_mod new file mode 100644 index 0000000..f91f2e4 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Header_1x03_P2.54.kicad_mod @@ -0,0 +1,15 @@ +(footprint "Header_1x03_P2.54" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -2.77 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "MOD RANGE: 1-2 UNI / 2-3 BI" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "2.54 mm 1x03 header + removable shunt" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -3.81 -1.27) (end 3.81 1.27) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -4.06 -1.52) (end 4.06 1.52) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -3.81 -1.27) (end -3.21 -1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 3.81 1.27) (end 3.21 1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" thru_hole rect (at -2.54 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" thru_hole circle (at 0 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) +(pad "3" thru_hole circle (at 2.54 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "01e8bae5-0e19-5e9d-8c1d-7ac71e980461") ) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Header_1x05_P2.54.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Header_1x05_P2.54.kicad_mod new file mode 100644 index 0000000..8c08d8f --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Header_1x05_P2.54.kicad_mod @@ -0,0 +1,17 @@ +(footprint "Header_1x05_P2.54" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -2.77 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "TO MAIN J9" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "SELECT 2.54 mm 1x5 header + mating cable" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "Pin-for-pin harness, NOT a stacking connector. Confirm current rating and actual mating housing." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -6.35 -1.27) (end 6.35 1.27) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -6.6 -1.52) (end 6.6 1.52) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -6.35 -1.27) (end -5.75 -1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 6.35 1.27) (end 5.75 1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" thru_hole rect (at -5.08 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" thru_hole circle (at -2.54 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) +(pad "3" thru_hole circle (at 0 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "01e8bae5-0e19-5e9d-8c1d-7ac71e980461") ) +(pad "4" thru_hole circle (at 2.54 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "8927fbc0-d5ca-5531-abc9-645da0621f64") ) +(pad "5" thru_hole circle (at 5.08 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "c8fde40b-474a-510f-b0ef-c4c8b8fa4feb") ) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Header_1x06_P2.54.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Header_1x06_P2.54.kicad_mod new file mode 100644 index 0000000..d0d9de1 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Header_1x06_P2.54.kicad_mod @@ -0,0 +1,18 @@ +(footprint "Header_1x06_P2.54" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -2.77 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "JTAG SERVICE" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "SELECT 2.54 mm 1x06 header" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -7.62 -1.27) (end 7.62 1.27) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -7.87 -1.52) (end 7.87 1.52) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -7.62 -1.27) (end -7.02 -1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 7.62 1.27) (end 7.02 1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" thru_hole rect (at -6.35 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" thru_hole circle (at -3.81 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) +(pad "3" thru_hole circle (at -1.27 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "01e8bae5-0e19-5e9d-8c1d-7ac71e980461") ) +(pad "4" thru_hole circle (at 1.27 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "8927fbc0-d5ca-5531-abc9-645da0621f64") ) +(pad "5" thru_hole circle (at 3.81 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "c8fde40b-474a-510f-b0ef-c4c8b8fa4feb") ) +(pad "6" thru_hole circle (at 6.35 0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "d29f0697-c1b6-575f-a436-c97c41716532") ) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/IDC_2x05_P2.54_Shrouded.kicad_mod b/hardware/panel/library/RadianPanel.pretty/IDC_2x05_P2.54_Shrouded.kicad_mod new file mode 100644 index 0000000..24e73ae --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/IDC_2x05_P2.54_Shrouded.kicad_mod @@ -0,0 +1,22 @@ +(footprint "IDC_2x05_P2.54_Shrouded" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -10.5 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "EURORACK 10 PIN" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "SELECT keyed 2x05 IDC 2.54 mm header" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -4.45 -9) (end 4.45 9) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -4.7 -9.25) (end 4.7 9.25) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -4.45 -9) (end -3.85 -9) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 4.45 9) (end 3.85 9) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" thru_hole rect (at -1.27 -5.08 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" thru_hole circle (at 1.27 -5.08 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) +(pad "3" thru_hole circle (at -1.27 -2.54 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "01e8bae5-0e19-5e9d-8c1d-7ac71e980461") ) +(pad "4" thru_hole circle (at 1.27 -2.54 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "8927fbc0-d5ca-5531-abc9-645da0621f64") ) +(pad "5" thru_hole circle (at -1.27 -0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "c8fde40b-474a-510f-b0ef-c4c8b8fa4feb") ) +(pad "6" thru_hole circle (at 1.27 -0 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "d29f0697-c1b6-575f-a436-c97c41716532") ) +(pad "7" thru_hole circle (at -1.27 2.54 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "fe5c60ff-78c4-5caf-9444-f29c5be904e9") ) +(pad "8" thru_hole circle (at 1.27 2.54 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "30e43d81-2be8-5b49-953f-74ae1b9417ca") ) +(pad "9" thru_hole circle (at -1.27 5.08 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "e8ede24a-7434-5064-b5c4-dd3de6006a2a") ) +(pad "10" thru_hole circle (at 1.27 5.08 0) (size 1.8 1.8) (drill 1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7f47a758-b41d-56bb-9b29-e8be594124d0") ) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/LED_D3.0_P2.54.kicad_mod b/hardware/panel/library/RadianPanel.pretty/LED_D3.0_P2.54.kicad_mod new file mode 100644 index 0000000..2faa753 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/LED_D3.0_P2.54.kicad_mod @@ -0,0 +1,20 @@ +(footprint "LED_D3.0_P2.54" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -3.4 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "VOICE 1" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "Kingbright" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "L-934GD" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -1.9 -1.9) (end 1.9 1.9) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -2.32 -2.15) (end 2.32 2.15) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -1.9 -1.9) (end -1.3 -1.9) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 1.9 1.9) (end 1.3 1.9) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" thru_hole circle (at -1.27 0 0) (size 1.6 1.6) (drill 0.9) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" thru_hole circle (at 1.27 0 0) (size 1.6 1.6) (drill 0.9) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) + + (model "${KIPRJMOD}/../cad/models/Kingbright_L934GD_package_green_centered.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Molex_22-27-2021_J201_B.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Molex_22-27-2021_J201_B.kicad_mod new file mode 100644 index 0000000..98fd853 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Molex_22-27-2021_J201_B.kicad_mod @@ -0,0 +1,16 @@ +(footprint "Molex_22-27-2021_J201_B" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -2.77 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "22-27-2021" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "22-27-2021" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -2.54 -1.27) (end 2.54 1.27) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -2.79 -1.52) (end 2.79 1.52) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -2.54 -1.27) (end -1.94 -1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 2.54 1.27) (end 1.94 1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" thru_hole rect (at -1.27 0 0) (size 1.6 1.6) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" thru_hole circle (at 1.27 0 0) (size 1.6 1.6) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) + +(model "${KIPRJMOD}/../cad/models/Molex_22-27-2021_centered.step" (offset (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0))) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Molex_22-27-2021_J306_B.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Molex_22-27-2021_J306_B.kicad_mod new file mode 100644 index 0000000..accf4c4 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Molex_22-27-2021_J306_B.kicad_mod @@ -0,0 +1,16 @@ +(footprint "Molex_22-27-2021_J306_B" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -2.77 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "22-27-2021" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "22-27-2021" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -2.54 -1.27) (end 2.54 1.27) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -2.79 -1.52) (end 2.79 1.52) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -2.54 -1.27) (end -1.94 -1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 2.54 1.27) (end 1.94 1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" thru_hole rect (at -1.27 0 0) (size 1.6 1.6) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" thru_hole circle (at 1.27 0 0) (size 1.6 1.6) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) + +(model "${KIPRJMOD}/../cad/models/Molex_22-27-2021_centered.step" (offset (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0))) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Molex_22-27-2061_J202_B.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Molex_22-27-2061_J202_B.kicad_mod new file mode 100644 index 0000000..d18d9d6 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Molex_22-27-2061_J202_B.kicad_mod @@ -0,0 +1,20 @@ +(footprint "Molex_22-27-2061_J202_B" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -2.77 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "22-27-2061" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "22-27-2061" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -7.62 -1.27) (end 7.62 1.27) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -7.87 -1.52) (end 7.87 1.52) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -7.62 -1.27) (end -7.02 -1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 7.62 1.27) (end 7.02 1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" thru_hole rect (at -6.35 0 0) (size 1.6 1.6) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" thru_hole circle (at -3.81 0 0) (size 1.6 1.6) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) +(pad "3" thru_hole circle (at -1.27 0 0) (size 1.6 1.6) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "01e8bae5-0e19-5e9d-8c1d-7ac71e980461") ) +(pad "4" thru_hole circle (at 1.27 0 0) (size 1.6 1.6) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "8927fbc0-d5ca-5531-abc9-645da0621f64") ) +(pad "5" thru_hole circle (at 3.81 0 0) (size 1.6 1.6) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "c8fde40b-474a-510f-b0ef-c4c8b8fa4feb") ) +(pad "6" thru_hole circle (at 6.35 0 0) (size 1.6 1.6) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "d29f0697-c1b6-575f-a436-c97c41716532") ) + +(model "${KIPRJMOD}/../cad/models/Molex_22-27-2061_centered.step" (offset (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0))) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Mount_NPTH.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Mount_NPTH.kicad_mod new file mode 100644 index 0000000..6b2a081 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Mount_NPTH.kicad_mod @@ -0,0 +1,42 @@ +(footprint "Mount_NPTH" + (version 20260206) + (generator "radian_native_cleanup") + (layer "F.Cu") + (property "Reference" "" + (at 0 0 0) + (layer "F.SilkS") + (uuid "c4fb6e21-cce0-4b62-9e52-6ce068c25e04") + (effects + (font + (size 1.27 1.27)))) + (property "Value" "" + (at 0 0 0) + (layer "F.Fab") + (uuid "d97feb12-e188-4d2a-b92d-c716abd91eba") + (effects + (font + (size 1.27 1.27)))) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "97b6f070-e203-40df-8036-29dd96b18564") + (effects + (font + (size 1.27 1.27)))) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "e668aaa6-993a-4210-b3bc-9119c2a14e79") + (effects + (font + (size 1.27 1.27)))) + (attr board_only exclude_from_pos_files exclude_from_bom) + (duplicate_pad_numbers_are_jumpers no) + (pad "" np_thru_hole circle + (at 0 0) + (size 2.7 2.7) + (drill 2.7) + (layers "*.Cu" "*.Mask")) + (embedded_fonts no)) diff --git a/hardware/panel/library/RadianPanel.pretty/R_0603.kicad_mod b/hardware/panel/library/RadianPanel.pretty/R_0603.kicad_mod new file mode 100644 index 0000000..f6a141c --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/R_0603.kicad_mod @@ -0,0 +1,80 @@ +(footprint "R_0603" + (layer "F.Cu") + (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") + (version 20260206) + (generator "radian_panel_generator") + (property "Reference" "REF**" + (at 0 -1.9 0) + (layer "F.SilkS") + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Value" "100k" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Manufacturer" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "MPN" "SELECT 100k 1% 0603" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Description" "Resistor 1%" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (fp_rect + (start -0.8 -0.4) + (end 0.8 0.4) + (stroke + (width 0.1) + (type default)) + (fill none) + (layer "F.Fab")) + (fp_rect + (start -1.5 -0.725) + (end 1.5 0.725) + (stroke + (width 0.05) + (type default)) + (fill none) + (layer "F.CrtYd")) + (pad "1" smd roundrect + (at -0.825 0 0) + (size 0.85 0.95) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "333632a0-b57f-5011-9a6d-4df43b026673")) + (pad "2" smd roundrect + (at 0.825 0 0) + (size 0.85 0.95) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900")) + (model "${KIPRJMOD}/../cad/models/R_0603_package.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/library/RadianPanel.pretty/SOIC8_3.9x4.9_P1.27.kicad_mod b/hardware/panel/library/RadianPanel.pretty/SOIC8_3.9x4.9_P1.27.kicad_mod new file mode 100644 index 0000000..d04be43 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/SOIC8_3.9x4.9_P1.27.kicad_mod @@ -0,0 +1,122 @@ +(footprint "SOIC8_3.9x4.9_P1.27" + (layer "F.Cu") + (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") + (version 20260206) + (generator "radian_panel_generator") + (property "Reference" "REF**" + (at 0 -3.95 0) + (layer "F.SilkS") + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Value" "OPA2192ID" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Manufacturer" "Texas Instruments" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "MPN" "OPA2192ID" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Description" "A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping." + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (fp_rect + (start -1.95 -2.45) + (end 1.95 2.45) + (stroke + (width 0.1) + (type default)) + (fill none) + (layer "F.Fab")) + (fp_rect + (start -3.725 -2.7) + (end 3.725 2.7) + (stroke + (width 0.05) + (type default)) + (fill none) + (layer "F.CrtYd")) + (pad "1" smd roundrect + (at -2.7 -1.905 0) + (size 1.55 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "333632a0-b57f-5011-9a6d-4df43b026673")) + (pad "2" smd roundrect + (at -2.7 -0.635 0) + (size 1.55 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900")) + (pad "3" smd roundrect + (at -2.7 0.635 0) + (size 1.55 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "01e8bae5-0e19-5e9d-8c1d-7ac71e980461")) + (pad "4" smd roundrect + (at -2.7 1.905 0) + (size 1.55 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "8927fbc0-d5ca-5531-abc9-645da0621f64")) + (pad "5" smd roundrect + (at 2.7 1.905 0) + (size 1.55 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "c8fde40b-474a-510f-b0ef-c4c8b8fa4feb")) + (pad "6" smd roundrect + (at 2.7 0.635 0) + (size 1.55 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "d29f0697-c1b6-575f-a436-c97c41716532")) + (pad "7" smd roundrect + (at 2.7 -0.635 0) + (size 1.55 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "fe5c60ff-78c4-5caf-9444-f29c5be904e9")) + (pad "8" smd roundrect + (at 2.7 -1.905 0) + (size 1.55 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "30e43d81-2be8-5b49-953f-74ae1b9417ca")) + (model "${KIPRJMOD}/../cad/models/OPA2192_SOIC8_package.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/library/RadianPanel.pretty/SOT23_BAT54S.kicad_mod b/hardware/panel/library/RadianPanel.pretty/SOT23_BAT54S.kicad_mod new file mode 100644 index 0000000..b05d9f7 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/SOT23_BAT54S.kicad_mod @@ -0,0 +1,94 @@ +(footprint "SOT23_BAT54S" + (layer "F.Cu") + (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") + (version 20260206) + (generator "radian_panel_generator") + (property "Reference" "REF**" + (at 0 -2.95 0) + (layer "F.SilkS") + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Value" "BAT54S" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Manufacturer" "Nexperia" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "MPN" "BAT54S,215" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Description" "Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior." + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (fp_rect + (start -0.7 -1.45) + (end 0.7 1.45) + (stroke + (width 0.1) + (type default)) + (fill none) + (layer "F.Fab")) + (fp_rect + (start -1.75 -1.7) + (end 1.75 1.7) + (stroke + (width 0.05) + (type default)) + (fill none) + (layer "F.CrtYd")) + (fp_line + (start 0.7 1.45) + (end 0.1 1.45) + (stroke + (width 0.15) + (type default)) + (layer "F.SilkS")) + (pad "1" smd roundrect + (at -1 -0.95 0) + (size 1 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "333632a0-b57f-5011-9a6d-4df43b026673")) + (pad "2" smd roundrect + (at -1 0.95 0) + (size 1 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900")) + (pad "3" smd roundrect + (at 1 0 0) + (size 1 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "01e8bae5-0e19-5e9d-8c1d-7ac71e980461")) + (model "${KIPRJMOD}/../cad/models/BAT54S_SOT23_package.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/library/RadianPanel.pretty/SW_PUSH_6x6_P6.5x4.5.kicad_mod b/hardware/panel/library/RadianPanel.pretty/SW_PUSH_6x6_P6.5x4.5.kicad_mod new file mode 100644 index 0000000..73f6ae8 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/SW_PUSH_6x6_P6.5x4.5.kicad_mod @@ -0,0 +1,94 @@ +(footprint "SW_PUSH_6x6_P6.5x4.5" + (layer "F.Cu") + (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") + (version 20260206) + (generator "radian_panel_generator") + (property "Reference" "REF**" + (at 0 -4.5 0) + (layer "F.SilkS") + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Value" "PROGRAM / SERVICE" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Manufacturer" "Omron" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "MPN" "B3F-1000" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Description" "Internal service push button, accessible after module removal." + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (fp_rect + (start -3 -3) + (end 3 3) + (stroke + (width 0.1) + (type default)) + (fill none) + (layer "F.Fab")) + (fp_rect + (start -4.4 -3.4) + (end 4.4 3.4) + (stroke + (width 0.05) + (type default)) + (fill none) + (layer "F.CrtYd")) + (pad "1" thru_hole circle + (at -3.25 2.25 0) + (size 1.8 1.8) + (drill 1) + (layers "*.Cu" "*.Mask") + (clearance 0.2) + (uuid "333632a0-b57f-5011-9a6d-4df43b026673")) + (pad "1" thru_hole circle + (at -3.25 -2.25 0) + (size 1.8 1.8) + (drill 1) + (layers "*.Cu" "*.Mask") + (clearance 0.2) + (uuid "4493563d-7c5f-5282-984b-590fe6b8234a")) + (pad "2" thru_hole circle + (at 3.25 2.25 0) + (size 1.8 1.8) + (drill 1) + (layers "*.Cu" "*.Mask") + (clearance 0.2) + (uuid "a62c7ed5-a9eb-5c89-93e4-8afa115e9d83")) + (pad "2" thru_hole circle + (at 3.25 -2.25 0) + (size 1.8 1.8) + (drill 1) + (layers "*.Cu" "*.Mask") + (clearance 0.2) + (uuid "2278dede-bafc-5d6a-97f3-27a699ee13ec")) + (model "${KIPRJMOD}/../cad/models/Omron_B3F_1000_centered.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/library/RadianPanel.pretty/SameSky_SD-50BV.kicad_mod b/hardware/panel/library/RadianPanel.pretty/SameSky_SD-50BV.kicad_mod new file mode 100644 index 0000000..dfb4917 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/SameSky_SD-50BV.kicad_mod @@ -0,0 +1,16 @@ +(footprint "SameSky_SD-50BV" + (version 20240108) (generator "radian_production_io") (layer "F.Cu") + (descr "Same Sky SD-50BV vertical 5-pin 180-degree DIN receptacle") + (property "Reference" "REF**" (at 0 0 0) (layer "F.Fab") hide (effects (font (size 1 1)))) + (property "Value" "SD-50BV" (at 0 0 0) (layer "F.Fab") hide (effects (font (size 1 1)))) + (property "MPN" "SD-50BV" (at 0 0 0) (layer "F.Fab") hide (effects (font (size 1 1)))) + (property "Manufacturer" "Same Sky" (at 0 0 0) (layer "F.Fab") hide (effects (font (size 1 1)))) + (fp_circle (center 0 0) (end 8.3 0) (stroke (width .05) (type default)) (fill none) (layer "F.CrtYd")) + (pad "1" thru_hole circle (at 0 -5.5) (size 2.2 2.2) (drill 1.4) (layers "*.Cu" "*.Mask")) + (pad "4" thru_hole circle (at -3.889087 -3.889087) (size 2.2 2.2) (drill 1.4) (layers "*.Cu" "*.Mask")) + (pad "2" thru_hole circle (at -5.5 0) (size 2.2 2.2) (drill 1.4) (layers "*.Cu" "*.Mask")) + (pad "5" thru_hole circle (at -3.889087 3.889087) (size 2.2 2.2) (drill 1.4) (layers "*.Cu" "*.Mask")) + (pad "3" thru_hole circle (at 0 5.5) (size 2.2 2.2) (drill 1.4) (layers "*.Cu" "*.Mask")) + (pad "MP" thru_hole circle (at 4.5 0) (size 2.2 2.2) (drill 1.4) (layers "*.Cu" "*.Mask")) + (model "${KIPRJMOD}/../cad/models/SameSky_SD-50BV_boardref.step" (offset (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0))) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Stack_2x10_P2.54.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Stack_2x10_P2.54.kicad_mod new file mode 100644 index 0000000..ac4a82f --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Stack_2x10_P2.54.kicad_mod @@ -0,0 +1,311 @@ +(footprint "Stack_2x10_P2.54" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -14.39 0) + (layer "F.SilkS") + (uuid "8e8f4b18-a716-4ac3-b571-10b03e6ceddc") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "IPS1-110-01-L-D" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "3412218d-b85e-4d74-bc24-7efec9297b0e") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "d878c367-95d5-4fb2-a578-7d8013b7118e") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity." + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "b73f2dcf-c7fd-4812-8f59-48241f839f1c") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Manufacturer" "Samtec" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "2f43cd71-b450-4faf-b043-e54368fc06b1") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "MPN" "IPS1-110-01-L-D" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "2b4d105b-d003-426a-bde0-fb75527fd1d1") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start -2.475 -12.89) + (end -1.875 -12.89) + (stroke + (width 0.15) + (type default) + ) + (layer "F.SilkS") + (uuid "b26aea87-1907-432f-950c-60286e208c46") + ) + (fp_line + (start 2.475 12.89) + (end 1.875 12.89) + (stroke + (width 0.15) + (type default) + ) + (layer "F.SilkS") + (uuid "f04a4064-25de-40f1-801d-5707f03fdded") + ) + (fp_rect + (start -2.725 -13.14) + (end 2.725 13.14) + (stroke + (width 0.05) + (type default) + ) + (fill no) + (layer "F.CrtYd") + (uuid "44492d15-e6c7-4be8-8f9f-8ed60b144571") + ) + (fp_rect + (start -2.475 -12.89) + (end 2.475 12.89) + (stroke + (width 0.1) + (type default) + ) + (fill no) + (layer "F.Fab") + (uuid "1b731182-abf2-43a3-b565-e2bfd5a36604") + ) + (pad "1" thru_hole rect + (at 1.27 -11.43) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "e32da25a-b4c1-45dd-a9e6-c3ea1f7bb15a") + ) + (pad "2" thru_hole circle + (at -1.27 -11.43) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "ba26dd04-e7d7-433a-9036-36b839adf911") + ) + (pad "3" thru_hole circle + (at 1.27 -8.89) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "8295547d-4cd6-4f0b-bbb2-353c5d8f9b0e") + ) + (pad "4" thru_hole circle + (at -1.27 -8.89) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "ee255d07-3ef1-49a6-b27c-b744ea8ed964") + ) + (pad "5" thru_hole circle + (at 1.27 -6.35) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "774472bf-f73e-4ee5-8e30-f79b278adcb6") + ) + (pad "6" thru_hole circle + (at -1.27 -6.35) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "ee608615-eff2-4907-afbf-dbf365deab50") + ) + (pad "7" thru_hole circle + (at 1.27 -3.81) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "b69c636d-c992-4d98-bc34-5c01758fcd0a") + ) + (pad "8" thru_hole circle + (at -1.27 -3.81) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "a6f400a9-9b60-4ac3-b889-894bd71d8a79") + ) + (pad "9" thru_hole circle + (at 1.27 -1.27) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "cc86e06c-26b5-4012-9965-313d5e2ff5ae") + ) + (pad "10" thru_hole circle + (at -1.27 -1.27) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "e03f84da-75a3-45cc-a62a-17e5027a734f") + ) + (pad "11" thru_hole circle + (at 1.27 1.27) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "b6418327-e46b-434f-8bf1-fc486a67973f") + ) + (pad "12" thru_hole circle + (at -1.27 1.27) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "fcb2fbfa-ae04-46cb-bf03-000a9357f591") + ) + (pad "13" thru_hole circle + (at 1.27 3.81) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "24cba2ab-2047-476a-b788-86e22ae278f9") + ) + (pad "14" thru_hole circle + (at -1.27 3.81) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "9764a429-cf7d-492f-a120-21e2ea8268b4") + ) + (pad "15" thru_hole circle + (at 1.27 6.35) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "d016f20a-1566-41e4-bb6f-a45a3c5c7a64") + ) + (pad "16" thru_hole circle + (at -1.27 6.35) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "6cc01a03-b4d3-4974-8bfe-fe66cf0f96d7") + ) + (pad "17" thru_hole circle + (at 1.27 8.89) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "51a70c04-8aa2-4ce0-a30d-273db6ff0c22") + ) + (pad "18" thru_hole circle + (at -1.27 8.89) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "fd65f655-91bc-49bb-bc53-daa96c265065") + ) + (pad "19" thru_hole circle + (at 1.27 11.43) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "5f536203-3b85-4197-9f26-65b1c9b6985d") + ) + (pad "20" thru_hole circle + (at -1.27 11.43) + (size 1.8 1.8) + (drill 1.04) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 0.2) + (uuid "04a9bfaa-1981-40af-929a-7be589e8ef16") + ) + (embedded_fonts no) + (model "${KIPRJMOD}/../../stack/models/Samtec_IPS1-110-01-L-D_drawing_reference.step" + (offset + (xyz 0 0 0) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 0) + ) + ) +) diff --git a/hardware/panel/library/RadianPanel.pretty/TI_DDC0006A_SOT23_6.kicad_mod b/hardware/panel/library/RadianPanel.pretty/TI_DDC0006A_SOT23_6.kicad_mod new file mode 100644 index 0000000..568b419 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/TI_DDC0006A_SOT23_6.kicad_mod @@ -0,0 +1,108 @@ +(footprint "TI_DDC0006A_SOT23_6" + (layer "F.Cu") + (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") + (version 20260206) + (generator "radian_panel_generator") + (property "Reference" "REF**" + (at 0 -2.95 0) + (layer "F.SilkS") + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Value" "TPS54302DDCR" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Manufacturer" "Texas Instruments" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "MPN" "TPS54302DDCR" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Description" "3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit." + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (fp_rect + (start -0.8 -1.45) + (end 0.8 1.45) + (stroke + (width 0.1) + (type default)) + (fill none) + (layer "F.Fab")) + (fp_rect + (start -1.85 -1.7) + (end 1.85 1.7) + (stroke + (width 0.05) + (type default)) + (fill none) + (layer "F.CrtYd")) + (pad "1" smd roundrect + (at -1.1 -0.95 0) + (size 1 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "333632a0-b57f-5011-9a6d-4df43b026673")) + (pad "2" smd roundrect + (at -1.1 0 0) + (size 1 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900")) + (pad "3" smd roundrect + (at -1.1 0.95 0) + (size 1 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "01e8bae5-0e19-5e9d-8c1d-7ac71e980461")) + (pad "4" smd roundrect + (at 1.1 0.95 0) + (size 1 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "8927fbc0-d5ca-5531-abc9-645da0621f64")) + (pad "5" smd roundrect + (at 1.1 0 0) + (size 1 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "c8fde40b-474a-510f-b0ef-c4c8b8fa4feb")) + (pad "6" smd roundrect + (at 1.1 -0.95 0) + (size 1 0.6) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "d29f0697-c1b6-575f-a436-c97c41716532")) + (model "${KIPRJMOD}/../cad/models/TPS54302_SOT23_6_package.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/library/RadianPanel.pretty/TagConnect_TC2030_IDC_NL.kicad_mod b/hardware/panel/library/RadianPanel.pretty/TagConnect_TC2030_IDC_NL.kicad_mod new file mode 100644 index 0000000..8fa1738 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/TagConnect_TC2030_IDC_NL.kicad_mod @@ -0,0 +1,228 @@ +(footprint "TagConnect_TC2030_IDC_NL" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (descr "Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2030-IDC-NL.pdf") + (tags "tag connect programming header pogo pins") + (property "Reference" "REF**" + (at 0 2.7 0) + (layer "F.SilkS") + (uuid "adf8cbe6-3f0f-433b-af61-fe5b4bf73d8e") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "Tag-Connect_TC2030-IDC-NL_2x03_P1.27mm_Vertical" + (at 0 -2.3 0) + (layer "F.Fab") + (uuid "9b218149-ded9-4af9-94db-b0a7aba25e7f") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "05de9503-bb18-410e-863b-ec0a4b6537f1") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "b21c31b6-7e33-4499-8805-83b448a9908e") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (attr exclude_from_pos_files exclude_from_bom) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start -1.905 1.27) + (end -1.905 0.635) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "2440e6d4-0daf-4eec-97b9-5f81bb5a2431") + ) + (fp_line + (start -1.27 1.27) + (end -1.905 1.27) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "a1bfd8f7-261d-4234-ae80-8c64873e2ab7") + ) + (fp_line + (start -3.5 -2) + (end 3.5 -2) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "1aba0165-c4dd-4219-baab-525735b4a8cc") + ) + (fp_line + (start -3.5 2) + (end -3.5 -2) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "538e511d-087a-4738-8dd5-a78e43f1258e") + ) + (fp_line + (start 3.5 -2) + (end 3.5 2) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "c27a14a3-5c92-4f97-919d-858062e7897f") + ) + (fp_line + (start 3.5 2) + (end -3.5 2) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "5de5fc8c-7a09-4f5e-9bc8-491057a1e53e") + ) + (fp_text user "KEEPOUT" + (at 0 0 0) + (layer "Cmts.User") + (uuid "d8cc238d-09dd-4065-911b-3899f2c71b14") + (effects + (font + (size 0.4 0.4) + (thickness 0.07) + ) + ) + ) + (fp_text user "${REFERENCE}" + (at 0 0 0) + (layer "F.Fab") + (uuid "0b8bdf4a-3622-41ae-b951-b4f24098fe4f") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (pad "" np_thru_hole circle + (at -2.54 0) + (size 0.9906 0.9906) + (drill 0.9906) + (layers "*.Cu" "*.Mask") + (uuid "d1d5cec1-b481-4d06-9a3c-dc2f3d9efa4c") + ) + (pad "" np_thru_hole circle + (at 2.54 -1.016) + (size 0.9906 0.9906) + (drill 0.9906) + (layers "*.Cu" "*.Mask") + (uuid "5355c404-a36b-488e-85f1-52eda51b75c4") + ) + (pad "" np_thru_hole circle + (at 2.54 1.016) + (size 0.9906 0.9906) + (drill 0.9906) + (layers "*.Cu" "*.Mask") + (uuid "14111820-4228-41d0-8072-7edac6bf4aba") + ) + (pad "1" connect circle + (at -1.27 0.635) + (size 0.7874 0.7874) + (layers "F.Cu" "F.Mask") + (uuid "b1f4cea2-d8ed-485d-973e-f1a377c554e8") + ) + (pad "2" connect circle + (at -1.27 -0.635) + (size 0.7874 0.7874) + (layers "F.Cu" "F.Mask") + (uuid "45d8e94f-155b-406c-98b5-a8dc2b802a24") + ) + (pad "3" connect circle + (at 0 0.635) + (size 0.7874 0.7874) + (layers "F.Cu" "F.Mask") + (uuid "ffacf613-4810-41ca-a086-cb7e3056446a") + ) + (pad "4" connect circle + (at 0 -0.635) + (size 0.7874 0.7874) + (layers "F.Cu" "F.Mask") + (uuid "659e371b-5f69-4ef0-9f3c-600bba994579") + ) + (pad "5" connect circle + (at 1.27 0.635) + (size 0.7874 0.7874) + (layers "F.Cu" "F.Mask") + (uuid "356bdc74-443f-47c5-8ce8-a3ed2c9255ee") + ) + (pad "6" connect circle + (at 1.27 -0.635) + (size 0.7874 0.7874) + (layers "F.Cu" "F.Mask") + (uuid "c69e1cc9-e21f-419e-9c91-24726f9c6382") + ) + (zone + (layer "F.Cu") + (uuid "55b6b040-a746-4424-a5b4-1f45a1d15120") + (hatch full 0.508) + (connect_pads + (clearance 0) + ) + (min_thickness 0.254) + (keepout + (tracks allowed) + (vias not_allowed) + (pads allowed) + (copperpour not_allowed) + (footprints not_allowed) + ) + (placement + (enabled no) + (sheetname "") + ) + (fill + (thermal_gap 0.508) + (thermal_bridge_width 0.508) + (island_removal_mode 0) + ) + (polygon + (pts + (xy 1.27 -0.635) (xy -1.27 -0.635) (xy -1.27 0.635) (xy 1.27 0.635) + ) + ) + ) + (embedded_fonts no) +) diff --git a/hardware/panel/library/RadianPanel.pretty/TagConnect_TC2030_IDC_NL_B.kicad_mod b/hardware/panel/library/RadianPanel.pretty/TagConnect_TC2030_IDC_NL_B.kicad_mod new file mode 100644 index 0000000..d2ddc03 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/TagConnect_TC2030_IDC_NL_B.kicad_mod @@ -0,0 +1,19 @@ +(footprint "TagConnect_TC2030_IDC_NL_B" + (version 20240108) (generator "radian_production_io") (layer "B.Cu") + (descr "Tag-Connect TC2030-IDC-NL 6-pin no-legs programming target, bottom-side") + (attr exclude_from_pos_files) + (property "Reference" "REF**" (at 0 0 0) (layer "B.Fab") hide (effects (font (size 1 1)) (justify mirror))) + (property "Value" "TC2030-IDC-NL" (at 0 0 0) (layer "B.Fab") hide (effects (font (size 1 1)) (justify mirror))) + (property "MPN" "TC2030-IDC-NL" (at 0 0 0) (layer "B.Fab") hide (effects (font (size 1 1)) (justify mirror))) + (property "Manufacturer" "Tag-Connect" (at 0 0 0) (layer "B.Fab") hide (effects (font (size 1 1)) (justify mirror))) + (fp_rect (start -3.5 -2) (end 3.5 2) (stroke (width .05) (type default)) (fill none) (layer "B.CrtYd")) + (pad "1" connect circle (at 1.27 .635) (size .7874 .7874) (layers "B.Cu" "B.Mask")) + (pad "2" connect circle (at 1.27 -.635) (size .7874 .7874) (layers "B.Cu" "B.Mask")) + (pad "3" connect circle (at 0 .635) (size .7874 .7874) (layers "B.Cu" "B.Mask")) + (pad "4" connect circle (at 0 -.635) (size .7874 .7874) (layers "B.Cu" "B.Mask")) + (pad "5" connect circle (at -1.27 .635) (size .7874 .7874) (layers "B.Cu" "B.Mask")) + (pad "6" connect circle (at -1.27 -.635) (size .7874 .7874) (layers "B.Cu" "B.Mask")) + (pad "" np_thru_hole circle (at 2.54 0) (size .9906 .9906) (drill .9906) (layers "*.Cu" "*.Mask")) + (pad "" np_thru_hole circle (at -2.54 1.016) (size .9906 .9906) (drill .9906) (layers "*.Cu" "*.Mask")) + (pad "" np_thru_hole circle (at -2.54 -1.016) (size .9906 .9906) (drill .9906) (layers "*.Cu" "*.Mask")) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/TestPoint_D2.kicad_mod b/hardware/panel/library/RadianPanel.pretty/TestPoint_D2.kicad_mod new file mode 100644 index 0000000..04d238c --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/TestPoint_D2.kicad_mod @@ -0,0 +1,67 @@ +(footprint "TestPoint_D2" + (layer "F.Cu") + (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") + (version 20260206) + (generator "radian_panel_generator") + (property "Reference" "REF**" + (at 0 -2.5 0) + (layer "F.SilkS") + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Value" "GND" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Manufacturer" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "MPN" "PCB test pad" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (property "Description" "Exposed soldermask aperture, no component." + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15)))) + (fp_rect + (start -1 -1) + (end 1 1) + (stroke + (width 0.1) + (type default)) + (fill none) + (layer "F.Fab")) + (fp_rect + (start -1.25 -1.25) + (end 1.25 1.25) + (stroke + (width 0.05) + (type default)) + (fill none) + (layer "F.CrtYd")) + (pad "1" smd roundrect + (at 0 0 0) + (size 2 2) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.20) + (clearance 0.2) + (uuid "333632a0-b57f-5011-9a6d-4df43b026673"))) diff --git a/hardware/panel/library/RadianPanel.pretty/WQP518MA_PJ398SM_Vertical.kicad_mod b/hardware/panel/library/RadianPanel.pretty/WQP518MA_PJ398SM_Vertical.kicad_mod new file mode 100644 index 0000000..18ee7ca --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/WQP518MA_PJ398SM_Vertical.kicad_mod @@ -0,0 +1,22 @@ +(footprint "WQP518MA_PJ398SM_Vertical" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -6.75 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "PITCH 0-5V" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "QingPu / Thonk" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "WQP518MA (Thonkiconn/PJ398SM)" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -4.5 -5.25) (end 4.5 5.25) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -4.75 -8.03) (end 4.75 8.03) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -4.5 -5.25) (end -3.9 -5.25) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 4.5 5.25) (end 3.9 5.25) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" thru_hole oval (at 0 6.48 0) (size 2.3 2.6) (drill oval 1 1.9) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" thru_hole oval (at 0 3.38 0) (size 2.3 2.6) (drill oval 1 1.9) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) +(pad "3" thru_hole oval (at 0 -4.92 0) (size 2.3 2.6) (drill oval 1 1.9) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "01e8bae5-0e19-5e9d-8c1d-7ac71e980461") ) +(pad "" np_thru_hole circle (at 0 0 0) (size 3 3) (drill 3) (layers "*.Cu" "*.Mask") (uuid "051c7f50-be4c-565c-8d97-6704ab2adf09") ) + + (model "${KIPRJMOD}/../cad/models/QingPu_PJ398SM_Knurl_actual.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Wurth_450301014042.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Wurth_450301014042.kicad_mod new file mode 100644 index 0000000..a034dc5 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Wurth_450301014042.kicad_mod @@ -0,0 +1,38 @@ +(footprint "Wurth_450301014042" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "Mini Slide Switch, Opposite Side Connection 10x2.5 mm, body 10x2.5x6.4mm, https://www.we-online.com/en/components/products/datasheet/450301014042?ki") + (tags "THT") + (attr through_hole) + (fp_text reference "REF**" (at 0 -2.5 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 848b5c45-2293-4dd8-ab8d-71a16feda60a) + ) + (fp_text value "SW_Wurth_WS-SLTV_450301014042" (at 0 2.5 unlocked) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 2d76e583-558a-4861-ac6d-43d44d683dc2) + ) + (fp_text user "${REFERENCE}" (at 0 0 unlocked) (layer "F.Fab") + (effects (font (size 0.5 0.5) (thickness 0.075))) + (tstamp 2f5a3520-a232-4079-a5d0-7773cb434782) + ) + (fp_line (start -0.4 -1.585) (end 0.4 -1.585) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 629c20b6-60e7-44a4-aee2-d920cea6a665)) + (fp_rect (start -5.11 -1.36) (end 5.11 1.36) + (stroke (width 0.12) (type solid)) (fill none) (layer "F.SilkS") (tstamp beca020c-dd2e-40dd-a395-62d8c41e0de9)) + (fp_rect (start -5.25 -1.5) (end 5.25 1.5) + (stroke (width 0.05) (type solid)) (fill none) (layer "F.CrtYd") (tstamp 70ceb2a6-8f24-463b-9607-1594069ac329)) + (fp_line (start -0.4 -1.25) (end 0 -0.77) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 1eb76ead-0c4b-4067-aa62-63f296298c1d)) + (fp_line (start 0.4 -1.25) (end 0 -0.77) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 5e1f7129-5313-4a84-b231-fdd4d13ec615)) + (fp_rect (start -5 -1.25) (end 5 1.25) + (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp 319d0ade-9681-4a91-aaac-fe86d1bd74d0)) + (pad "1" thru_hole rect (at 0 0) (size 1.3 1.3) (drill 0.8) (layers "*.Cu" "*.Mask") (tstamp fea13788-4025-42b4-aaec-24aeb9408de5)) + (pad "2" thru_hole circle (at -2.54 0) (size 1.3 1.3) (drill 0.8) (layers "*.Cu" "*.Mask") (tstamp 32998917-0055-45e1-8b79-7c73ec3e0c4a)) + (pad "3" thru_hole circle (at 2.54 0) (size 1.3 1.3) (drill 0.8) (layers "*.Cu" "*.Mask") (tstamp 8dec20c2-0bb5-4cc9-bdac-cd0f5631b755)) + (model "${KIPRJMOD}/../cad/models/Wurth_450301014042.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/hardware/panel/library/RadianPanel.pretty/Wurth_450301014042_B.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Wurth_450301014042_B.kicad_mod new file mode 100644 index 0000000..f73e39e --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Wurth_450301014042_B.kicad_mod @@ -0,0 +1,13 @@ +(footprint "Wurth_450301014042_B" + (version 20240108) (generator "radian_production_io") (layer "B.Cu") + (descr "Wurth WS-SLTV 450301014042 SPDT THT mini slide switch, bottom-side") + (property "Reference" "REF**" (at 0 0 0) (layer "B.Fab") hide (effects (font (size 1 1)) (justify mirror))) + (property "Value" "450301014042" (at 0 0 0) (layer "B.Fab") hide (effects (font (size 1 1)) (justify mirror))) + (property "MPN" "450301014042" (at 0 0 0) (layer "B.Fab") hide (effects (font (size 1 1)) (justify mirror))) + (property "Manufacturer" "Wurth Elektronik" (at 0 0 0) (layer "B.Fab") hide (effects (font (size 1 1)) (justify mirror))) + (fp_rect (start -5.5 -1.75) (end 5.5 1.75) (stroke (width .05) (type default)) (fill none) (layer "B.CrtYd")) + (pad "1" thru_hole rect (at 0 0) (size 1.3 1.3) (drill .8) (layers "*.Cu" "*.Mask")) + (pad "2" thru_hole circle (at -2.54 0) (size 1.3 1.3) (drill .8) (layers "*.Cu" "*.Mask")) + (pad "3" thru_hole circle (at 2.54 0) (size 1.3 1.3) (drill .8) (layers "*.Cu" "*.Mask")) + (model "${KIPRJMOD}/../cad/models/Wurth_450301014042.step" (offset (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0))) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Wurth_450301014042_Exact_B.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Wurth_450301014042_Exact_B.kicad_mod new file mode 100644 index 0000000..173247a --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Wurth_450301014042_Exact_B.kicad_mod @@ -0,0 +1,17 @@ +(footprint "Wurth_450301014042_Exact_B" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -2.77 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "450301014042" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "450301014042" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -3.81 -1.27) (end 3.81 1.27) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -4.06 -1.52) (end 4.06 1.52) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -3.81 -1.27) (end -3.21 -1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 3.81 1.27) (end 3.21 1.27) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "3" thru_hole rect (at -2.54 0 0) (size 1.3 1.3) (drill .8) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "1" thru_hole circle (at 0 0 0) (size 1.3 1.3) (drill .8) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) +(pad "2" thru_hole circle (at 2.54 0 0) (size 1.3 1.3) (drill .8) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "01e8bae5-0e19-5e9d-8c1d-7ac71e980461") ) + +(model "${KIPRJMOD}/../cad/models/Wurth_450301014042_native.step" (offset (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0))) +) diff --git a/hardware/panel/library/RadianPanel.pretty/Wurth_61201021621.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Wurth_61201021621.kicad_mod new file mode 100644 index 0000000..a885fc9 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Wurth_61201021621.kicad_mod @@ -0,0 +1,249 @@ +(footprint "Wurth_61201021621" + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (layer "F.Cu") + (descr "2.54 mm Male Box Header, body 20.36x9.1x12.1mm, https://www.we-online.com/en/components/products/datasheet/61201021621?ki") + (tags "THT") + (property "Reference" "REF**" + (at 1.27 -6.35 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "3b456430-352e-4c99-aa72-3994bf520101") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "J_Wurth_WR-BHD_61201021621" + (at 1.27 16.51 0) + (unlocked yes) + (layer "F.Fab") + (uuid "f37cde21-b229-430c-9910-087ff8e54c63") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 1.27 2.54 270) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "05d075f6-62b9-4806-a856-c42ebae51a3e") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 1.27 2.54 270) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "4993e440-5e42-4227-a829-c9d487dd200a") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (attr through_hole) + (fp_line + (start -3.74 -0.825) + (end -3.74 0.825) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "0032ecad-cd80-4410-8bbe-fa0d4d2bdd0a") + ) + (fp_rect + (start -3.265 -5.21) + (end 5.805 15.37) + (stroke + (width 0.12) + (type solid) + ) + (fill no) + (layer "F.SilkS") + (uuid "199dae6d-fd85-4cb7-a553-05de13e11a54") + ) + (fp_rect + (start -3.1555 2.83) + (end -2.4305 7.33) + (stroke + (width 0.12) + (type solid) + ) + (fill yes) + (layer "F.SilkS") + (uuid "5ea6793e-0bcd-4c14-891f-9b9ae7af18d8") + ) + (fp_rect + (start -3.655 -5.6) + (end 6.195 15.76) + (stroke + (width 0.05) + (type solid) + ) + (fill no) + (layer "F.CrtYd") + (uuid "0fb240be-ac00-4d68-8726-44ef2d098818") + ) + (fp_line + (start -2.405 0) + (end -3.155 -0.5) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "73601cb8-7610-482d-b453-02faceaedeac") + ) + (fp_line + (start -2.405 0) + (end -3.155 0.5) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "6c6aa682-a0ad-4808-a557-8f9fb8bbaadd") + ) + (fp_rect + (start -3.1555 2.83) + (end -2.4305 7.33) + (stroke + (width 0.1) + (type solid) + ) + (fill yes) + (layer "F.Fab") + (uuid "c5db3e63-08aa-4297-ba7f-df2f66973f01") + ) + (fp_rect + (start -3.155 -5.1) + (end 5.695 15.26) + (stroke + (width 0.1) + (type solid) + ) + (fill no) + (layer "F.Fab") + (uuid "c7a7d3ca-d7ef-4e4a-ae72-65187120f950") + ) + (fp_text user "${REFERENCE}" + (at 1.27 5.08 0) + (unlocked yes) + (layer "F.Fab") + (uuid "221acc09-2336-4401-8633-3415b9ff4c90") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (pad "1" thru_hole rect + (at 0 0 270) + (size 1.65 1.65) + (drill 1.1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (thermal_bridge_angle 45) + (uuid "3a4cd263-45b5-4677-a002-1562ebfea323") + ) + (pad "2" thru_hole circle + (at 2.54 0 270) + (size 1.65 1.65) + (drill 1.1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "0fef0606-fc02-45eb-895b-47cab131909e") + ) + (pad "3" thru_hole circle + (at 0 2.54 270) + (size 1.65 1.65) + (drill 1.1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "91cd3c4c-c53d-4239-9f5f-fb9095503fad") + ) + (pad "4" thru_hole circle + (at 2.54 2.54 270) + (size 1.65 1.65) + (drill 1.1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "5816fe01-9734-48ca-afc0-1ff2665c99dc") + ) + (pad "5" thru_hole circle + (at 0 5.08 270) + (size 1.65 1.65) + (drill 1.1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "173fb7ac-b206-4146-8dbe-6746e0c0baa9") + ) + (pad "6" thru_hole circle + (at 2.54 5.08 270) + (size 1.65 1.65) + (drill 1.1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "57728e16-b94a-4654-a5a2-7ef28a0310d0") + ) + (pad "7" thru_hole circle + (at 0 7.62 270) + (size 1.65 1.65) + (drill 1.1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "b007a673-44c2-43e3-80f9-1adc7510fcc9") + ) + (pad "8" thru_hole circle + (at 2.54 7.62 270) + (size 1.65 1.65) + (drill 1.1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "76add3b6-6ba7-49e5-800f-61eb7cfe1c3b") + ) + (pad "9" thru_hole circle + (at 0 10.16 270) + (size 1.65 1.65) + (drill 1.1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "c750b840-0d7a-415c-bcef-13b7180603c0") + ) + (pad "10" thru_hole circle + (at 2.54 10.16 270) + (size 1.65 1.65) + (drill 1.1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "65ca409e-827c-459e-beb6-5b75e8d6e102") + ) + (embedded_fonts no) + (model "${KIPRJMOD}/../cad/models/Wurth_61201021621.step" + (offset + (xyz 0 0 0) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 0) + ) + ) +) diff --git a/hardware/panel/library/RadianPanel.pretty/Wurth_61201021621_B.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Wurth_61201021621_B.kicad_mod new file mode 100644 index 0000000..7896152 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Wurth_61201021621_B.kicad_mod @@ -0,0 +1,20 @@ +(footprint "Wurth_61201021621_B" + (version 20240108) (generator "radian_production_io") (layer "B.Cu") + (descr "Wurth WR-BHD 61201021621 keyed 2x5 2.54mm THT header, bottom-side") + (property "Reference" "REF**" (at 0 0 0) (layer "B.Fab") hide (effects (font (size 1 1)) (justify mirror))) + (property "Value" "61201021621" (at 0 0 0) (layer "B.Fab") hide (effects (font (size 1 1)) (justify mirror))) + (property "MPN" "61201021621" (at 0 0 0) (layer "B.Fab") hide (effects (font (size 1 1)) (justify mirror))) + (property "Manufacturer" "Wurth Elektronik" (at 0 0 0) (layer "B.Fab") hide (effects (font (size 1 1)) (justify mirror))) + (fp_rect (start -6.195 -5.6) (end 3.655 15.76) (stroke (width .05) (type default)) (fill none) (layer "B.CrtYd")) + (pad "1" thru_hole rect (at 0 0) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask")) + (pad "2" thru_hole circle (at -2.54 0) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask")) + (pad "3" thru_hole circle (at 0 2.54) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask")) + (pad "4" thru_hole circle (at -2.54 2.54) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask")) + (pad "5" thru_hole circle (at 0 5.08) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask")) + (pad "6" thru_hole circle (at -2.54 5.08) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask")) + (pad "7" thru_hole circle (at 0 7.62) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask")) + (pad "8" thru_hole circle (at -2.54 7.62) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask")) + (pad "9" thru_hole circle (at 0 10.16) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask")) + (pad "10" thru_hole circle (at -2.54 10.16) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask")) + (model "${KIPRJMOD}/../cad/models/Wurth_61201021621.step" (offset (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0))) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Wurth_61201021621_Exact_B.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Wurth_61201021621_Exact_B.kicad_mod new file mode 100644 index 0000000..7b891a7 --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Wurth_61201021621_Exact_B.kicad_mod @@ -0,0 +1,24 @@ +(footprint "Wurth_61201021621_Exact_B" (layer "F.Cu") (uuid "6f768ca8-0c52-59a0-ba80-acad7d8d5539") +(version 20260206) (generator "radian_panel_generator") +(property "Reference" "REF**" (at 0 -10.5 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) +(property "Value" "61201021621" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Manufacturer" "" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "MPN" "61201021621" (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(property "Description" "Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections." (at 0 0 0) (layer "F.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15)))) +(fp_rect (start -4.45 -9) (end 4.45 9) (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab")) +(fp_rect (start -4.7 -9.25) (end 4.7 9.25) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) +(fp_line (start -4.45 -9) (end -3.85 -9) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(fp_line (start 4.45 9) (end 3.85 9) (stroke (width 0.15) (type default)) (layer "F.SilkS")) +(pad "1" thru_hole rect (at -1.27 -5.08 0) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "333632a0-b57f-5011-9a6d-4df43b026673") ) +(pad "2" thru_hole circle (at 1.27 -5.08 0) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7835a310-dea5-5e03-ac7e-6c1796b5f900") ) +(pad "3" thru_hole circle (at -1.27 -2.54 0) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "01e8bae5-0e19-5e9d-8c1d-7ac71e980461") ) +(pad "4" thru_hole circle (at 1.27 -2.54 0) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "8927fbc0-d5ca-5531-abc9-645da0621f64") ) +(pad "5" thru_hole circle (at -1.27 -0 0) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "c8fde40b-474a-510f-b0ef-c4c8b8fa4feb") ) +(pad "6" thru_hole circle (at 1.27 -0 0) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "d29f0697-c1b6-575f-a436-c97c41716532") ) +(pad "7" thru_hole circle (at -1.27 2.54 0) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "fe5c60ff-78c4-5caf-9444-f29c5be904e9") ) +(pad "8" thru_hole circle (at 1.27 2.54 0) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "30e43d81-2be8-5b49-953f-74ae1b9417ca") ) +(pad "9" thru_hole circle (at -1.27 5.08 0) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "e8ede24a-7434-5064-b5c4-dd3de6006a2a") ) +(pad "10" thru_hole circle (at 1.27 5.08 0) (size 1.65 1.65) (drill 1.1) (layers "*.Cu" "*.Mask") (clearance 0.2) (uuid "7f47a758-b41d-56bb-9b29-e8be594124d0") ) + +(model "${KIPRJMOD}/../cad/models/Wurth_61201021621_native.step" (offset (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0))) +) \ No newline at end of file diff --git a/hardware/panel/library/RadianPanel.pretty/Wurth_694106402002.kicad_mod b/hardware/panel/library/RadianPanel.pretty/Wurth_694106402002.kicad_mod new file mode 100644 index 0000000..bd998ee --- /dev/null +++ b/hardware/panel/library/RadianPanel.pretty/Wurth_694106402002.kicad_mod @@ -0,0 +1,46 @@ +(footprint "Wurth_694106402002" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "DC Power Jacks, body 9x10.7x14mm, https://www.we-online.com/en/components/products/datasheet/694106402002?ki") + (tags "THT") + (attr smd) + (fp_text reference "REF**" (at 3.5 -5.5 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e9b5894f-f357-44a8-a5c5-177c4e3b88d7) + ) + (fp_text value "J_Wurth_WR-DC_694106402002" (at 3.5 7.8 unlocked) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 8f8c1ff0-018a-4933-97e6-97134f229e89) + ) + (fp_text user "${REFERENCE}" (at 3.5 0 unlocked) (layer "F.Fab") + (effects (font (size 0.5 0.5) (thickness 0.075))) + (tstamp ed8ef6c3-b8d0-40b0-81d3-2f1fbfdc87e2) + ) + (fp_line (start -1.585 -0.5) (end -1.585 0.5) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 5ec60691-cbaf-4cc3-9756-b7e711632023)) + (fp_line (start -1.1 -4.3) (end 8.1 -4.3) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp dd2e8d6e-8772-4f1d-a2a9-64b2a67faac3)) + (fp_line (start -1.1 -2.4) (end -1.1 -4.3) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp f5acac28-b5b2-4621-a6a2-e847220df4b7)) + (fp_line (start -1.1 6.6) (end -1.1 2.4) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 46ce0d4d-1ad3-482f-a188-e7b0da61175b)) + (fp_line (start -1.1 6.6) (end 8.1 6.6) + (stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 12e7d757-037e-4bb4-a25c-b65a434485ba)) + (fp_line (start 8.1 -4.3) (end 8.1 6.6) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp c3439e78-e5a1-4325-a768-cc7a9a767bc4)) + (fp_rect (start -1.5 -4.7) (end 8.5 7) + (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd") (tstamp 3c231fa0-c8fc-4ef8-8f95-a7f90f434f7b)) + (fp_line (start -1 -0.5) (end -0.2 0) + (stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp a3b21a41-14d2-420e-bd79-68baa0b1bc11)) + (fp_line (start -0.2 0) (end -1 0.5) + (stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp dbe006ec-bca4-4945-bcce-3ad4ac689f50)) + (fp_rect (start -1 -4.2) (end 8 6.5) + (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab") (tstamp e0bb5171-5150-4ef1-b58e-d4883fe355e6)) + (pad "1" thru_hole rect (at 0 0) (size 2 4.25) (drill oval 0.8 3.5) (layers "*.Cu" "*.Mask") (tstamp acd0eac2-2169-4691-b9a8-2b0360bf12f3)) + (pad "2" thru_hole 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Existing FPGA mainboard unchanged. 40 HP / 3U + removable desktop dock. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +ENGINEERING DRAFT: not a fabrication release. Consult the latest native ERC/DRC reports. +ENGINEERING DRAFT: not a fabrication release. Consult the latest native ERC/DRC reports. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Default build: unipolar PITCH and MOD; line-level outputs; 12 V desktop / rack +12 V to onboard 5 V conversion. +Default build: unipolar PITCH and MOD; line-level outputs; 12 V desktop / rack +12 V to onboard 5 V conversion. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +DIN and dock inlet are the two intentional off-board cable connections. No extra custom carrier PCB is required. +DIN and dock inlet are the two intentional off-board cable connections. No extra custom carrier PCB is required. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +See ../docs/README.md for explicit unverified items and the bring-up procedure. +See ../docs/README.md for explicit unverified items and the bring-up procedure. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/panel/reference/courant-bom.csv b/hardware/panel/reference/courant-bom.csv new file mode 100644 index 0000000..cee27b1 --- /dev/null +++ b/hardware/panel/reference/courant-bom.csv @@ -0,0 +1,58 @@ +Reference(s),Qty,Value,Footprint,Side,Manufacturer,MPN,LCSC,Notes +"C100,C101,C102,C103,C104,C105,C106,C107,C108,C109,C110,C111,C112,C113,C114,C115,C116,C117,C118,C119,C120,C121,C122,C123,C124,C125,C126,C127,C128,C129,C130,C131,C132,C133,C134,C135,C136,C137",38,100nF,capacitor_cap0201,bottom,CCTC,TCC0201X5R104K100ZT,C5142565,10 V X5R. JLC extended library: one setup fee for the whole array +"C11,C21,C31,C146,C150,C151,C152,C161,C162,C166,C170,C172,C190,C195,C200",15,100nF,capacitor_cap0603,top,Samsung,CL10B104KB8NNNC,C1591,50 V X7R +"R12,R22,R32,R103,R104,R105,R106,R121,R130,R143,R144,R145,R146,R169",14,10kΩ,resistor_res0603,top,Yageo,RC0603FR-0710KL,C98220,thick film 1% +"R131,R132,R133,R140,R141,R142,R147,R148,R149,R150",10,1kΩ,resistor_res0603,top,Yageo,RC0603FR-071KL,,thick film 1% +"C174,C175,C176,C180,C181,C182,C193,C194",8,10nF,capacitor_cap0603,top,Murata,GRM1885C1H103JA01D,C85973,"50 V C0G -- ADC anti-alias, C0G for low voltage coefficient" +"R110,R114,R115,R122,R123,R124,R125",7,33Ω,resistor_res0603,top,Yageo,RC0603FR-0733RL,,thick film 1% +"C12,C13,C22,C23,C32,C33",6,22uF,capacitor_cap0805,top,Samsung,CL21A226MAQNNNE,C45783,"25 V X5R, JLC basic library -- switcher output" +"R100,R101,R102,R111,R112,R113",6,4.7kΩ,resistor_res0603,top,Yageo,RC0603FR-074K7L,,thick film 1% +"R11,R21,R31,R166",4,100kΩ,resistor_res0603,top,Yageo,RC0603FR-07100KL,,thick film 1% +"C10,C20,C30,C160",4,10uF,capacitor_cap0805,top,Samsung,CL21A106KAYNNNE,C15850,"25 V X5R, JLC basic library" +"R160,R161,R163,R164",4,20kΩ,resistor_res0603,top,Yageo,RT0603BRD0720KL,C723637,"0.1%, 25 ppm/C thin film -- matched CV divider pair" +"C1,C140,C141,C142",4,47uF,capacitor_cap1210,top,Murata,GRM32ER61C476KE15L,C77101,16 V X5R -- bulk input +"C191,C192,C196",3,1nF,capacitor_cap0603,top,Murata,GRM1885C1H102JA01D,,"50 V C0G, same series as the 10 nF" +"C165,C171,C173",3,1uF,capacitor_cap0603,top,Samsung,CL10B105KB8NQNC,C5199872,50 V X7R +"L1,L2,L3",3,1µH,inductor,top,cjiang,FNR4030S1R0MT,C167865,"4x4 mm shielded, 18 mOhm, 5.7 A sat -- must exceed the TPS62130's 3 A plus ripple" +"C14,C24,C34",3,3.3nF,capacitor_cap0603,top,Murata,GRM1885C1H332JA01D,,50 V C0G -- switcher soft-start +"C143,C144,C145",3,4.7uF,capacitor_cap0805,top,Yageo,CC0805KKX7R8BB475,C354262,25 V X7R +"D10,D11,D12",3,BAT54S,BAT54S,top,,BAT54S,,"dual Schottky, CV input clamp" +"U11,U12,U13",3,TPS62130ARGTR,TPS62130ARGTR,top,Texas Instruments,TPS62130ARGTR,,"3 A buck, QFN-16 with exposed pad" +"R162,R165",2,100Ω,resistor_res0603,top,Yageo,RC0603FR-07100RL,,thick film 1% +"C167,C168",2,2.2nF,capacitor_cap0603,top,Murata,GRM1885C1H222JA01D,,"50 V C0G, same series" +"C163,C164",2,2.2uF,capacitor_cap0603,top,Samsung,CL10A225KO8NNNC,C23630,"16 V X5R, JLC basic library" +"R126,R127",2,470Ω,resistor_res0603,top,Yageo,RC0603FR-07470RL,,thick film 1% +R20,1,124kΩ,resistor_res0603,top,Yageo,RC0603FR-07124KL,,thick film 1% +D20,1,1N4148W,1N4148W,top,,1N4148W,,signal diode +J12,1,1x02 header,PITCH_CV_GND,top,,"1x02 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +J4,1,1x02 header,RESET_GND,top,,"1x02 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +J1,1,1x02 header,5V_INPUT,top,,"1x02 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +J15,1,1x02 header,MIDI_DIN4_DIN5,top,,"1x02 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +J13,1,1x02 header,MOD_CV_GND,top,,"1x02 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +J14,1,1x02 header,GATE_GND,top,,"1x02 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +J3,1,1x02 header,PROGRAM_GND,top,,"1x02 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +J7,1,1x03 header,POT_DECAY_REF_WIPER_GND,top,,"1x03 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +J6,1,1x03 header,POT_PITCH_REF_WIPER_GND,top,,"1x03 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +J8,1,1x03 header,POT_TIMBRE_REF_WIPER_GND,top,,"1x03 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +J5,1,1x03 header,STEREO_LINE_OUT_L_G_R,top,,"1x03 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +J10,1,1x03 header,MODE_3V3_CV_SEL_GND,top,,"1x03 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +J9,1,1x05 header,ENCODER_A_GND_B_SW_GND,top,,"1x05 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +J11,1,1x05 header,STATUS_GND_VOICE0_3,top,,"1x05 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +J2,1,1x06 header,JTAG_VREF_GND_TCK_TDO_TDI_TMS,top,,"1x06 2.54 mm header, vertical THT",,panel harness connector -- mates to off-board hardware +R120,1,1Ω,resistor_res0603,top,Yageo,RC0603FR-071RL,,thick film 1% +R181,1,2.2kΩ,resistor_res0603,top,Yageo,RC0603FR-072K2L,,thick film 1% +R180,1,220Ω,resistor_res0603,top,Yageo,RC0603FR-07220RL,,thick film 1% +R10,1,24.9kΩ,resistor_res0603,top,Yageo,RC0603FR-0724K9L,C137761,thick film 1% +R30,1,316kΩ,resistor_res0603,top,Yageo,RC0603FR-07316KL,,thick film 1% +R167,1,33kΩ,resistor_res0603,top,Yageo,RC0603FR-0733KL,,thick film 1% +R168,1,40.2kΩ,resistor_res0603,top,Yageo,RC0603FR-0740K2L,,thick film 1% +Y1,1,ASE-100.000MHZ-LC-T,ASE-100_000MHZ-LC-T,top,Abracon,ASE-100.000MHZ-LC-T,,100 MHz system oscillator +Y2,1,ASE-12.288MHZ-LC-T,ASE-12_288MHZ-LC-T,top,Abracon,ASE-12.288MHZ-LC-T,,12.288 MHz audio master clock +U8,1,H11L1M,H11L1M,top,onsemi,H11L1M,,"Schmitt optocoupler, MIDI input" +U4,1,MCP3208-CI/SL,MCP3208-CI_SL,top,Microchip,MCP3208-CI/SL,,8-ch 12-bit SPI ADC +U6,1,MCP6002-I/SN,MCP6002-I_SN,top,Microchip,MCP6002-I/SN,,"dual op-amp, CV buffer" +U7,1,MCP6561T-E/OT,MCP6561T-E_OT,top,Microchip,MCP6561T-E/OT,,"comparator, gate input" +U3,1,PCM5102APWR,PCM5102APWR,top,Texas Instruments,PCM5102APWR,,stereo audio DAC +U5,1,REF3125AIDBZR,REF3125AIDBZR,top,Texas Instruments,REF3125AIDBZR,,2.5 V reference +U2,1,W25Q64JVSSIQ,W25Q64JVSSIQ,top,Winbond,W25Q64JVSSIQ,,64 Mbit SPI flash +U1,1,XC7A50T-1FTG256I,XC7A35T-1FTG256C,top,AMD/Xilinx,XC7A50T-1FTG256I,C3272410,"FPGA, 52160 logic cells, industrial temp" diff --git a/hardware/panel/reference/courant-panel-hardware.md b/hardware/panel/reference/courant-panel-hardware.md new file mode 100644 index 0000000..3f77144 --- /dev/null +++ b/hardware/panel/reference/courant-panel-hardware.md @@ -0,0 +1,51 @@ +# Courant Rev A — off-board (panel) hardware + +Nothing in this list is on the PCB. Every control and socket is panel-mounted +and wires to one of the fifteen 2.54 mm headers; `courant-panel-interface.csv` +gives the pin-by-pin mapping. The board was designed this way deliberately — +see `courant-source-design.ts:187` for the filter arrangement that depends on +it — so these are the parts that complete the instrument, not alternatives to +anything on the board. + +**These are selections, not decisions you have already made.** The design does +not name panel hardware, and the right choice depends on a panel format that +does not exist yet. Everything below is specified to be electrically correct +and mechanically ordinary; treat it as a starting BOM to argue with. + +## Sourced, with datasheets in `datasheets/` + +| Qty | Part | Manufacturer | MPN | ~$ ea | Feeds | +| --- | --- | --- | --- | --- | --- | +| 3 | 10 kΩ linear pot, 9 mm, 6 mm flatted shaft | Bourns | `PTV09A-4020F-B103` | 1.29 | J6 pitch, J7 decay, J8 timbre | +| 1 | Rotary encoder, 24 PPR, detented, with switch | Bourns | `PEC11R-4215F-S0024` | 2.95 | J9 | +| 4 | 3.5 mm TRS jack, right angle | Same Sky | `SJ1-3523N` | 1.12 | J5 line out, J12 pitch CV, J13 mod CV, J14 gate | +| 1 | DIN 5-pin socket, 180°, right angle | Same Sky | `SDS-50J` | 2.84 | J15 MIDI in | + +Panel hardware subtotal: **about $16 per instrument.** + +## Still to choose — trivial parts, but they depend on the panel + +| Qty | What | Note | +| --- | --- | --- | +| 4 | LEDs, 3 mm or 5 mm | J11. **Series resistors R147–R150 are on the board** — wire the LEDs directly, anode to the pin, cathode to the GND pin. Do not add panel resistors | +| 1 | SPDT toggle or slide switch | J10. Pin 1 is 3V3, pin 3 is GND, pin 2 is the wiper to `cv_select`. Any single-pole changeover | +| 1 | 5 V DC inlet | J1. The board expects **regulated 5 V**, externally fused. A 2.1 mm barrel jack (e.g. Same Sky `PJ-102AH`) or a 2-pin terminal block both work | + +## Three things worth knowing before wiring the panel + +**The pots are referenced to `VREF25`, not 3.3 V.** Pin 1 of J6/J7/J8 carries +the 2.5 V reference that the ADC also uses, so a wiper reading is ratiometric +and reference drift cancels instead of appearing as pitch drift. Do not wire +the pot top ends to a rail. + +**Keep the wiper runs as short as convenient, but do not add filtering.** The +1 kΩ series resistor sits on the board at the header and the 10 nF sits at the +ADC pin, which puts the cable *inside* the RC — anything the wiring picks up is +shunted at the ADC input rather than arriving at its sampling capacitor. A +capacitor added at the pot would defeat that. + +**The CV inputs expect 0–5 V unipolar.** They pass through 0.1 % matched 20 kΩ +dividers into an MCP6002 buffer, scaling to the ADC's 0–2.5 V span, with +BAT54S clamps to the rails. Bipolar Eurorack CV (±5 V) will clamp on the +negative half — if this needs to accept bipolar CV, that is a front-end change, +not a wiring choice. diff --git a/hardware/panel/reference/courant-panel-interface.csv b/hardware/panel/reference/courant-panel-interface.csv new file mode 100644 index 0000000..2e79cab --- /dev/null +++ b/hardware/panel/reference/courant-panel-interface.csv @@ -0,0 +1,46 @@ +Connector,Pin,Net,Purpose +J1,1,VIN5,"5 V DC input, externally fused" +J1,2,GND,"5 V DC input, externally fused" +J2,1,V3V3,"JTAG, to programmer" +J2,2,GND,"JTAG, to programmer" +J2,3,JTAG_TCK,"JTAG, to programmer" +J2,4,JTAG_TDO,"JTAG, to programmer" +J2,5,JTAG_TDI,"JTAG, to programmer" +J2,6,JTAG_TMS,"JTAG, to programmer" +J3,1,PROGRAM_B,"PROGRAM_B, momentary to GND forces reconfiguration" +J3,2,GND,"PROGRAM_B, momentary to GND forces reconfiguration" +J4,1,reset_n,"Reset, momentary to GND" +J4,2,GND,"Reset, momentary to GND" +J5,1,LINE_L,"Stereo line out, to panel jacks" +J5,2,GND,"Stereo line out, to panel jacks" +J5,3,LINE_R,"Stereo line out, to panel jacks" +J6,1,VREF25,"Pitch potentiometer, panel mounted" +J6,2,POT_PITCH_RAW,"Pitch potentiometer, panel mounted" +J6,3,GND,"Pitch potentiometer, panel mounted" +J7,1,VREF25,"Decay potentiometer, panel mounted" +J7,2,POT_DECAY_RAW,"Decay potentiometer, panel mounted" +J7,3,GND,"Decay potentiometer, panel mounted" +J8,1,VREF25,"Timbre potentiometer, panel mounted" +J8,2,POT_TIMBRE_RAW,"Timbre potentiometer, panel mounted" +J8,3,GND,"Timbre potentiometer, panel mounted" +J9,1,ENC_A_RAW,"Rotary encoder with switch, panel mounted" +J9,2,GND,"Rotary encoder with switch, panel mounted" +J9,3,ENC_B_RAW,"Rotary encoder with switch, panel mounted" +J9,4,ENC_SW_RAW,"Rotary encoder with switch, panel mounted" +J9,5,GND,"Rotary encoder with switch, panel mounted" +J10,1,V3V3,"Mode selector switch, panel mounted" +J10,2,cv_select,"Mode selector switch, panel mounted" +J10,3,GND,"Mode selector switch, panel mounted" +J11,1,GND,"Status LEDs x4, anodes -- series resistors are on-board" +J11,2,LED0_A,"Status LEDs x4, anodes -- series resistors are on-board" +J11,3,LED1_A,"Status LEDs x4, anodes -- series resistors are on-board" +J11,4,LED2_A,"Status LEDs x4, anodes -- series resistors are on-board" +J11,5,LED3_A,"Status LEDs x4, anodes -- series resistors are on-board" +J12,1,PITCH_IN,"Pitch CV input jack, 0-5 V" +J12,2,GND,"Pitch CV input jack, 0-5 V" +J13,1,MOD_IN,"Mod CV input jack, 0-5 V" +J13,2,GND,"Mod CV input jack, 0-5 V" +J14,1,GATE_IN,Gate input jack +J14,2,GND,Gate input jack +J15,1,MIDI4,"MIDI DIN socket, pins 4 and 5" +J15,2,MIDI5,"MIDI DIN socket, pins 4 and 5" diff --git a/hardware/panel/reference/input_manifest.json b/hardware/panel/reference/input_manifest.json new file mode 100644 index 0000000..c8b8865 --- /dev/null +++ b/hardware/panel/reference/input_manifest.json @@ -0,0 +1,56 @@ +[ + { + "file": "courant.kicad_pcb", + "sha256": "0683ead4a73049f5a2276b2cd3bf6389199609574a67aab8e27f48040a18deec", + "original_modified": false, + "matches_previous_CAD_input": true + }, + { + "file": "courant.kicad_pro", + "sha256": "c0e9824c19a95061b562f756c77f8a53870a33f02f0da2f811606eaa1efe2e29", + "original_modified": false, + "matches_previous_CAD_input": true + }, + { + "file": "courant-assembly.step", + "sha256": "5c2f0ce6bb0c26e9238e15df43c1ea901f06d30a4737d4bc70c42c0c9fc234b2", + "original_modified": false, + "matches_previous_CAD_input": true + }, + { + "file": "courant-panel-interface.csv", + "sha256": "6bc4fccbe2f51fdec63e53fe4295c54f5519a4a97a7b3e7603ddc4fc3440892d", + "original_modified": false, + "matches_previous_CAD_input": true + }, + { + "file": "courant-panel-hardware.md", + "sha256": "f17477e9ef2c793b653305bb57475ae2488c3f60ef81cae378ad133ce2b2d25e", + "original_modified": false, + "matches_previous_CAD_input": true + }, + { + "file": "courant-bom.csv", + "sha256": "4fe74896c152a276bd1a0a37fc066c6c26dd296950eadb39afc0c03581f3fb3f", + "original_modified": false, + "matches_previous_CAD_input": true + }, + { + "file": "courant-source-design.ts", + "sha256": "0554d412eced4c1fd5cdd44aef4780f26692f7103972e492ec83d79fcba2a45e", + "original_modified": false, + "matches_previous_CAD_input": true + }, + { + "file": "Bourns_PEC11R_encoder.pdf", + "sha256": "ac88f657e611bc82fe79b102426fb5abcb7f40740540f0c681727e2d74784491", + "original_modified": false, + "matches_previous_CAD_input": true + }, + { + "file": "Bourns_PTV09_potentiometer.pdf", + "sha256": "411cdb6a62e61f9c5bc2df76ed64ee21d7bcfbee035c1ba36beff08c43f28558", + "original_modified": false, + "matches_previous_CAD_input": true + } +] \ No newline at end of file diff --git a/hardware/panel/reports/CASE_UPDATE.md b/hardware/panel/reports/CASE_UPDATE.md new file mode 100644 index 0000000..5820cab --- /dev/null +++ b/hardware/panel/reports/CASE_UPDATE.md @@ -0,0 +1,25 @@ +# RADIAN case P3 two-row control update — 2026-09-18 + +The enclosure/product CAD now matches the two-row six-control panel and direct Samtec board stack. + +- Primary row: **TENSION · DECAY · CHAOS** with 23 mm reference knobs at **(38,96), (76,96), (114,96) mm**. +- FX row: **DRIVE · DELAY · REVERB** with 14 mm reference knobs at **(66,70), (88,70), (110,70) mm**. +- The engraving reinforces the hierarchy: primary labels sit above the large row; a compact **FX** group mark sits left of the lower row with the three effect labels beneath it. +- All six controls remain standard rear-facing Bourns PTV09A4 potentiometers on the PCB; knob size is an enclosure/assembly choice. +- The three legacy macro holes are closed and six current 6.8 mm shaft openings are modeled in the main faceplate. +- MODE is restored to the original raised insert at **(150.5,84.5) mm**. +- The encoder remains at **(42,43) mm** and the right-side jack/LED layout remains unchanged. +- Mainboard remains shifted **+0.46 mm toward the panel** for the **19.99 mm fully mated** PCB-to-PCB gap. +- Four front supports terminate at **z = -29.54 mm** and the rear spacer set reaches **z = -31.14 mm**; the rear guard remains unchanged. +- The assembly imports the current **exact-part native mainboard STEP**. All 180 BOM placements now carry production MPN metadata and a resolved 3D model; the retired J5–J15 edge headers remain absent. Re-running the full enclosure intersection check with this populated STEP still reports zero panel↔mainboard clashes and zero unintended enclosure intersections. Mainboard IPT1 and panel IPS1 are represented by drawing-derived 20-contact STEP reference models. +- The former generic panel utility headers are now selected parts: J200 Wurth 61201021621; J201/J306 Molex 22-27-2021; J202 Molex 22-27-2061; JP1 Wurth 450301014042 SPDT. The panel CAD imports selected-part Wurth/Molex STEP geometry for these parts and reports no panel↔mainboard clash. +- **The final product CAD no longer uses the old white generic component envelopes.** `RADIAN_actual_parts_full_assembly.step`, `RADIAN_P1_desktop_fit_study.step`, and `RADIAN_P1_case_updated.step` are assembled from component-filtered STEP exports of the **native KiCad panel and mainboard**, so component placement/orientation comes directly from the PCBs. +- Prominent panel hardware now uses real/open or package-accurate geometry: aligned Bourns PTV09A-family CAD for RV1–RV6 (20 mm selected-shaft configuration), PJ398SM/Thonkiconn mechanical CAD with knurled nut for J301–J305, Omron B3F package CAD for SW3/SW4, and a 3 mm green LED package for D10–D13. Standard IC/passive packages and selected Wurth/Molex parts likewise come from the models attached to KiCad. +- The remaining non-vendor-download solids are explicitly **MPN-specific drawing-derived reference models**, not generic boxes: ENC1 PEC11R-4220F-S0024, SW1 E-Switch 100SP1T1B1M2REH, Samtec J100/J101/J17/J18, and mainboard Molex J1–J4. Model provenance is recorded in `stack/actual_parts/actual_parts_report.json`. +- CAD validation reports zero control-hole conflicts, zero panel-component/mainboard clashes and zero unintended enclosure intersections. The rounded Samtec REF dimensions create a 0.01 mm housing-interface closure in the reference solids; the stack is separately checked at 19.99 mm PCB gap, 3.82 mm nominal geometric insertion and 0.84 mm nominal contact wipe. + +The selected enclosure endpoints are Switchcraft 722A for desktop 12 V and Same Sky SDS-50J for MIDI; both remain short-harness/chassis parts and require physical case-retention and strain-relief validation. The canonical full-product CAD now uses KiCad-placed actual/package component geometry rather than the former generic white component envelopes. The real/open PTV09A-family, PJ398SM, Omron B3F and LED models plus package-accurate IC/passive geometry are used directly; explicit drawing-derived references remain for PEC11R, the selected E-Switch and vendor-gated Samtec/Molex connectors. `stack/actual_parts/actual_part_collision_report.json` reports zero unintended panel↔mainboard and rear-guard/dock collisions. + +The final STEP is exported as individually colored physical solids so CAD viewers no longer substitute default white for component groups. Round-trip validation reports 715 colored children and zero uncolored/default-white children. U8 on the mainboard is separately pin/center-aligned to its native footprint before the assembly export. + +This is a checked reference mechanical model, not physical fit certification. The connector CAD is reconstructed from Samtec's official drawings because the vendor STEP download is email-gated. First-article connector seating/retention, knob/nut/washer stack and manufacturing tolerance remain required. diff --git a/hardware/panel/reports/STATUS.md b/hardware/panel/reports/STATUS.md new file mode 100644 index 0000000..07a89a6 --- /dev/null +++ b/hardware/panel/reports/STATUS.md @@ -0,0 +1,14 @@ +# RADIAN Panel P1 — integration status, 2026-09-18 + +The current panel is the six-pot, two-row direct-stack revision. Native KiCad 10.0.6 ERC, DRC, filled-zone connectivity and schematic/PCB parity all pass with zero findings. + +The performance controls now have a visual hierarchy: **TENSION / DECAY / CHAOS** form a widely spaced primary row intended for 23 mm knobs; **DRIVE / DELAY / REVERB** form a tighter FX row intended for 14 mm knobs. The PCB still uses the same six Bourns PTV09A4 rear-facing potentiometer footprints. MODE is restored to the original raised insert. + +The panel no longer connects to the mainboard through individual function harnesses. J100 and J101 are Samtec IPS1-110-01-L-D sockets mating mainboard J17/J18 Samtec IPT1-110-06-L-D terminal strips. The two 20-pin interfaces carry power, six pot controls, CV/gate, audio, encoder/MODE/LEDs, MIDI and service/JTAG. Only truly off-board functions such as the retained MIDI DIN and desktop inlet still use short leads. + +`../stack/panel-stack.json` defines the common pin map, pad geometry and mechanical stack: 19.99 mm fully mated, 20.45 mm maximum and ~20.0 mm nominal support spacing. Standoffs/support hardware, not the connectors, must carry structural load. + +Current fabrication-format outputs are in `fab/` and `radian_panel-fab.zip`; current reports are in `reports/native/`. They are engineering outputs. Real connector seating, enclosure tolerances, support hardware, power/load/thermal/fault behaviour and hardware bring-up remain first-article checks. + +## Mechanical integration +The reference enclosure CAD is synchronized to the two-row layout: three large primary knob references, three smaller FX knob references, MODE on its original raised insert, shifted mainboard/support planes and Samtec body envelopes. Independent validation reports zero control-hole conflicts, zero panel-component/mainboard clashes and zero Samtec body-envelope overlap. Physical first-article tolerance/retention remains required. diff --git a/hardware/panel/reports/cad_export_checks.json b/hardware/panel/reports/cad_export_checks.json new file mode 100644 index 0000000..5cf7fd1 --- /dev/null +++ b/hardware/panel/reports/cad_export_checks.json @@ -0,0 +1,8 @@ +{ + "fit_template_watertight": true, + "fit_template_winding_consistent": true, + "fit_template_positive_volume": true, + "note": "Bare PCB mechanical template, not a fabrication approval or a conductive PCB.", + "bare_board_step_reimport_valid": true, + "bare_board_step_solid_count": 1 +} \ No newline at end of file diff --git a/hardware/panel/reports/cad_fit_checks.json b/hardware/panel/reports/cad_fit_checks.json new file mode 100644 index 0000000..cdfa00a --- /dev/null +++ b/hardware/panel/reports/cad_fit_checks.json @@ -0,0 +1,35 @@ +{ + "scope": "Reference-envelope CAD only. No manufacturer STEP or component lead-form certification. Zero nominal intersections is not fit approval.", + "board_valid": true, + "board_solids": 1, + "board_bounds_mm": [ + 18.0, + 10.0, + -9.6, + 198.5, + 118.0, + -8.0 + ], + "component_reference_count": 69, + "body_only_mechanical_checks": { + "positive_volume_intersections": [], + "exclusions": [ + "leads, solder fillets, cables, fastener threads, torques and inserted plugs", + "DIN support is retained as a provisional bracket; its socket retention without the former carrier PCB is not validated", + "generic mating headers are separately bounded, not exact purchased assemblies" + ] + }, + "reference_parts_valid": true, + "mainboard_modified": false, + "native_KiCad_3D_import": "NOT RUN; local model alignments require native 3D viewer validation", + "assumed_16mm_panel_header_envelope_vs_mainboard": [], + "desktop_dock_geometry": "unchanged from Rev F.1; inlet cutout, strain relief and feet remain provisional", + "panel_changes": [ + "two new M2.5 clearance holes at 24,14 and 55,14", + "6.6 mm mode-switch bore in existing raised insert", + "existing shaft and jack locations retained" + ], + "board_bounds_method": "OCCT AddOptimal without triangulation, avoids conservative meshed bounding-box inflation", + "status": "HISTORICAL PRE-DIRECT-STACK FIT STUDY", + "superseded_by": "case_direct_stack_update.json" +} diff --git a/hardware/panel/reports/case_changed_solid_fit.json b/hardware/panel/reports/case_changed_solid_fit.json new file mode 100644 index 0000000..bf8af02 --- /dev/null +++ b/hardware/panel/reports/case_changed_solid_fit.json @@ -0,0 +1,91 @@ +{ + "pairs": [ + { + "a": "MAINBOARD_REPAIRED", + "b": "rear_guard", + "volume_mm3": 0.0 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "desktop_dock", + "volume_mm3": 0.0 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "panel", + "volume_mm3": 0.0 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "reverb_insert", + "volume_mm3": 0.0 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "corner_support_BL", + "volume_mm3": 11.592476891746346 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "corner_support_BR", + "volume_mm3": 11.592476891746337 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "corner_support_TL", + "volume_mm3": 11.592476891746342 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "corner_support_TR", + "volume_mm3": 11.592476891746365 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "spacers_reference", + "volume_mm3": 92.5377493721202 + }, + { + "a": "RV4_body", + "b": "rear_guard", + "volume_mm3": 0.0 + }, + { + "a": "RV4_body", + "b": "desktop_dock", + "volume_mm3": 0.0 + }, + { + "a": "RV5_body", + "b": "rear_guard", + "volume_mm3": 0.0 + }, + { + "a": "RV5_body", + "b": "desktop_dock", + "volume_mm3": 0.0 + }, + { + "a": "RV6_body", + "b": "rear_guard", + "volume_mm3": 0.0 + }, + { + "a": "RV6_body", + "b": "desktop_dock", + "volume_mm3": 0.0 + }, + { + "a": "SW1_body", + "b": "rear_guard", + "volume_mm3": 0.0 + }, + { + "a": "SW1_body", + "b": "desktop_dock", + "volume_mm3": 0.0 + } + ], + "unintended_positive_volume_intersections": [], + "changed_case_solid_fit": "pass" +} diff --git a/hardware/panel/reports/case_direct_stack_update.json b/hardware/panel/reports/case_direct_stack_update.json new file mode 100644 index 0000000..61d44cc --- /dev/null +++ b/hardware/panel/reports/case_direct_stack_update.json @@ -0,0 +1,234 @@ +{ + "revision": "CASE-P3-TWO-ROW", + "source_case": "cad/RADIAN_P1_case_legacy_reference.step", + "stack_revision": "STACK-P2", + "mainboard_shift_forward_mm": 0.46000000000000085, + "panel_to_mainboard_pcb_gap_mm": 19.99, + "samtec": { + "main": "IPT1-110-06-L-D", + "panel": "IPS1-110-01-L-D", + "fully_mated_gap_mm": 19.99, + "max_gap_mm": 20.45, + "support_target_mm": 20.0 + }, + "front_panel": { + "old_macro_holes_closed": [ + [ + 42, + 84 + ], + [ + 80, + 84 + ], + [ + 118, + 84 + ] + ], + "primary_large_knob_centers": [ + [ + 38, + 96 + ], + [ + 76, + 96 + ], + [ + 114, + 96 + ] + ], + "fx_small_knob_centers": [ + [ + 66, + 70 + ], + [ + 88, + 70 + ], + [ + 110, + 70 + ] + ], + "pot_hole_diameter_mm": 6.8, + "primary_knob_diameter_mm": 23.0, + "fx_knob_diameter_mm": 14.0, + "mode_center": [ + 150.5, + 84.5 + ], + "mode_hole_diameter_mm": 6.6, + "mode_insert_role": "MODE" + }, + "supports": { + "front_support_rear_z_mm": -29.54, + "rear_spacer_front_z_mm": -31.14, + "rear_guard_unchanged": true + }, + "validation": { + "panel_valid": true, + "mode_insert_valid": true, + "panel_bbox_mm": [ + -0.0, + -0.0, + 0.0, + 202.8, + 128.5, + 2.0 + ], + "mainboard_bbox_mm": [ + 8.0, + 14.25, + -32.31, + 168.0, + 114.25, + -13.45 + ], + "support_zmin_mm": -29.54, + "rear_spacer_zmax_mm": -31.14, + "pcb_gap_mm": 19.99, + "target_gap_mm": 19.99, + "control_enclosure_intersection_mm3": { + "RV1": 0.0, + "RV2": 0.0, + "RV3": 0.0, + "RV4": 0.0, + "RV5": 0.0, + "RV6": 0.0, + "SW1_bushing": 0.0, + "SW1_shaft": 0.0 + }, + "panel_component_vs_mainboard_clashes": [], + "samtec_nominal_geometric_insertion_mm": 3.82, + "samtec_geometric_insertion_at_max_gap_mm": 3.36, + "samtec_fully_mated_wipe_mm": 0.84, + "samtec_min_wipe_at_max_gap_mm": 0.38, + "samtec_housing_ref_rounding_depth_mm": 0.01, + "samtec_reference_models": [ + { + "id": "A", + "panel_model_z": [ + -18.11, + -7.06 + ], + "main_model_z": [ + -31.94, + -14.29 + ], + "solid_overlap_mm3": 0.3430395, + "solid_overlap_z_mm": 0.01 + }, + { + "id": "B", + "panel_model_z": [ + -18.11, + -7.06 + ], + "main_model_z": [ + -31.94, + -14.29 + ], + "solid_overlap_mm3": 0.3430395, + "solid_overlap_z_mm": 0.01 + } + ], + "changed_enclosure_intersections": [ + { + "a": "MAINBOARD_REPAIRED", + "b": "rear_guard", + "volume_mm3": 0.0 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "desktop_dock", + "volume_mm3": 0.0 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "panel", + "volume_mm3": 0.0 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "mode_blank", + "volume_mm3": 0.0 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "corner_support_BL", + "volume_mm3": 8.1726962 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "corner_support_BR", + "volume_mm3": 8.1726962 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "corner_support_TL", + "volume_mm3": 8.1726962 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "corner_support_TR", + "volume_mm3": 8.1726962 + }, + { + "a": "MAINBOARD_REPAIRED", + "b": "spacers_reference", + "volume_mm3": 0.0 + }, + { + "a": "RV4_body", + "b": "rear_guard", + "volume_mm3": 0.0 + }, + { + "a": "RV4_body", + "b": "desktop_dock", + "volume_mm3": 0.0 + }, + { + "a": "RV5_body", + "b": "rear_guard", + "volume_mm3": 0.0 + }, + { + "a": "RV5_body", + "b": "desktop_dock", + "volume_mm3": 0.0 + }, + { + "a": "RV6_body", + "b": "rear_guard", + "volume_mm3": 0.0 + }, + { + "a": "RV6_body", + "b": "desktop_dock", + "volume_mm3": 0.0 + }, + { + "a": "SW1_body", + "b": "rear_guard", + "volume_mm3": 0.0 + }, + { + "a": "SW1_body", + "b": "desktop_dock", + "volume_mm3": 0.0 + } + ], + "changed_enclosure_unintended_intersections": [] + }, + "limitations": [ + "Samtec connector solids are drawing-derived reference models, not Samtec-supplied STEP downloads", + "connector insertion/retention forces and case tolerances require first-article validation", + "0.01 mm nominal housing-plane overlap comes from rounded REF dimensions in the Samtec prints", + "knob/nut/washer stack remains reference geometry" + ] +} diff --git a/hardware/panel/reports/case_export_validation.json b/hardware/panel/reports/case_export_validation.json new file mode 100644 index 0000000..db25203 --- /dev/null +++ b/hardware/panel/reports/case_export_validation.json @@ -0,0 +1,75 @@ +{ + "assembly_children": 163, + "missing_required": [], + "panel_bbox_mm": [ + -0.0, + -0.0, + 0.0, + 202.8, + 128.5, + 2.0 + ], + "reverb_insert_bbox_mm": [ + 139.0, + 71.0, + 2.0, + 162.0, + 98.0, + 4.0 + ], + "mainboard_bbox_mm": [ + 8.0, + 14.25, + -32.805, + 168.0, + 114.25, + -20.965 + ], + "spacers_bbox_mm": [ + 9.535898, + 16.25, + -39.6, + 166.464102, + 112.25, + -31.14 + ], + "corner_support_bboxes_mm": { + "corner_support_BL": [ + 6.0, + 12.25, + -29.54, + 15.6, + 21.85, + 0.0 + ], + "corner_support_BR": [ + 160.4, + 12.25, + -29.54, + 170.0, + 21.85, + 0.0 + ], + "corner_support_TL": [ + 6.0, + 106.65, + -29.54, + 15.6, + 116.25, + 0.0 + ], + "corner_support_TR": [ + 160.4, + 106.65, + -29.54, + 170.0, + 116.25, + 0.0 + ] + }, + "exact_faceplate_thickness_pass": true, + "exact_insert_thickness_pass": true, + "required_current_parts_present": true, + "obsolete_panel_harness_models": [], + "roundtrip_step_load": "pass" +} diff --git a/hardware/panel/reports/electrical_geometry_checks.json b/hardware/panel/reports/electrical_geometry_checks.json new file mode 100644 index 0000000..ff7d5bb --- /dev/null +++ b/hardware/panel/reports/electrical_geometry_checks.json @@ -0,0 +1,150 @@ +{ + "scope": "Custom nominal pad/track/via geometry and exact design graph, NOT native KiCad ERC/DRC, not thermal/signal integrity/manufacturing approval", + "components": 69, + "pads": 201, + "nets": 43, + "tracks": 682, + "vias": 34, + "routed_length_mm": 1352.767216927618, + "minimum_rule_mm": 0.2, + "copper_edge_rule_mm": 0.3, + "copper_clearance_violations": [], + "copper_edge_violations": [], + "disconnected_non_ground_nets": {}, + "ground_status": "Inner GND zone definitions provided. Native KiCad refill required; GND connectivity is not claimed by this test.", + "native_erc": "NOT RUN", + "native_drc": "NOT RUN", + "bench_tests": "NOT RUN", + "power_budget": "3 A IC target only; system capability not verified", + "mainboard_pin_crosscheck": { + "checked": 45, + "mismatches": [] + }, + "native_pcb_pin_net_crosscheck": { + "footprints": 69, + "mismatches": [] + }, + "syntax": { + "design/service.kicad_sch": { + "balanced": true, + "duplicate_uuids": [] + }, + "design/io.kicad_sch": { + "balanced": true, + "duplicate_uuids": [] + }, + "design/controls.kicad_sch": { + "balanced": true, + "duplicate_uuids": [] + }, + "design/power.kicad_sch": { + "balanced": true, + "duplicate_uuids": [] + }, + "design/radian_panel.kicad_sch": { + "balanced": true, + "duplicate_uuids": [] + }, + "design/mod.kicad_sch": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/SW_PUSH_6x6_P6.5x4.5.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/Header_1x05_P2.54.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/IDC_2x05_P2.54_Shrouded.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/Bourns_PEC11R4_RearFacing_Switch.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/SOT23_BAT54S.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/C_1210.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/TestPoint_D2.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/TI_DDC0006A_SOT23_6.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/WQP518MA_PJ398SM_Vertical.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/D_SMB.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/Bourns_PTV09A4_RearFacing.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/R_0603.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/C_0603.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/LED_D3.0_P2.54.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/C_0805.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/E_Switch_100SP_M2.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/Header_1x03_P2.54.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/Header_1x02_P2.54.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/Fuse_1206.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/Bourns_SRP7050TA.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/Header_1x06_P2.54.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.pretty/SOIC8_3.9x4.9_P1.27.kicad_mod": { + "balanced": true, + "duplicate_uuids": [] + }, + "library/RadianPanel.kicad_sym": { + "balanced": true, + "duplicate_uuids": [] + }, + "design/radian_panel.kicad_pcb": { + "balanced": true, + "duplicate_uuids": [] + } + }, + "custom_checks_pass": true +} \ No newline at end of file diff --git a/hardware/panel/reports/ideal_dc_checks.json b/hardware/panel/reports/ideal_dc_checks.json new file mode 100644 index 0000000..79cae14 --- /dev/null +++ b/hardware/panel/reports/ideal_dc_checks.json @@ -0,0 +1,18 @@ +{ + "model": "Ideal DC resistor network only. Not SPICE, no op-amp macro-model, no switching converter transient simulation. Monte Carlo assumes independent uniform resistor errors +/-0.1%.", + "mod_nominal_gain": 0.5, + "mod_nominal_zero_V": 2.5, + "gain_range_sampled": [ + 0.49890855317664606, + 0.5010418984472397 + ], + "zero_range_sampled_V": [ + 2.4956032418541674, + 2.504215590481196 + ], + "rail_endpoint_warning": "Nominal -5/+5 V maps to supply rails: real output swing and loading reduce usable endpoint range. Calibrate/limit firmware range.", + "power_feedback_nominal_V": 5.0794391278195485, + "power_EN_at_VRAW_11V": 1.875, + "inductor_ripple_nominal_A_at_VIN12": 0.732345160012716, + "input_power_formula": "I_RACK = (Vout * Iout)/(VIN * converter_efficiency) + housekeeping; unknown actual FPGA load and efficiency" +} \ No newline at end of file diff --git a/hardware/panel/reports/native/cad b/hardware/panel/reports/native/cad new file mode 120000 index 0000000..b34d67a --- /dev/null +++ b/hardware/panel/reports/native/cad @@ -0,0 +1 @@ +/home/ik/ChatGPT/Courant/hardware/panel/cad \ No newline at end of file diff --git a/hardware/panel/reports/native/drc-actual-models-final.json b/hardware/panel/reports/native/drc-actual-models-final.json new file mode 100644 index 0000000..ae98c76 --- /dev/null +++ b/hardware/panel/reports/native/drc-actual-models-final.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T16:13:19", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "radian_panel.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/panel/reports/native/drc-actual-models.json b/hardware/panel/reports/native/drc-actual-models.json new file mode 100644 index 0000000..445b9f7 --- /dev/null +++ b/hardware/panel/reports/native/drc-actual-models.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T07:47:31", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "radian_panel.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/panel/reports/native/drc-current.json b/hardware/panel/reports/native/drc-current.json new file mode 100644 index 0000000..7aac47d --- /dev/null +++ b/hardware/panel/reports/native/drc-current.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T04:00:24", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "radian_panel.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/panel/reports/native/drc.json b/hardware/panel/reports/native/drc.json new file mode 100644 index 0000000..3d5a365 --- /dev/null +++ b/hardware/panel/reports/native/drc.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T16:13:13", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "radian_panel.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/panel/reports/native/erc.json b/hardware/panel/reports/native/erc.json new file mode 100644 index 0000000..9652160 --- /dev/null +++ b/hardware/panel/reports/native/erc.json @@ -0,0 +1,62 @@ +{ + "$schema": "https://schemas.kicad.org/erc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T16:13:11", + "ignored_checks": [ + { + "description": "Global label only appears once in the schematic", + "key": "single_global_label" + }, + { + "description": "Four connection points are joined together", + "key": "four_way_junction" + }, + { + "description": "SPICE model issue", + "key": "simulation_model_issue" + }, + { + "description": "Assigned footprint doesn't match footprint filters", + "key": "footprint_filter" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "sheets": [ + { + "path": "/", + "uuid_path": "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276", + "violations": [] + }, + { + "path": "/01 | POWER INPUTS AND 5 V CONVERTER/", + "uuid_path": "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/fd872eb1-5f1f-55eb-8327-3584154f3e1b", + "violations": [] + }, + { + "path": "/02 | FRONT-PANEL CONTROLS/", + "uuid_path": "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/fe425aa9-89e9-5e5b-9592-3f1bdae47718", + "violations": [] + }, + { + "path": "/03 | PATCH JACKS AND MIDI/", + "uuid_path": "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/1578ecd5-bea0-5ad2-8ccb-a84196c400b8", + "violations": [] + }, + { + "path": "/04 | OPTIONAL BIPOLAR MODULATION/", + "uuid_path": "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/a353e908-e1f3-5887-a37d-be1463de1afa", + "violations": [] + }, + { + "path": "/05 | INTERNAL SERVICE ACCESS/", + "uuid_path": "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/dd60d741-95e3-5383-9836-1c68c07ca20b", + "violations": [] + } + ], + "source": "radian_panel.kicad_sch" +} diff --git a/hardware/panel/reports/native/exact_connector_drc.json b/hardware/panel/reports/native/exact_connector_drc.json new file mode 100644 index 0000000..eaa7bd8 --- /dev/null +++ b/hardware/panel/reports/native/exact_connector_drc.json @@ -0,0 +1,1725 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-17T22:51:03", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "radian_panel.kicad_pcb", + "unconnected_items": [ + { + "description": "Missing connection between items", + "items": [ + { + "description": "Track [GND] on F.Cu, length 1.3500 mm", + "pos": { + "x": 23.0, + "y": 93.85 + }, + "uuid": "98bff87d-d3e9-57c6-99dd-06c3c43e6f6a" + }, + { + "description": "Pad 2 [GND] of C5 on F.Cu", + "pos": { + "x": 29.0, + "y": 93.85 + }, + "uuid": "c8e5f242-17c0-5122-ba9d-ae1593ba0bec" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Track [GND] on B.Cu, length 1.5000 mm", + "pos": { + "x": 25.0, + "y": 86.5 + }, + "uuid": "55b2c2ea-201b-5a94-a683-1cea8b0775ad" + }, + { + "description": "Track [GND] on F.Cu, length 1.3500 mm", + "pos": { + "x": 23.0, + "y": 93.85 + }, + "uuid": "98bff87d-d3e9-57c6-99dd-06c3c43e6f6a" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 2 [GND] of J201", + "pos": { + "x": 24.73, + "y": 76.5 + }, + "uuid": "53bd8df4-532d-57e2-9af8-c7df65542fb7" + }, + { + "description": "Track [GND] on F.Cu, length 1.7000 mm", + "pos": { + "x": 27.7, + "y": 82.5 + }, + "uuid": "987f1649-dde8-57fd-bb7f-15c73c08fe17" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Track [GND] on F.Cu, length 1.7000 mm", + "pos": { + "x": 27.7, + "y": 82.5 + }, + "uuid": "987f1649-dde8-57fd-bb7f-15c73c08fe17" + }, + { + "description": "Track [GND] on B.Cu, length 1.5000 mm", + "pos": { + "x": 25.0, + "y": 86.5 + }, + "uuid": "55b2c2ea-201b-5a94-a683-1cea8b0775ad" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Track [GND] on F.Cu, length 1.4000 mm", + "pos": { + "x": 29.0, + "y": 93.85 + }, + "uuid": "4b12afa2-0947-522c-b356-15577017588f" + }, + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 33.0, + "y": 101.75 + }, + "uuid": "2850be29-8357-5910-866d-e0b1d98c7b1e" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 1 [GND] of J101", + "pos": { + "x": 31.57, + "y": 57.52 + }, + "uuid": "b1f82d71-d391-4cfd-8809-d38cd9cfb41e" + }, + { + "description": "PTH pad 1 [GND] of RV1", + "pos": { + "x": 31.5, + "y": 51.5 + }, + "uuid": "90bc9d97-3906-5fe7-b585-9ada504d78ff" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Track [GND] on F.Cu, length 1.0028 mm", + "pos": { + "x": 32.0, + "y": 107.825 + }, + "uuid": "eb763fb5-4bda-5978-bc1f-8f12f9d8fadb" + }, + { + "description": "Track [GND] on F.Cu, length 1.3500 mm", + "pos": { + "x": 32.65, + "y": 110.5 + }, + "uuid": "7f49c367-4ef6-56f1-b2d7-730e1711b834" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Track [GND] on F.Cu, length 0.8062 mm", + "pos": { + "x": 32.9, + "y": 102.55 + }, + "uuid": "f1ccdd78-4f3e-5fa9-9bba-bc0a4f989bba" + }, + { + "description": "Track [GND] on F.Cu, length 1.0028 mm", + "pos": { + "x": 32.0, + "y": 107.825 + }, + "uuid": "109ab12b-7a76-5557-ab8a-fb35f250b7c5" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Track [GND] on F.Cu, length 1.3500 mm", + "pos": { + "x": 32.65, + "y": 110.5 + }, + "uuid": "7f49c367-4ef6-56f1-b2d7-730e1711b834" + }, + { + "description": "Track [GND] on F.Cu, length 0.9250 mm", + "pos": { + "x": 39.825, + "y": 108.5 + }, + "uuid": "f987cc8e-8abe-596d-8a50-1bb5de95351f" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 3 [GND] of J101", + "pos": { + "x": 34.11, + "y": 57.52 + }, + "uuid": "550ddc10-07d9-4441-b2ba-25129b39c6a8" + }, + { + "description": "PTH pad 1 [GND] of J101", + "pos": { + "x": 31.57, + "y": 57.52 + }, + "uuid": "b1f82d71-d391-4cfd-8809-d38cd9cfb41e" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 3 [GND] of J101", + "pos": { + "x": 34.11, + "y": 57.52 + }, + "uuid": "550ddc10-07d9-4441-b2ba-25129b39c6a8" + }, + { + "description": "PTH pad 12 [GND] of J101", + "pos": { + "x": 44.27, + "y": 54.98 + }, + "uuid": "debd9ea7-4de3-435f-8952-26f04949deb3" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Track [GND] on F.Cu, length 0.9250 mm", + "pos": { + "x": 39.825, + "y": 108.5 + }, + "uuid": "f987cc8e-8abe-596d-8a50-1bb5de95351f" + }, + { + "description": "Track [GND] on F.Cu, length 0.9250 mm", + "pos": { + "x": 43.825, + "y": 109.5 + }, + "uuid": "acc33809-4cc2-543c-ac23-c2b3bc1f4392" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad C [GND] of ENC1", + "pos": { + "x": 42.0, + "y": 93.0 + }, + "uuid": "225d33c3-ecf1-5399-a6f5-23647d3299c2" + }, + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 33.0, + "y": 101.75 + }, + "uuid": "2850be29-8357-5910-866d-e0b1d98c7b1e" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad C [GND] of ENC1", + "pos": { + "x": 42.0, + "y": 93.0 + }, + "uuid": "225d33c3-ecf1-5399-a6f5-23647d3299c2" + }, + { + "description": "PTH pad S2 [GND] of ENC1", + "pos": { + "x": 44.5, + "y": 78.5 + }, + "uuid": "35c66f09-8cf4-55ee-b54b-6edb8502405b" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 12 [GND] of J101", + "pos": { + "x": 44.27, + "y": 54.98 + }, + "uuid": "debd9ea7-4de3-435f-8952-26f04949deb3" + }, + { + "description": "PTH pad 1 [GND] of RV2", + "pos": { + "x": 55.5, + "y": 51.5 + }, + "uuid": "ed6dc7db-8434-538e-965c-b0778931ac3b" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 12 [GND] of J101", + "pos": { + "x": 44.27, + "y": 54.98 + }, + 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"type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 3 [GND] of J200", + "pos": { + "x": 175.27, + "y": 61.96 + }, + "uuid": "9aeb3ef7-1a4b-5864-bcbb-13584709607c" + }, + { + "description": "PTH pad 1 [GND] of J302", + "pos": { + "x": 186.5, + "y": 53.98 + }, + "uuid": "6f40fd61-8332-507e-a300-d21c3db2b3a7" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 7 [GND] of J200", + "pos": { + "x": 175.27, + "y": 67.04 + }, + "uuid": "77a53efe-c9c4-56c8-88ca-06aedb6ffd8b" + }, + { + "description": "PTH pad 5 [GND] of J200", + "pos": { + "x": 175.27, + "y": 64.5 + }, + "uuid": "75506622-9ad3-51e1-b8c8-a01f705ee9d4" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 7 [GND] of J200", + "pos": { + "x": 175.27, + "y": 67.04 + }, + "uuid": "77a53efe-c9c4-56c8-88ca-06aedb6ffd8b" + }, + { + "description": "PTH pad 2 [GND] of J303", + "pos": { + "x": 186.5, + "y": 68.88 + }, + "uuid": "79028a46-6c74-5d8f-8f37-f104fb1ee5cd" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 1 [GND] of J301", + "pos": { + "x": 186.5, + "y": 35.98 + }, + "uuid": "55f6746f-d57c-5074-addc-a73a868feb6e" + }, + { + "description": "PTH pad 2 [GND] of J301", + "pos": { + "x": 186.5, + "y": 32.88 + }, + "uuid": "5830b651-5ed2-55fd-ae72-263db09b72ea" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 2 [GND] of J302", + "pos": { + "x": 186.5, + "y": 50.88 + }, + "uuid": "26f4cc92-8c14-500c-aebf-8787b00ea6b1" + }, + { + "description": "PTH pad 1 [GND] of J301", + "pos": { + "x": 186.5, + "y": 35.98 + }, + "uuid": "55f6746f-d57c-5074-addc-a73a868feb6e" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 1 [GND] of J302", + "pos": { + "x": 186.5, + "y": 53.98 + }, + "uuid": "6f40fd61-8332-507e-a300-d21c3db2b3a7" + }, + { + "description": "PTH pad 2 [GND] of J302", + "pos": { + "x": 186.5, + "y": 50.88 + }, + "uuid": "26f4cc92-8c14-500c-aebf-8787b00ea6b1" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 1 [GND] of J303", + "pos": { + "x": 186.5, + "y": 71.98 + }, + "uuid": "fd42b66f-2939-5145-81e7-c7c8ff6f3abc" + }, + { + "description": "PTH pad 2 [GND] of J303", + "pos": { + "x": 186.5, + "y": 68.88 + }, + "uuid": "79028a46-6c74-5d8f-8f37-f104fb1ee5cd" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 1 [GND] of J304", + "pos": { + "x": 186.5, + "y": 89.98 + }, + "uuid": "85c140b7-f863-57ac-a52b-f4d7ff4253a0" + }, + { + "description": "PTH pad 1 [GND] of J303", + "pos": { + "x": 186.5, + "y": 71.98 + }, + "uuid": "fd42b66f-2939-5145-81e7-c7c8ff6f3abc" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 1 [GND] of J305", + "pos": { + "x": 186.5, + "y": 107.98 + }, + "uuid": "6b24d02c-f921-57c6-95e7-21266a8a4dd1" + }, + { + "description": "PTH pad 1 [GND] of J304", + "pos": { + "x": 186.5, + "y": 89.98 + }, + "uuid": "85c140b7-f863-57ac-a52b-f4d7ff4253a0" + } + ], + "severity": "error", + "type": "unconnected_items" + } + ], + "violations": [ + { + "description": "Footprint 'Stack_2x10_P2.54' does not match copy in library 'RadianPanel'", + "items": [ + { + "description": "Footprint J101", + "pos": { + "x": 43.0, + "y": 56.25 + }, + "uuid": "3e8349d7-9e13-4614-b7fa-7c0ef1916f30" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'Stack_2x10_P2.54' does not match copy in library 'RadianPanel'", + "items": [ + { + "description": "Footprint J100", + "pos": { + "x": 124.0, + "y": 66.75 + }, + "uuid": "bd9e6adc-d8f4-47d3-980d-022846ac4a6a" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 33.0, + "y": 107.75 + }, + "uuid": "011369dc-5c47-5613-80ec-436d6dc52ff3" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 151.0, + "y": 54.5 + }, + "uuid": "0512e428-0912-5b65-a852-9e95b423ceeb" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 158.75, + "y": 59.5 + }, + "uuid": "0d151662-4acb-501d-aafd-74b9e19374a3" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 23.0, + "y": 95.25 + }, + "uuid": "227a5f44-c540-596b-a4dd-c19b702f807b" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 33.0, + "y": 101.75 + }, + "uuid": "2850be29-8357-5910-866d-e0b1d98c7b1e" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 148.25, + "y": 64.25 + }, + "uuid": "30c3014c-3d7c-57fc-bb56-c41c0f5fd8e9" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 26.0, + "y": 82.5 + }, + "uuid": "394f0034-2e5b-5798-b64d-0a2176dc87c7" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 29.0, + "y": 95.25 + }, + "uuid": "4010d834-7de7-5aac-8cc3-07084a3cdcde" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 34.0, + "y": 110.5 + }, + "uuid": "42ecc953-7b7a-5e5b-9128-96979fb6b79f" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 29.0, + "y": 92.5 + }, + "uuid": "52480cc3-3c3e-5a18-81e7-3689acbb39d2" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 29.5, + "y": 82.5 + }, + "uuid": "7c149561-4126-5580-b62b-a40a4f5ce0c3" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 40.75, + "y": 108.5 + }, + "uuid": "8022085a-b9a9-5ed5-b098-fd454de20099" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 165.0, + "y": 61.75 + }, + "uuid": "9e32d5cc-b5ff-5218-b556-8ac155ad7d3c" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 43.25, + "y": 69.5 + }, + "uuid": "a33d23bd-ca7b-5528-a7c3-33655a76a919" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 31.25, + "y": 110.5 + }, + "uuid": "a4f2b060-5b43-58c7-8011-a5598b7afed1" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 23.0, + "y": 92.5 + }, + "uuid": "a5a88657-62cd-5c4e-bc05-d26c28d4c7ac" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 165.75, + "y": 57.5 + }, + "uuid": "ab722d3c-3389-57cc-8339-8e31576da960" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 31.0, + "y": 107.75 + }, + "uuid": "b4ce75e1-f075-5b9b-95fd-ca29c4bcdea4" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 44.75, + "y": 109.5 + }, + "uuid": "c83d9e44-3145-50ae-a0a0-444bb35ace87" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 31.75, + "y": 102.5 + }, + "uuid": "cdf0229f-f000-58a2-a2ac-72213062eb4c" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 46.0, + "y": 69.5 + }, + "uuid": "e435273a-e153-5254-8b1d-bad4ae575fa2" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 23.5, + "y": 86.5 + }, + "uuid": "e7253e3f-5683-5d9c-a281-123196d62e77" + } + ], + "severity": "warning", + "type": "via_dangling" + }, + { + "description": "Via is not connected or connected on only one layer", + "items": [ + { + "description": "Via [GND] on F.Cu - B.Cu", + "pos": { + "x": 161.25, + "y": 71.5 + }, + "uuid": "e9bbe84f-6aba-590c-b6d9-c58472d1b7dd" + } + ], + "severity": "warning", + "type": "via_dangling" + } + ] +} diff --git a/hardware/panel/reports/native/exact_connector_erc.json b/hardware/panel/reports/native/exact_connector_erc.json new file mode 100644 index 0000000..1132d44 --- /dev/null +++ b/hardware/panel/reports/native/exact_connector_erc.json @@ -0,0 +1,62 @@ +{ + "$schema": "https://schemas.kicad.org/erc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-17T22:51:04", + "ignored_checks": [ + { + "description": "Global label only appears once in the schematic", + "key": "single_global_label" + }, + { + "description": "Four connection points are joined together", + "key": "four_way_junction" + }, + { + "description": "SPICE model issue", + "key": "simulation_model_issue" + }, + { + "description": "Assigned footprint doesn't match footprint filters", + "key": "footprint_filter" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "sheets": [ + { + "path": "/", + "uuid_path": "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276", + "violations": [] + }, + { + "path": "/01 | POWER INPUTS AND 5 V CONVERTER/", + "uuid_path": "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/fd872eb1-5f1f-55eb-8327-3584154f3e1b", + "violations": [] + }, + { + "path": "/02 | FRONT-PANEL CONTROLS/", + "uuid_path": "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/fe425aa9-89e9-5e5b-9592-3f1bdae47718", + "violations": [] + }, + { + "path": "/03 | PATCH JACKS AND MIDI/", + "uuid_path": "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/1578ecd5-bea0-5ad2-8ccb-a84196c400b8", + "violations": [] + }, + { + "path": "/04 | OPTIONAL BIPOLAR MODULATION/", + "uuid_path": "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/a353e908-e1f3-5887-a37d-be1463de1afa", + "violations": [] + }, + { + "path": "/05 | INTERNAL SERVICE ACCESS/", + "uuid_path": "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/dd60d741-95e3-5383-9836-1c68c07ca20b", + "violations": [] + } + ], + "source": "radian_panel.kicad_sch" +} diff --git a/hardware/panel/reports/native/exact_connector_final_drc.json b/hardware/panel/reports/native/exact_connector_final_drc.json new file mode 100644 index 0000000..e078f47 --- /dev/null +++ b/hardware/panel/reports/native/exact_connector_final_drc.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-17T22:54:31", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "radian_panel.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/panel/reports/native/exact_connector_netlist.xml b/hardware/panel/reports/native/exact_connector_netlist.xml new file mode 100644 index 0000000..a47b74c --- /dev/null +++ b/hardware/panel/reports/native/exact_connector_netlist.xml @@ -0,0 +1,3101 @@ + + + + /home/ik/ChatGPT/Courant/hardware/panel/design/radian_panel.kicad_sch + 2026-09-18T06:03:45 + Eeschema 10.0.6-1.fc44 + + + RADIAN | SINGLE PANEL / INTERFACE PCB + + P1 DRAFT + 2026-09-15 + radian_panel.kicad_sch + + + + + + + + + + + + + + 01 | POWER INPUTS AND 5 V CONVERTER + + P1 DRAFT + 2026-09-15 + power.kicad_sch + + + + + + + + + + + + + + 02 | FRONT-PANEL CONTROLS + + P1 DRAFT + 2026-09-15 + controls.kicad_sch + + + + + + + + + + + + + + 03 | PATCH JACKS AND MIDI + + P1 DRAFT + 2026-09-15 + io.kicad_sch + + + + + + + + + + + + + + 04 | OPTIONAL BIPOLAR MODULATION + + P1 DRAFT + 2026-09-15 + mod.kicad_sch + + + + + + + + + + + + + + 05 | INTERNAL SERVICE ACCESS + + P1 DRAFT + 2026-09-15 + service.kicad_sch + + + + + + + + + + + + + + + 10uF + RadianPanel:C_1210 + 50V X7R; verify effective capacitance at DC bias + + SELECT 10uF 50V X7R 1210 + + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + e235e9e9-27d8-5bc5-9979-aa61676bbb5e + + + + + + + + + + + 100nF + RadianPanel:C_0603 + 50V X7R; verify effective capacitance at DC bias + + SELECT 100nF 50V X7R 0603 + + RadianPanel:C_0603 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + f0dfa655-1c0e-52c4-8e96-ff7485b903fa + + + + + + + + + + + 100nF + RadianPanel:C_0603 + 16V X7R; verify effective capacitance at DC bias + + SELECT 100nF 16V X7R 0603 + + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + 9d21645e-6e9c-5499-9690-93108325ef0e + + + + + + + + + + + 22uF + RadianPanel:C_1210 + 25V X7R; verify effective capacitance at DC bias + + SELECT 22uF 25V X7R 1210 + + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + 6e2ec867-0c4b-5305-84d8-cdacb8e45221 + + + + + + + + + + + 22uF + RadianPanel:C_1210 + 25V X7R; verify effective capacitance at DC bias + + SELECT 22uF 25V X7R 1210 + + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + fe6c420e-f8ee-519a-9963-1ced568e4ce0 + + + + + + + + + + + 75pF + RadianPanel:C_0603 + 50V C0G; verify effective capacitance at DC bias + + SELECT 75pF 50V C0G 0603 + + RadianPanel:C_0603 + + 50V C0G; verify effective capacitance at DC bias + + + + + + + + 659e71f7-093e-5d1c-89c4-9d3cd026407d + + + + + + + + + + + 10uF + RadianPanel:C_1210 + 50V X7R; verify effective capacitance at DC bias + + SELECT 10uF 50V X7R 1210 + + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + 4a089892-03db-5c15-98b2-fdc052063e20 + + + + + + + + + + + SS54 / OR + RadianPanel:D_SMB + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + SS54-E3/57T + Vishay + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + + + + + + + 2491e415-d4d3-5f05-adc4-96f2585667c3 + + + + + + + + + + + SS54 / OR + RadianPanel:D_SMB + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + SS54-E3/57T + Vishay + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + + + + + + + 22451254-ce41-55ee-8e90-c20756e02fe9 + + + + + + + + + + + SMBJ15A + RadianPanel:D_SMB + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + + SMBJ15A-E3/52 + Vishay + RadianPanel:D_SMB + + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + + + + + + + + e3db311e-a848-59dd-b0da-759dab706442 + + + + + + + + + + + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + SELECT 2 A >=32 V 1206 fuse + + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + cf3fecca-7a96-5152-8905-52011939431b + + + + + + + + + + + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + SELECT 2 A >=32 V 1206 fuse + + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + 2c15d3f7-621c-571d-bae0-d9bc20f3166d + + + + + + + + + + + 61201021621 + RadianPanel:Wurth_61201021621_Exact_B + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + 61201021621 + + RadianPanel:Wurth_61201021621_Exact_B + + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + + + + + + + 22b1fffe-abd6-5915-b500-c63f9c0cc768 + + + + + + + + + + + + + + + + + + + 22-27-2021 + RadianPanel:Molex_22-27-2021_J201_B + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + 22-27-2021 + + RadianPanel:Molex_22-27-2021_J201_B + + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + + + + + + + a47c0ef6-62da-55f1-9de0-f66bd495a11a + + + + + + + + + + + 10uH 4A / Isat7.5A + RadianPanel:Bourns_SRP7050TA + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + + SRP7050TA-100M + Bourns + RadianPanel:Bourns_SRP7050TA + + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + + + + + + + + cf417c35-4329-5b7a-949c-57d34d609287 + + + + + + + + + + + 100k + RadianPanel:R_0603 + Resistor 1% + + SELECT 100k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + e06fed5c-7bac-525d-a94d-7c4fb1b320ac + + + + + + + + + + + 13.3k + RadianPanel:R_0603 + Resistor 1% + + SELECT 13.3k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + 1ed808a6-f40e-5015-9e0e-5d2f703996c9 + + + + + + + + + + + 511k + RadianPanel:R_0603 + Resistor 1% + + SELECT 511k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + 9c543196-dbb2-5183-8db6-93df2d3af013 + + + + + + + + + + + 105k + RadianPanel:R_0603 + Resistor 1% + + SELECT 105k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + a7ef9d11-82b6-59ca-b368-2f515d0c5c24 + + + + + + + + + + + 49.9 + RadianPanel:R_0603 + Resistor 1% + + SELECT 49.9 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + cb3d6d3e-3504-5797-b2cb-7095c94b674c + + + + + + + + + + + GND + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 30e5f418-53cd-5bd6-83da-5313e82697f5 + + + + + + + + + + VIN5 + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 6efe25b9-68ef-56d7-aaa2-7cb82610ed50 + + + + + + + + + + VRAW + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + bfc78a37-02e3-5618-a8bf-e2932365b2e3 + + + + + + + + + + TPS54302DDCR + RadianPanel:TI_DDC0006A_SOT23_6 + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + + TPS54302DDCR + Texas Instruments + RadianPanel:TI_DDC0006A_SOT23_6 + + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + + + + + + + + d5d17bcd-d73f-574d-ad30-191a495b187f + + + + + + + + + + + + + + + VOICE 1 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + fe276ab0-ff85-5ab2-898b-ed8075966655 + + + + + + + + + + + VOICE 2 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + b36d9fe8-1d28-5e73-9188-b569959c7a35 + + + + + + + + + + + VOICE 3 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + 8581a420-1ba2-5d16-a609-c9a592c237c5 + + + + + + + + + + + VOICE 4 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + cb84da0a-7689-587d-8688-e97d2e4c3449 + + + + + + + + + + + 24 PPR / PUSH + RadianPanel:Bourns_PEC11R4_RearFacing_Switch + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + + PEC11R-4220F-S0024 + Bourns + RadianPanel:Bourns_PEC11R4_RearFacing_Switch + + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + + + + + + + + 82881ed2-d2b6-51a6-9dad-cffbe9d62def + + + + + + + + + + + + + + + + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + IPS1-110-01-L-D + Samtec + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + + + + + + + 8d29a3b6-4dc8-5d80-8428-86e24030d339 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10k linear / TENSION + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + 7509de8e-e60c-5e1e-9ec3-c1c2df981adc + + + + + + + + + + + + + + 10k linear / DECAY + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + feaf009e-cdb0-5dd4-a19f-e89862601cfb + + + + + + + + + + + + + + 10k linear / CHAOS + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + 6050cafe-321e-5010-9ad6-cdd72088f2d6 + + + + + + + + + + + + + + 10k linear / DRIVE + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + cb6c0109-b436-5916-be99-c5b95f57a16b + + + + + + + + + + + + + + 10k linear / DELAY + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + a77ff7f6-ae92-50bd-b28b-442cd55be9b6 + + + + + + + + + + + + + + 10k linear / REVERB + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + 0849b9e4-ac33-55b8-87e2-939f457734af + + + + + + + + + + + + + + MODE / SPDT ON-ON + RadianPanel:E_Switch_100SP_M2 + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + + 100SP1T1B1M2REH + E-Switch + RadianPanel:E_Switch_100SP_M2 + + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + + + + + + + + f5afaab2-c860-5fc4-9b76-5a05e19eaa7a + + + + + + + + + + + + PITCH 0-5V + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + 1d1426a6-6ee9-5869-8b4b-7ecb976e988e + + + + + + + + + + + + MOD + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + c1806fec-6f4c-552c-ac14-80ec675f5a36 + + + + + + + + + + + + GATE + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + be78fd5a-3121-50f1-a6c8-33469a59e66e + + + + + + + + + + + + LINE L + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + 20a12c22-8872-522b-8afe-80cd0acffe87 + + + + + + + + + + + + LINE R + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + 39bd0795-f68c-5b3f-83ac-033c8b0bcb76 + + + + + + + + + + + + 22-27-2021 + RadianPanel:Molex_22-27-2021_J306_B + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + 22-27-2021 + + RadianPanel:Molex_22-27-2021_J306_B + + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + + + + + + + f536e084-c6a1-57ea-8653-b1afeea3b2ff + + + + + + + + + + + 100nF + RadianPanel:C_0603 + 16V X7R; verify effective capacitance at DC bias + + SELECT 100nF 16V X7R 0603 + + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + 60f3a6c1-6f01-5457-bd28-d2f52e211c96 + + + + + + + + + + + 1uF + RadianPanel:C_0805 + 16V X7R; verify effective capacitance at DC bias + + SELECT 1uF 16V X7R 0805 + + RadianPanel:C_0805 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + 9b8308d0-0230-537b-ac42-dd90818e7824 + + + + + + + + + + + BAT54S + RadianPanel:SOT23_BAT54S + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + + BAT54S,215 + Nexperia + RadianPanel:SOT23_BAT54S + + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + + + + + + + + 0a9cb6cd-78cb-5760-9975-5324be4a7a45 + + + + + + + + + + + + 450301014042 + RadianPanel:Wurth_450301014042_Exact_B + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + 450301014042 + + RadianPanel:Wurth_450301014042_Exact_B + + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + + + + + + + 7a1dc449-3659-51a2-b518-7001903ac8ef + + + + + + + + + + + + 200k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 200k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 4f0fc251-9961-5f36-90aa-92cff98b7d48 + + + + + + + + + + + 100k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 100k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 8186e4ec-ba27-5931-9775-980ea06efde9 + + + + + + + + + + + 200k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 200k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 86815e7d-c360-516d-afff-46eb3b0d64c0 + + + + + + + + + + + 10k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 10k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 45109df0-d108-5e40-988e-420c2d961340 + + + + + + + + + + + 10k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 10k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 5a1e97fe-608e-588b-abb0-73dfd93ea8dd + + + + + + + + + + + VREF25 + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 9a57579e-c67c-5118-aa2a-a9574281fbeb + + + + + + + + + + MOD_BIPOLAR + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 2d0eae80-797a-549c-a27f-4473fbcee434 + + + + + + + + + + OPA2192ID + RadianPanel:SOIC8_3.9x4.9_P1.27 + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + + OPA2192ID + Texas Instruments + RadianPanel:SOIC8_3.9x4.9_P1.27 + + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + + + + + + + + 76da6519-7887-5b94-ad4a-2323d80f01ec + + + + + + + + + + + + + + + + + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + IPS1-110-01-L-D + Samtec + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + + + + + + + 37c3ba3a-67a8-53b0-9b31-8f009dd72af4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 22-27-2061 + RadianPanel:Molex_22-27-2061_J202_B + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + 22-27-2061 + + RadianPanel:Molex_22-27-2061_J202_B + + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + + + + + + + 6e352fab-9100-5920-bc40-ba528cdf06e9 + + + + + + + + + + + + + + + PROGRAM / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + Internal service push button, accessible after module removal. + + B3F-1000 + Omron + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + Internal service push button, accessible after module removal. + + + + + + + + 6ac8d041-74b6-51e1-b114-8a9f2fd7723c + + + + + + + + + + + RESET / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + B3F-1000 + Omron + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + + + + + + + + + ac438e8b-9f2d-50a4-ab02-b0bd7ac6245f + + + + + + + + + + + + + 50V X7R; verify effective capacitance at DC bias + + C + 10uF + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + + 50V X7R; verify effective capacitance at DC bias + + C + 100nF + RadianPanel:C_0603 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + + 16V X7R; verify effective capacitance at DC bias + + C + 100nF + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + + 16V X7R; verify effective capacitance at DC bias + + C + 1uF + RadianPanel:C_0805 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + + 16V X7R; verify effective capacitance at DC bias + + C + 100nF + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + + 25V X7R; verify effective capacitance at DC bias + + C + 22uF + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + + 25V X7R; verify effective capacitance at DC bias + + C + 22uF + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + + 50V C0G; verify effective capacitance at DC bias + + C + 75pF + RadianPanel:C_0603 + + 50V C0G; verify effective capacitance at DC bias + + + + + + + + + 50V X7R; verify effective capacitance at DC bias + + C + 10uF + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + D + SS54 / OR + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + Vishay + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 1 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 2 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 3 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 4 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + D + SS54 / OR + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + Vishay + + + + + + + + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + + D + SMBJ15A + RadianPanel:D_SMB + + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + Vishay + + + + + + + + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + + D + BAT54S + RadianPanel:SOT23_BAT54S + + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + Nexperia + + + + + + + + + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + + ENC + 24 PPR / PUSH + RadianPanel:Bourns_PEC11R4_RearFacing_Switch + + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + Bourns + + + + + + + + + + + + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + F + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + F + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + J + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + Samtec + + + + + + + + + + + + + + + + + + + + + + + + + + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + J + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + Samtec + + + + + + + + + + + + + + + + + + + + + + + + + + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + J + 61201021621 + RadianPanel:Wurth_61201021621_Exact_B + + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + + + + + + + + + + + + + + + + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + J + 22-27-2021 + RadianPanel:Molex_22-27-2021_J201_B + + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + + + + + + + + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + J + 22-27-2061 + RadianPanel:Molex_22-27-2061_J202_B + + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + + + + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + PITCH 0-5V + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + MOD + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + GATE + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + LINE L + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + LINE R + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + J + 22-27-2021 + RadianPanel:Molex_22-27-2021_J306_B + + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + + + + + + + + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + JP + 450301014042 + RadianPanel:Wurth_450301014042_Exact_B + + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + + + + + + + + + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + + L + 10uH 4A / Isat7.5A + RadianPanel:Bourns_SRP7050TA + + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + Bourns + + + + + + + + Resistor 1% + + R + 100k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 1% + + R + 13.3k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 0.1% + + R + 200k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 100k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 200k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 10k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 10k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 1% + + R + 511k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 1% + + R + 105k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 1% + + R + 49.9 + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / TENSION + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / DECAY + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / CHAOS + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / DRIVE + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / DELAY + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / REVERB + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + + SW + MODE / SPDT ON-ON + RadianPanel:E_Switch_100SP_M2 + + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + E-Switch + + + + + + + + + Internal service push button, accessible after module removal. + + SW + PROGRAM / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + Internal service push button, accessible after module removal. + Omron + + + + + + + + + SW + RESET / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + + Omron + + + + + + + + Exposed soldermask aperture, no component. + + TP + GND + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + VIN5 + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + VRAW + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + VREF25 + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + MOD_BIPOLAR + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + + U + TPS54302DDCR + RadianPanel:TI_DDC0006A_SOT23_6 + + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + Texas Instruments + + + + + + + + + + + + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + + U + OPA2192ID + RadianPanel:SOIC8_3.9x4.9_P1.27 + + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + Texas Instruments + + + + + + + + + + + + + + + + ${KIPRJMOD}/../library/RadianPanel.kicad_sym + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/panel/reports/native/exact_connector_normalized_drc.json b/hardware/panel/reports/native/exact_connector_normalized_drc.json new file mode 100644 index 0000000..f117c0a --- /dev/null +++ b/hardware/panel/reports/native/exact_connector_normalized_drc.json @@ -0,0 +1,68 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-17T22:53:25", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "radian_panel.kicad_pcb", + "unconnected_items": [], + "violations": [ + { + "description": "Footprint 'Stack_2x10_P2.54' does not match copy in library 'RadianPanel'", + "items": [ + { + "description": "Footprint J101", + "pos": { + "x": 43.0, + "y": 56.25 + }, + "uuid": "3c304775-2f0b-47c3-9bcb-e54ca711f4bc" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'Stack_2x10_P2.54' does not match copy in library 'RadianPanel'", + "items": [ + { + "description": "Footprint J100", + "pos": { + "x": 124.0, + "y": 66.75 + }, + "uuid": "7732cd51-570b-4aea-a358-6e21f15b0877" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + } + ] +} diff --git a/hardware/panel/reports/native/exact_connector_refill_drc.json b/hardware/panel/reports/native/exact_connector_refill_drc.json new file mode 100644 index 0000000..0b9ca9c --- /dev/null +++ b/hardware/panel/reports/native/exact_connector_refill_drc.json @@ -0,0 +1,68 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-17T22:52:27", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "radian_panel.kicad_pcb", + "unconnected_items": [], + "violations": [ + { + "description": "Footprint 'Stack_2x10_P2.54' does not match copy in library 'RadianPanel'", + "items": [ + { + "description": "Footprint J101", + "pos": { + "x": 43.0, + "y": 56.25 + }, + "uuid": "3c304775-2f0b-47c3-9bcb-e54ca711f4bc" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + }, + { + "description": "Footprint 'Stack_2x10_P2.54' does not match copy in library 'RadianPanel'", + "items": [ + { + "description": "Footprint J100", + "pos": { + "x": 124.0, + "y": 66.75 + }, + "uuid": "7732cd51-570b-4aea-a358-6e21f15b0877" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + } + ] +} diff --git a/hardware/panel/reports/native/library b/hardware/panel/reports/native/library new file mode 120000 index 0000000..aa280ac --- /dev/null +++ b/hardware/panel/reports/native/library @@ -0,0 +1 @@ +/home/ik/ChatGPT/Courant/hardware/panel/library \ No newline at end of file diff --git a/hardware/panel/reports/native/netlist.xml b/hardware/panel/reports/native/netlist.xml new file mode 100644 index 0000000..423d1dc --- /dev/null +++ b/hardware/panel/reports/native/netlist.xml @@ -0,0 +1,3101 @@ + + + + /home/ik/ChatGPT/Courant/hardware/panel/design/radian_panel.kicad_sch + 2026-09-18T16:13:14 + Eeschema 10.0.6-1.fc44 + + + RADIAN | SINGLE PANEL / INTERFACE PCB + + P1 DRAFT + 2026-09-15 + radian_panel.kicad_sch + + + + + + + + + + + + + + 01 | POWER INPUTS AND 5 V CONVERTER + + P1 DRAFT + 2026-09-15 + power.kicad_sch + + + + + + + + + + + + + + 02 | FRONT-PANEL CONTROLS + + P1 DRAFT + 2026-09-15 + controls.kicad_sch + + + + + + + + + + + + + + 03 | PATCH JACKS AND MIDI + + P1 DRAFT + 2026-09-15 + io.kicad_sch + + + + + + + + + + + + + + 04 | OPTIONAL BIPOLAR MODULATION + + P1 DRAFT + 2026-09-15 + mod.kicad_sch + + + + + + + + + + + + + + 05 | INTERNAL SERVICE ACCESS + + P1 DRAFT + 2026-09-15 + service.kicad_sch + + + + + + + + + + + + + + + 10uF + RadianPanel:C_1210 + 50V X7R; verify effective capacitance at DC bias + + SELECT 10uF 50V X7R 1210 + + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + e235e9e9-27d8-5bc5-9979-aa61676bbb5e + + + + + + + + + + + 100nF + RadianPanel:C_0603 + 50V X7R; verify effective capacitance at DC bias + + SELECT 100nF 50V X7R 0603 + + RadianPanel:C_0603 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + f0dfa655-1c0e-52c4-8e96-ff7485b903fa + + + + + + + + + + + 100nF + RadianPanel:C_0603 + 16V X7R; verify effective capacitance at DC bias + + SELECT 100nF 16V X7R 0603 + + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + 9d21645e-6e9c-5499-9690-93108325ef0e + + + + + + + + + + + 22uF + RadianPanel:C_1210 + 25V X7R; verify effective capacitance at DC bias + + SELECT 22uF 25V X7R 1210 + + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + 6e2ec867-0c4b-5305-84d8-cdacb8e45221 + + + + + + + + + + + 22uF + RadianPanel:C_1210 + 25V X7R; verify effective capacitance at DC bias + + SELECT 22uF 25V X7R 1210 + + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + fe6c420e-f8ee-519a-9963-1ced568e4ce0 + + + + + + + + + + + 75pF + RadianPanel:C_0603 + 50V C0G; verify effective capacitance at DC bias + + SELECT 75pF 50V C0G 0603 + + RadianPanel:C_0603 + + 50V C0G; verify effective capacitance at DC bias + + + + + + + + 659e71f7-093e-5d1c-89c4-9d3cd026407d + + + + + + + + + + + 10uF + RadianPanel:C_1210 + 50V X7R; verify effective capacitance at DC bias + + SELECT 10uF 50V X7R 1210 + + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + 4a089892-03db-5c15-98b2-fdc052063e20 + + + + + + + + + + + SS54 / OR + RadianPanel:D_SMB + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + SS54-E3/57T + Vishay + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + + + + + + + 2491e415-d4d3-5f05-adc4-96f2585667c3 + + + + + + + + + + + SS54 / OR + RadianPanel:D_SMB + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + SS54-E3/57T + Vishay + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + + + + + + + 22451254-ce41-55ee-8e90-c20756e02fe9 + + + + + + + + + + + SMBJ15A + RadianPanel:D_SMB + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + + SMBJ15A-E3/52 + Vishay + RadianPanel:D_SMB + + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + + + + + + + + e3db311e-a848-59dd-b0da-759dab706442 + + + + + + + + + + + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + SELECT 2 A >=32 V 1206 fuse + + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + cf3fecca-7a96-5152-8905-52011939431b + + + + + + + + + + + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + SELECT 2 A >=32 V 1206 fuse + + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + 2c15d3f7-621c-571d-bae0-d9bc20f3166d + + + + + + + + + + + 61201021621 + RadianPanel:Wurth_61201021621_Exact_B + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + 61201021621 + + RadianPanel:Wurth_61201021621_Exact_B + + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + + + + + + + 22b1fffe-abd6-5915-b500-c63f9c0cc768 + + + + + + + + + + + + + + + + + + + 22-27-2021 + RadianPanel:Molex_22-27-2021_J201_B + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + 22-27-2021 + + RadianPanel:Molex_22-27-2021_J201_B + + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + + + + + + + a47c0ef6-62da-55f1-9de0-f66bd495a11a + + + + + + + + + + + 10uH 4A / Isat7.5A + RadianPanel:Bourns_SRP7050TA + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + + SRP7050TA-100M + Bourns + RadianPanel:Bourns_SRP7050TA + + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + + + + + + + + cf417c35-4329-5b7a-949c-57d34d609287 + + + + + + + + + + + 100k + RadianPanel:R_0603 + Resistor 1% + + SELECT 100k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + e06fed5c-7bac-525d-a94d-7c4fb1b320ac + + + + + + + + + + + 13.3k + RadianPanel:R_0603 + Resistor 1% + + SELECT 13.3k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + 1ed808a6-f40e-5015-9e0e-5d2f703996c9 + + + + + + + + + + + 511k + RadianPanel:R_0603 + Resistor 1% + + SELECT 511k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + 9c543196-dbb2-5183-8db6-93df2d3af013 + + + + + + + + + + + 105k + RadianPanel:R_0603 + Resistor 1% + + SELECT 105k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + a7ef9d11-82b6-59ca-b368-2f515d0c5c24 + + + + + + + + + + + 49.9 + RadianPanel:R_0603 + Resistor 1% + + SELECT 49.9 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + cb3d6d3e-3504-5797-b2cb-7095c94b674c + + + + + + + + + + + GND + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 30e5f418-53cd-5bd6-83da-5313e82697f5 + + + + + + + + + + VIN5 + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 6efe25b9-68ef-56d7-aaa2-7cb82610ed50 + + + + + + + + + + VRAW + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + bfc78a37-02e3-5618-a8bf-e2932365b2e3 + + + + + + + + + + TPS54302DDCR + RadianPanel:TI_DDC0006A_SOT23_6 + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + + TPS54302DDCR + Texas Instruments + RadianPanel:TI_DDC0006A_SOT23_6 + + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + + + + + + + + d5d17bcd-d73f-574d-ad30-191a495b187f + + + + + + + + + + + + + + + VOICE 1 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + fe276ab0-ff85-5ab2-898b-ed8075966655 + + + + + + + + + + + VOICE 2 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + b36d9fe8-1d28-5e73-9188-b569959c7a35 + + + + + + + + + + + VOICE 3 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + 8581a420-1ba2-5d16-a609-c9a592c237c5 + + + + + + + + + + + VOICE 4 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + cb84da0a-7689-587d-8688-e97d2e4c3449 + + + + + + + + + + + 24 PPR / PUSH + RadianPanel:Bourns_PEC11R4_RearFacing_Switch + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + + PEC11R-4220F-S0024 + Bourns + RadianPanel:Bourns_PEC11R4_RearFacing_Switch + + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + + + + + + + + 82881ed2-d2b6-51a6-9dad-cffbe9d62def + + + + + + + + + + + + + + + + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + IPS1-110-01-L-D + Samtec + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + + + + + + + 8d29a3b6-4dc8-5d80-8428-86e24030d339 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10k linear / TENSION + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + 7509de8e-e60c-5e1e-9ec3-c1c2df981adc + + + + + + + + + + + + + + 10k linear / DECAY + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + feaf009e-cdb0-5dd4-a19f-e89862601cfb + + + + + + + + + + + + + + 10k linear / CHAOS + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + 6050cafe-321e-5010-9ad6-cdd72088f2d6 + + + + + + + + + + + + + + 10k linear / DRIVE + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + cb6c0109-b436-5916-be99-c5b95f57a16b + + + + + + + + + + + + + + 10k linear / DELAY + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + a77ff7f6-ae92-50bd-b28b-442cd55be9b6 + + + + + + + + + + + + + + 10k linear / REVERB + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + 0849b9e4-ac33-55b8-87e2-939f457734af + + + + + + + + + + + + + + MODE / SPDT ON-ON + RadianPanel:E_Switch_100SP_M2 + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + + 100SP1T1B1M2REH + E-Switch + RadianPanel:E_Switch_100SP_M2 + + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + + + + + + + + f5afaab2-c860-5fc4-9b76-5a05e19eaa7a + + + + + + + + + + + + PITCH 0-5V + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + 1d1426a6-6ee9-5869-8b4b-7ecb976e988e + + + + + + + + + + + + MOD + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + c1806fec-6f4c-552c-ac14-80ec675f5a36 + + + + + + + + + + + + GATE + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + be78fd5a-3121-50f1-a6c8-33469a59e66e + + + + + + + + + + + + LINE L + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + 20a12c22-8872-522b-8afe-80cd0acffe87 + + + + + + + + + + + + LINE R + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + 39bd0795-f68c-5b3f-83ac-033c8b0bcb76 + + + + + + + + + + + + 22-27-2021 + RadianPanel:Molex_22-27-2021_J306_B + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + 22-27-2021 + + RadianPanel:Molex_22-27-2021_J306_B + + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + + + + + + + f536e084-c6a1-57ea-8653-b1afeea3b2ff + + + + + + + + + + + 100nF + RadianPanel:C_0603 + 16V X7R; verify effective capacitance at DC bias + + SELECT 100nF 16V X7R 0603 + + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + 60f3a6c1-6f01-5457-bd28-d2f52e211c96 + + + + + + + + + + + 1uF + RadianPanel:C_0805 + 16V X7R; verify effective capacitance at DC bias + + SELECT 1uF 16V X7R 0805 + + RadianPanel:C_0805 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + 9b8308d0-0230-537b-ac42-dd90818e7824 + + + + + + + + + + + BAT54S + RadianPanel:SOT23_BAT54S + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + + BAT54S,215 + Nexperia + RadianPanel:SOT23_BAT54S + + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + + + + + + + + 0a9cb6cd-78cb-5760-9975-5324be4a7a45 + + + + + + + + + + + + 450301014042 + RadianPanel:Wurth_450301014042_Exact_B + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + 450301014042 + + RadianPanel:Wurth_450301014042_Exact_B + + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + + + + + + + 7a1dc449-3659-51a2-b518-7001903ac8ef + + + + + + + + + + + + 200k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 200k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 4f0fc251-9961-5f36-90aa-92cff98b7d48 + + + + + + + + + + + 100k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 100k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 8186e4ec-ba27-5931-9775-980ea06efde9 + + + + + + + + + + + 200k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 200k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 86815e7d-c360-516d-afff-46eb3b0d64c0 + + + + + + + + + + + 10k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 10k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 45109df0-d108-5e40-988e-420c2d961340 + + + + + + + + + + + 10k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 10k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 5a1e97fe-608e-588b-abb0-73dfd93ea8dd + + + + + + + + + + + VREF25 + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 9a57579e-c67c-5118-aa2a-a9574281fbeb + + + + + + + + + + MOD_BIPOLAR + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 2d0eae80-797a-549c-a27f-4473fbcee434 + + + + + + + + + + OPA2192ID + RadianPanel:SOIC8_3.9x4.9_P1.27 + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + + OPA2192ID + Texas Instruments + RadianPanel:SOIC8_3.9x4.9_P1.27 + + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + + + + + + + + 76da6519-7887-5b94-ad4a-2323d80f01ec + + + + + + + + + + + + + + + + + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + IPS1-110-01-L-D + Samtec + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + + + + + + + 37c3ba3a-67a8-53b0-9b31-8f009dd72af4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 22-27-2061 + RadianPanel:Molex_22-27-2061_J202_B + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + 22-27-2061 + + RadianPanel:Molex_22-27-2061_J202_B + + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + + + + + + + 6e352fab-9100-5920-bc40-ba528cdf06e9 + + + + + + + + + + + + + + + PROGRAM / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + Internal service push button, accessible after module removal. + + B3F-1000 + Omron + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + Internal service push button, accessible after module removal. + + + + + + + + 6ac8d041-74b6-51e1-b114-8a9f2fd7723c + + + + + + + + + + + RESET / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + B3F-1000 + Omron + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + + + + + + + + + ac438e8b-9f2d-50a4-ab02-b0bd7ac6245f + + + + + + + + + + + + + 50V X7R; verify effective capacitance at DC bias + + C + 10uF + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + + 50V X7R; verify effective capacitance at DC bias + + C + 100nF + RadianPanel:C_0603 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + + 16V X7R; verify effective capacitance at DC bias + + C + 100nF + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + + 16V X7R; verify effective capacitance at DC bias + + C + 1uF + RadianPanel:C_0805 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + + 16V X7R; verify effective capacitance at DC bias + + C + 100nF + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + + 25V X7R; verify effective capacitance at DC bias + + C + 22uF + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + + 25V X7R; verify effective capacitance at DC bias + + C + 22uF + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + + 50V C0G; verify effective capacitance at DC bias + + C + 75pF + RadianPanel:C_0603 + + 50V C0G; verify effective capacitance at DC bias + + + + + + + + + 50V X7R; verify effective capacitance at DC bias + + C + 10uF + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + D + SS54 / OR + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + Vishay + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 1 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 2 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 3 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 4 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + D + SS54 / OR + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + Vishay + + + + + + + + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + + D + SMBJ15A + RadianPanel:D_SMB + + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + Vishay + + + + + + + + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + + D + BAT54S + RadianPanel:SOT23_BAT54S + + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + Nexperia + + + + + + + + + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + + ENC + 24 PPR / PUSH + RadianPanel:Bourns_PEC11R4_RearFacing_Switch + + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + Bourns + + + + + + + + + + + + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + F + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + F + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + J + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + Samtec + + + + + + + + + + + + + + + + + + + + + + + + + + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + J + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + Samtec + + + + + + + + + + + + + + + + + + + + + + + + + + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + J + 61201021621 + RadianPanel:Wurth_61201021621_Exact_B + + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + + + + + + + + + + + + + + + + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + J + 22-27-2021 + RadianPanel:Molex_22-27-2021_J201_B + + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + + + + + + + + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + J + 22-27-2061 + RadianPanel:Molex_22-27-2061_J202_B + + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + + + + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + PITCH 0-5V + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + MOD + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + GATE + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + LINE L + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + LINE R + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + J + 22-27-2021 + RadianPanel:Molex_22-27-2021_J306_B + + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + + + + + + + + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + JP + 450301014042 + RadianPanel:Wurth_450301014042_Exact_B + + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + + + + + + + + + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + + L + 10uH 4A / Isat7.5A + RadianPanel:Bourns_SRP7050TA + + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + Bourns + + + + + + + + Resistor 1% + + R + 100k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 1% + + R + 13.3k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 0.1% + + R + 200k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 100k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 200k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 10k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 10k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 1% + + R + 511k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 1% + + R + 105k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 1% + + R + 49.9 + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / TENSION + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / DECAY + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / CHAOS + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / DRIVE + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / DELAY + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / REVERB + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + + SW + MODE / SPDT ON-ON + RadianPanel:E_Switch_100SP_M2 + + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + E-Switch + + + + + + + + + Internal service push button, accessible after module removal. + + SW + PROGRAM / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + Internal service push button, accessible after module removal. + Omron + + + + + + + + + SW + RESET / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + + Omron + + + + + + + + Exposed soldermask aperture, no component. + + TP + GND + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + VIN5 + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + VRAW + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + VREF25 + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + MOD_BIPOLAR + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + + U + TPS54302DDCR + RadianPanel:TI_DDC0006A_SOT23_6 + + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + Texas Instruments + + + + + + + + + + + + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + + U + OPA2192ID + RadianPanel:SOIC8_3.9x4.9_P1.27 + + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + Texas Instruments + + + + + + + + + + + + + + + + ${KIPRJMOD}/../library/RadianPanel.kicad_sym + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/panel/reports/native/panel_netlist.xml b/hardware/panel/reports/native/panel_netlist.xml new file mode 100644 index 0000000..5b693c3 --- /dev/null +++ b/hardware/panel/reports/native/panel_netlist.xml @@ -0,0 +1,3101 @@ + + + + /home/ik/ChatGPT/Courant/hardware/panel/design/radian_panel.kicad_sch + 2026-09-18T05:50:37 + Eeschema 10.0.6-1.fc44 + + + RADIAN | SINGLE PANEL / INTERFACE PCB + + P1 DRAFT + 2026-09-15 + radian_panel.kicad_sch + + + + + + + + + + + + + + 01 | POWER INPUTS AND 5 V CONVERTER + + P1 DRAFT + 2026-09-15 + power.kicad_sch + + + + + + + + + + + + + + 02 | FRONT-PANEL CONTROLS + + P1 DRAFT + 2026-09-15 + controls.kicad_sch + + + + + + + + + + + + + + 03 | PATCH JACKS AND MIDI + + P1 DRAFT + 2026-09-15 + io.kicad_sch + + + + + + + + + + + + + + 04 | OPTIONAL BIPOLAR MODULATION + + P1 DRAFT + 2026-09-15 + mod.kicad_sch + + + + + + + + + + + + + + 05 | INTERNAL SERVICE ACCESS + + P1 DRAFT + 2026-09-15 + service.kicad_sch + + + + + + + + + + + + + + + 10uF + RadianPanel:C_1210 + 50V X7R; verify effective capacitance at DC bias + + SELECT 10uF 50V X7R 1210 + + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + e235e9e9-27d8-5bc5-9979-aa61676bbb5e + + + + + + + + + + + 100nF + RadianPanel:C_0603 + 50V X7R; verify effective capacitance at DC bias + + SELECT 100nF 50V X7R 0603 + + RadianPanel:C_0603 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + f0dfa655-1c0e-52c4-8e96-ff7485b903fa + + + + + + + + + + + 100nF + RadianPanel:C_0603 + 16V X7R; verify effective capacitance at DC bias + + SELECT 100nF 16V X7R 0603 + + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + 9d21645e-6e9c-5499-9690-93108325ef0e + + + + + + + + + + + 22uF + RadianPanel:C_1210 + 25V X7R; verify effective capacitance at DC bias + + SELECT 22uF 25V X7R 1210 + + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + 6e2ec867-0c4b-5305-84d8-cdacb8e45221 + + + + + + + + + + + 22uF + RadianPanel:C_1210 + 25V X7R; verify effective capacitance at DC bias + + SELECT 22uF 25V X7R 1210 + + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + fe6c420e-f8ee-519a-9963-1ced568e4ce0 + + + + + + + + + + + 75pF + RadianPanel:C_0603 + 50V C0G; verify effective capacitance at DC bias + + SELECT 75pF 50V C0G 0603 + + RadianPanel:C_0603 + + 50V C0G; verify effective capacitance at DC bias + + + + + + + + 659e71f7-093e-5d1c-89c4-9d3cd026407d + + + + + + + + + + + 10uF + RadianPanel:C_1210 + 50V X7R; verify effective capacitance at DC bias + + SELECT 10uF 50V X7R 1210 + + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + 4a089892-03db-5c15-98b2-fdc052063e20 + + + + + + + + + + + SS54 / OR + RadianPanel:D_SMB + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + SS54-E3/57T + Vishay + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + + + + + + + 2491e415-d4d3-5f05-adc4-96f2585667c3 + + + + + + + + + + + SS54 / OR + RadianPanel:D_SMB + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + SS54-E3/57T + Vishay + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + + + + + + + 22451254-ce41-55ee-8e90-c20756e02fe9 + + + + + + + + + + + SMBJ15A + RadianPanel:D_SMB + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + + SMBJ15A-E3/52 + Vishay + RadianPanel:D_SMB + + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + + + + + + + + e3db311e-a848-59dd-b0da-759dab706442 + + + + + + + + + + + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + SELECT 2 A >=32 V 1206 fuse + + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + cf3fecca-7a96-5152-8905-52011939431b + + + + + + + + + + + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + SELECT 2 A >=32 V 1206 fuse + + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + 2c15d3f7-621c-571d-bae0-d9bc20f3166d + + + + + + + + + + + 61201021621 + RadianPanel:Wurth_61201021621_Exact_B + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + 61201021621 + + RadianPanel:Wurth_61201021621_Exact_B + + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + + + + + + + 22b1fffe-abd6-5915-b500-c63f9c0cc768 + + + + + + + + + + + + + + + + + + + 22-27-2021 + RadianPanel:Molex_22-27-2021_J201_B + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + 22-27-2021 + + RadianPanel:Molex_22-27-2021_J201_B + + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + + + + + + + a47c0ef6-62da-55f1-9de0-f66bd495a11a + + + + + + + + + + + 10uH 4A / Isat7.5A + RadianPanel:Bourns_SRP7050TA + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + + SRP7050TA-100M + Bourns + RadianPanel:Bourns_SRP7050TA + + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + + + + + + + + cf417c35-4329-5b7a-949c-57d34d609287 + + + + + + + + + + + 100k + RadianPanel:R_0603 + Resistor 1% + + SELECT 100k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + e06fed5c-7bac-525d-a94d-7c4fb1b320ac + + + + + + + + + + + 13.3k + RadianPanel:R_0603 + Resistor 1% + + SELECT 13.3k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + 1ed808a6-f40e-5015-9e0e-5d2f703996c9 + + + + + + + + + + + 511k + RadianPanel:R_0603 + Resistor 1% + + SELECT 511k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + 9c543196-dbb2-5183-8db6-93df2d3af013 + + + + + + + + + + + 105k + RadianPanel:R_0603 + Resistor 1% + + SELECT 105k 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + a7ef9d11-82b6-59ca-b368-2f515d0c5c24 + + + + + + + + + + + 49.9 + RadianPanel:R_0603 + Resistor 1% + + SELECT 49.9 1% 0603 + + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + cb3d6d3e-3504-5797-b2cb-7095c94b674c + + + + + + + + + + + GND + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 30e5f418-53cd-5bd6-83da-5313e82697f5 + + + + + + + + + + VIN5 + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 6efe25b9-68ef-56d7-aaa2-7cb82610ed50 + + + + + + + + + + VRAW + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + bfc78a37-02e3-5618-a8bf-e2932365b2e3 + + + + + + + + + + TPS54302DDCR + RadianPanel:TI_DDC0006A_SOT23_6 + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + + TPS54302DDCR + Texas Instruments + RadianPanel:TI_DDC0006A_SOT23_6 + + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + + + + + + + + d5d17bcd-d73f-574d-ad30-191a495b187f + + + + + + + + + + + + + + + VOICE 1 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + fe276ab0-ff85-5ab2-898b-ed8075966655 + + + + + + + + + + + VOICE 2 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + b36d9fe8-1d28-5e73-9188-b569959c7a35 + + + + + + + + + + + VOICE 3 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + 8581a420-1ba2-5d16-a609-c9a592c237c5 + + + + + + + + + + + VOICE 4 + RadianPanel:LED_D3.0_P2.54 + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + L-934GD + Kingbright + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + + + + + + + cb84da0a-7689-587d-8688-e97d2e4c3449 + + + + + + + + + + + 24 PPR / PUSH + RadianPanel:Bourns_PEC11R4_RearFacing_Switch + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + + PEC11R-4220F-S0024 + Bourns + RadianPanel:Bourns_PEC11R4_RearFacing_Switch + + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + + + + + + + + 82881ed2-d2b6-51a6-9dad-cffbe9d62def + + + + + + + + + + + + + + + + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + IPS1-110-01-L-D + Samtec + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + + + + + + + 8d29a3b6-4dc8-5d80-8428-86e24030d339 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10k linear / TENSION + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + 7509de8e-e60c-5e1e-9ec3-c1c2df981adc + + + + + + + + + + + + + + 10k linear / DECAY + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + feaf009e-cdb0-5dd4-a19f-e89862601cfb + + + + + + + + + + + + + + 10k linear / CHAOS + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + 6050cafe-321e-5010-9ad6-cdd72088f2d6 + + + + + + + + + + + + + + 10k linear / DRIVE + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + cb6c0109-b436-5916-be99-c5b95f57a16b + + + + + + + + + + + + + + 10k linear / DELAY + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + a77ff7f6-ae92-50bd-b28b-442cd55be9b6 + + + + + + + + + + + + + + 10k linear / REVERB + RadianPanel:Bourns_PTV09A4_RearFacing + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + PTV09A-4020F-B103 + Bourns + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + + + + + + + 0849b9e4-ac33-55b8-87e2-939f457734af + + + + + + + + + + + + + + MODE / SPDT ON-ON + RadianPanel:E_Switch_100SP_M2 + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + + 100SP1T1B1M2REH + E-Switch + RadianPanel:E_Switch_100SP_M2 + + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + + + + + + + + f5afaab2-c860-5fc4-9b76-5a05e19eaa7a + + + + + + + + + + + + PITCH 0-5V + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + 1d1426a6-6ee9-5869-8b4b-7ecb976e988e + + + + + + + + + + + + MOD + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + c1806fec-6f4c-552c-ac14-80ec675f5a36 + + + + + + + + + + + + GATE + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + be78fd5a-3121-50f1-a6c8-33469a59e66e + + + + + + + + + + + + LINE L + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + 20a12c22-8872-522b-8afe-80cd0acffe87 + + + + + + + + + + + + LINE R + RadianPanel:WQP518MA_PJ398SM_Vertical + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + WQP518MA (Thonkiconn/PJ398SM) + QingPu / Thonk + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + + + + + + + 39bd0795-f68c-5b3f-83ac-033c8b0bcb76 + + + + + + + + + + + + 22-27-2021 + RadianPanel:Molex_22-27-2021_J306_B + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + 22-27-2021 + + RadianPanel:Molex_22-27-2021_J306_B + + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + + + + + + + f536e084-c6a1-57ea-8653-b1afeea3b2ff + + + + + + + + + + + 100nF + RadianPanel:C_0603 + 16V X7R; verify effective capacitance at DC bias + + SELECT 100nF 16V X7R 0603 + + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + 60f3a6c1-6f01-5457-bd28-d2f52e211c96 + + + + + + + + + + + 1uF + RadianPanel:C_0805 + 16V X7R; verify effective capacitance at DC bias + + SELECT 1uF 16V X7R 0805 + + RadianPanel:C_0805 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + 9b8308d0-0230-537b-ac42-dd90818e7824 + + + + + + + + + + + BAT54S + RadianPanel:SOT23_BAT54S + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + + BAT54S,215 + Nexperia + RadianPanel:SOT23_BAT54S + + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + + + + + + + + 0a9cb6cd-78cb-5760-9975-5324be4a7a45 + + + + + + + + + + + + 450301014042 + RadianPanel:Wurth_450301014042_Exact_B + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + 450301014042 + + RadianPanel:Wurth_450301014042_Exact_B + + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + + + + + + + 7a1dc449-3659-51a2-b518-7001903ac8ef + + + + + + + + + + + + 200k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 200k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 4f0fc251-9961-5f36-90aa-92cff98b7d48 + + + + + + + + + + + 100k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 100k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 8186e4ec-ba27-5931-9775-980ea06efde9 + + + + + + + + + + + 200k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 200k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 86815e7d-c360-516d-afff-46eb3b0d64c0 + + + + + + + + + + + 10k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 10k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 45109df0-d108-5e40-988e-420c2d961340 + + + + + + + + + + + 10k + RadianPanel:R_0603 + Resistor 0.1% + + SELECT 10k 0.1% 0603 + + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + 5a1e97fe-608e-588b-abb0-73dfd93ea8dd + + + + + + + + + + + VREF25 + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 9a57579e-c67c-5118-aa2a-a9574281fbeb + + + + + + + + + + MOD_BIPOLAR + RadianPanel:TestPoint_D2 + Exposed soldermask aperture, no component. + + PCB test pad + + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 2d0eae80-797a-549c-a27f-4473fbcee434 + + + + + + + + + + OPA2192ID + RadianPanel:SOIC8_3.9x4.9_P1.27 + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + + OPA2192ID + Texas Instruments + RadianPanel:SOIC8_3.9x4.9_P1.27 + + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + + + + + + + + 76da6519-7887-5b94-ad4a-2323d80f01ec + + + + + + + + + + + + + + + + + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + IPS1-110-01-L-D + Samtec + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + + + + + + + 37c3ba3a-67a8-53b0-9b31-8f009dd72af4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 22-27-2061 + RadianPanel:Molex_22-27-2061_J202_B + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + 22-27-2061 + + RadianPanel:Molex_22-27-2061_J202_B + + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + + + + + + + 6e352fab-9100-5920-bc40-ba528cdf06e9 + + + + + + + + + + + + + + + PROGRAM / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + Internal service push button, accessible after module removal. + + B3F-1000 + Omron + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + Internal service push button, accessible after module removal. + + + + + + + + 6ac8d041-74b6-51e1-b114-8a9f2fd7723c + + + + + + + + + + + RESET / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + B3F-1000 + Omron + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + + + + + + + + + ac438e8b-9f2d-50a4-ab02-b0bd7ac6245f + + + + + + + + + + + + + 50V X7R; verify effective capacitance at DC bias + + C + 10uF + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + + 50V X7R; verify effective capacitance at DC bias + + C + 100nF + RadianPanel:C_0603 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + + 16V X7R; verify effective capacitance at DC bias + + C + 100nF + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + + 16V X7R; verify effective capacitance at DC bias + + C + 1uF + RadianPanel:C_0805 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + + 16V X7R; verify effective capacitance at DC bias + + C + 100nF + RadianPanel:C_0603 + + 16V X7R; verify effective capacitance at DC bias + + + + + + + + + 25V X7R; verify effective capacitance at DC bias + + C + 22uF + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + + 25V X7R; verify effective capacitance at DC bias + + C + 22uF + RadianPanel:C_1210 + + 25V X7R; verify effective capacitance at DC bias + + + + + + + + + 50V C0G; verify effective capacitance at DC bias + + C + 75pF + RadianPanel:C_0603 + + 50V C0G; verify effective capacitance at DC bias + + + + + + + + + 50V X7R; verify effective capacitance at DC bias + + C + 10uF + RadianPanel:C_1210 + + 50V X7R; verify effective capacitance at DC bias + + + + + + + + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + D + SS54 / OR + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + Vishay + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 1 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 2 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 3 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + + D + VOICE 4 + RadianPanel:LED_D3.0_P2.54 + + 3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height. + Kingbright + + + + + + + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + + D + SS54 / OR + RadianPanel:D_SMB + + Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature. + Vishay + + + + + + + + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + + D + SMBJ15A + RadianPanel:D_SMB + + Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test. + Vishay + + + + + + + + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + + D + BAT54S + RadianPanel:SOT23_BAT54S + + Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior. + Nexperia + + + + + + + + + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + + ENC + 24 PPR / PUSH + RadianPanel:Bourns_PEC11R4_RearFacing_Switch + + 20 mm shaft / 7 mm bushing replaces proposed 15 mm shaft part to accommodate common PCB plane. Check encoder direction and nut stack. + Bourns + + + + + + + + + + + + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + F + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + F + 2A FUSE / >=32V + RadianPanel:Fuse_1206 + + Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate. + + + + + + + + + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + J + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine A; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + Samtec + + + + + + + + + + + + + + + + + + + + + + + + + + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + + J + IPS1-110-01-L-D + RadianPanel:Stack_2x10_P2.54 + + Direct mezzanine B; Samtec IPS1 socket mates mainboard IPT1-110-06-L-D. Fully-mated PCB gap 19.99 mm; max 20.45 mm. Use ~20.0 mm standoffs and bench-verify seating before production quantity. + Samtec + + + + + + + + + + + + + + + + + + + + + + + + + + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + J + 61201021621 + RadianPanel:Wurth_61201021621_Exact_B + + Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections. + + + + + + + + + + + + + + + + + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + J + 22-27-2021 + RadianPanel:Molex_22-27-2021_J201_B + + From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. Dock cutout waits for inlet selection. + + + + + + + + + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + J + 22-27-2061 + RadianPanel:Molex_22-27-2061_J202_B + + Pin-for-pin to J102 -> main J2, no level conversion. Short cable, validate JTAG frequency. + + + + + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + PITCH 0-5V + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + MOD + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + GATE + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + LINE L + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + + J + LINE R + RadianPanel:WQP518MA_PJ398SM_Vertical + + Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check. + QingPu / Thonk + + + + + + + + + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + J + 22-27-2021 + RadianPanel:Molex_22-27-2021_J306_B + + Short 2-wire harness to retained SDS-50J pins 4 and 5. No DIN 2/shield-to-GND connection. DIN retention without old carrier still needs a tested clamp; no third custom PCB. + + + + + + + + + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + JP + 450301014042 + RadianPanel:Wurth_450301014042_Exact_B + + Move only with power off. Bipolar mode requires matching firmware scaling and calibration. NOT the front MODE switch. + + + + + + + + + + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + + L + 10uH 4A / Isat7.5A + RadianPanel:Bourns_SRP7050TA + + 4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing. + Bourns + + + + + + + + Resistor 1% + + R + 100k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 1% + + R + 13.3k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 0.1% + + R + 200k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 100k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 200k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 10k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 0.1% + + R + 10k + RadianPanel:R_0603 + + Resistor 0.1% + + + + + + + + + Resistor 1% + + R + 511k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 1% + + R + 105k + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Resistor 1% + + R + 49.9 + RadianPanel:R_0603 + + Resistor 1% + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / TENSION + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / DECAY + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / CHAOS + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / DRIVE + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / DELAY + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + + RV + 10k linear / REVERB + RadianPanel:Bourns_PTV09A4_RearFacing + + Pin 1 CCW/GND, pin 3 CW/VREF25: verify direction on physical sample. No added wiper RC. Mount tabs soldered, electrically NC. + Bourns + + + + + + + + + + + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + + SW + MODE / SPDT ON-ON + RadianPanel:E_Switch_100SP_M2 + + Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required. + E-Switch + + + + + + + + + Internal service push button, accessible after module removal. + + SW + PROGRAM / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + Internal service push button, accessible after module removal. + Omron + + + + + + + + + SW + RESET / SERVICE + RadianPanel:SW_PUSH_6x6_P6.5x4.5 + + + Omron + + + + + + + + Exposed soldermask aperture, no component. + + TP + GND + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + VIN5 + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + VRAW + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + VREF25 + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + Exposed soldermask aperture, no component. + + TP + MOD_BIPOLAR + RadianPanel:TestPoint_D2 + + Exposed soldermask aperture, no component. + + + + + + + + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + + U + TPS54302DDCR + RadianPanel:TI_DDC0006A_SOT23_6 + + 3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit. + Texas Instruments + + + + + + + + + + + + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + + U + OPA2192ID + RadianPanel:SOIC8_3.9x4.9_P1.27 + + A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping. + Texas Instruments + + + + + + + + + + + + + + + + ${KIPRJMOD}/../library/RadianPanel.kicad_sym + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/panel/reports/native/post_cleanup_exact_drc.json b/hardware/panel/reports/native/post_cleanup_exact_drc.json new file mode 100644 index 0000000..a9c6a8b --- /dev/null +++ b/hardware/panel/reports/native/post_cleanup_exact_drc.json @@ -0,0 +1,53 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-17T22:54:08", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "radian_panel.kicad_pcb", + "unconnected_items": [], + "violations": [ + { + "description": "Footprint 'Stack_2x10_P2.54' does not match copy in library 'RadianPanel'", + "items": [ + { + "description": "Footprint J101", + "pos": { + "x": 43.0, + "y": 56.25 + }, + "uuid": "3c304775-2f0b-47c3-9bcb-e54ca711f4bc" + } + ], + "severity": "warning", + "type": "lib_footprint_mismatch" + } + ] +} diff --git a/hardware/panel/reports/native/prod-jtag-local.json b/hardware/panel/reports/native/prod-jtag-local.json new file mode 100644 index 0000000..734a426 --- /dev/null +++ b/hardware/panel/reports/native/prod-jtag-local.json @@ -0,0 +1,383 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T05:35:50", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "radian_panel.kicad_pcb", + "unconnected_items": [ + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 1 [DESKTOP_12V] of J201", + "pos": { + "x": 100.0, + "y": 95.0 + }, + "uuid": "e21def7b-da6e-4e0e-b677-6bf538aafcad" + }, + { + "description": "Track [DESKTOP_12V] on F.Cu, length 0.0200 mm", + "pos": { + "x": 27.25, + "y": 76.5 + }, + "uuid": "16da8b9c-657d-52a5-beb4-ea1359291aa3" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Track [MIDI4] on B.Cu, length 0.0200 mm", + "pos": { + "x": 58.77, + "y": 89.5 + }, + "uuid": "631ba5c5-aa47-53d2-94d9-c297ddd416fe" + }, + { + "description": "PTH pad 4 [MIDI4] of J306", + "pos": { + "x": 81.110913, + "y": 81.610913 + }, + "uuid": "7a076f16-255f-44a0-9470-e693b0cc1d4c" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Track [MIDI5] on B.Cu, length 0.2300 mm", + "pos": { + "x": 56.23, + "y": 89.5 + }, + "uuid": "da07d234-27bd-50c3-a481-1f317e70decd" + }, + { + "description": "PTH pad 5 [MIDI5] of J306", + "pos": { + "x": 81.110913, + "y": 89.389087 + }, + "uuid": "8d90b8e5-2ffa-4fe0-8302-c47c1ebae6eb" + } + ], + "severity": "error", + "type": "unconnected_items" + } + ], + "violations": [ + { + "description": "Front solder mask aperture bridges items with different nets", + "items": [ + { + "description": "Track [JTAG_TDO] on F.Cu, length 3.3842 mm", + "pos": { + "x": 103.73, + "y": 94.0 + }, + "uuid": "1d59a680-d878-4171-b6ec-80e801f7f2a2" + }, + { + "description": "PTH pad 1 [DESKTOP_12V] of J201", + "pos": { + "x": 100.0, + "y": 95.0 + }, + "uuid": "e21def7b-da6e-4e0e-b677-6bf538aafcad" + } + ], + "severity": "error", + "type": "solder_mask_bridge" + }, + { + "description": "Front solder mask aperture bridges items with different nets", + "items": [ + { + "description": "Track [JTAG_TDO] on F.Cu, length 6.5000 mm", + "pos": { + "x": 101.0, + "y": 96.0 + }, + "uuid": "6932f21d-b2cd-44b3-bfec-80d7b1b2322d" + }, + { + "description": "PTH pad 1 [DESKTOP_12V] of J201", + "pos": { + "x": 100.0, + "y": 95.0 + }, + "uuid": "e21def7b-da6e-4e0e-b677-6bf538aafcad" + } + ], + "severity": "error", + "type": "solder_mask_bridge" + }, + { + "description": "Tracks crossing", + "items": [ + { + "description": "Track [V3V3] on B.Cu, length 2.9155 mm", + "pos": { + "x": 112.5, + "y": 104.5 + }, + "uuid": "0e5aefa8-dea7-4b61-af6e-e250fbcc01ad" + }, + { + "description": "Track [PROGRAM_B] on B.Cu, length 57.7500 mm", + "pos": { + "x": 117.75, + "y": 104.5 + }, + "uuid": "793b4ad9-f23c-5fcb-aa83-29aa92f8b0d9" + } + ], + "severity": "error", + "type": "tracks_crossing" + }, + { + "description": "Tracks crossing", + "items": [ + { + "description": "Track [PROGRAM_B] on B.Cu, length 57.7500 mm", + "pos": { + "x": 117.75, + "y": 104.5 + }, + "uuid": "793b4ad9-f23c-5fcb-aa83-29aa92f8b0d9" + }, + { + "description": "Track [V3V3] on B.Cu, length 4.5000 mm", + "pos": { + "x": 112.5, + "y": 100.0 + }, + "uuid": "cacfc38b-74f1-4c90-a968-93d90c0e5f82" + } + ], + "severity": "error", + "type": "tracks_crossing" + }, + { + "description": "Hole clearance violation (board setup constraints hole clearance 0.2500 mm; actual 0.0000 mm)", + "items": [ + { + "description": "Track [V3V3] on B.Cu, length 2.7333 mm", + "pos": { + "x": 106.27, + "y": 98.635 + }, + "uuid": "f932ae9e-bca9-4c31-927a-c35ada5a476e" + }, + { + "description": "NPTH pad of J202", + "pos": { + "x": 107.54, + "y": 98.0 + }, + "uuid": "aafafebb-6280-4afd-895e-2a6313df0be7" + } + ], + "severity": "error", + "type": "hole_clearance" + }, + { + "description": "Hole clearance violation (board setup constraints hole clearance 0.2500 mm; actual 0.0517 mm)", + "items": [ + { + "description": "Track [GND] on B.Cu, length 2.5438 mm", + "pos": { + "x": 103.73, + "y": 98.635 + }, + "uuid": "768a080f-132a-4e63-b668-93c3f447ac1f" + }, + { + "description": "NPTH pad of J202", + "pos": { + "x": 102.46, + "y": 99.016 + }, + "uuid": "562949ba-9867-4c1b-9f10-b8703b47301b" + } + ], + "severity": "error", + "type": "hole_clearance" + }, + { + "description": "Items shorting two nets (nets JTAG_TDO and DESKTOP_12V)", + "items": [ + { + "description": "Track [JTAG_TDO] on F.Cu, length 6.5000 mm", + "pos": { + "x": 101.0, + "y": 96.0 + }, + "uuid": "6932f21d-b2cd-44b3-bfec-80d7b1b2322d" + }, + { + "description": "PTH pad 1 [DESKTOP_12V] of J201", + "pos": { + "x": 100.0, + "y": 95.0 + }, + "uuid": "e21def7b-da6e-4e0e-b677-6bf538aafcad" + } + ], + "severity": "error", + "type": "shorting_items" + }, + { + "description": "Items shorting two nets (nets JTAG_TDO and DESKTOP_12V)", + "items": [ + { + "description": "Track [JTAG_TDO] on F.Cu, length 3.3842 mm", + "pos": { + "x": 103.73, + "y": 94.0 + }, + "uuid": "1d59a680-d878-4171-b6ec-80e801f7f2a2" + }, + { + "description": "PTH pad 1 [DESKTOP_12V] of J201", + "pos": { + "x": 100.0, + "y": 95.0 + }, + "uuid": "e21def7b-da6e-4e0e-b677-6bf538aafcad" + } + ], + "severity": "error", + "type": "shorting_items" + }, + { + "description": "Tracks crossing", + "items": [ + { + "description": "Track [JTAG_TCK] on F.Cu, length 3.9051 mm", + "pos": { + "x": 108.5, + "y": 100.5 + }, + "uuid": "26020489-e66f-48f1-82e3-51e50ffde4f2" + }, + { + "description": "Track [JTAG_TDO] on F.Cu, length 10.0000 mm", + "pos": { + "x": 101.0, + "y": 102.5 + }, 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b/hardware/panel/reports/native/prod-jtag-v5.json new file mode 100644 index 0000000..73641f2 --- /dev/null +++ b/hardware/panel/reports/native/prod-jtag-v5.json @@ -0,0 +1,420 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T05:39:58", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": 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+ ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Pad 2 [JTAG_TMS] of J202 on B.Cu", + "pos": { + "x": 106.27, + "y": 97.365 + }, + "uuid": "1014b175-4a92-4a67-a92b-203b8e9521c9" + }, + { + "description": "Track [JTAG_TMS] on B.Cu, length 4.5000 mm", + "pos": { + "x": 115.5, + "y": 93.0 + }, + "uuid": "53ce1daa-77bb-5300-9c5a-46e68418215a" + } + ], + "severity": "error", + "type": "unconnected_items" + } + ], + "violations": [ + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [DESKTOP_12V] on F.Cu, length 0.0200 mm", + "pos": { + "x": 27.25, + "y": 76.5 + }, + "uuid": "16da8b9c-657d-52a5-beb4-ea1359291aa3" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [MIDI4] on B.Cu, length 0.0200 mm", + "pos": { + "x": 58.77, + "y": 89.5 + }, + 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b/hardware/panel/reports/native/production-parts-drc.json @@ -0,0 +1,1484 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T05:10:17", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "radian_panel.kicad_pcb", + "unconnected_items": [], + "violations": [ + { + "description": "Rear solder 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+ } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "Pad 2 [JTAG_TMS] of J202 on B.Cu", + "pos": { + "x": 156.27, + "y": 111.365 + }, + "uuid": "ad055352-afa0-406c-bf1d-1c6b9547040e" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "Pad 1 [V3V3] of J202 on B.Cu", + "pos": { + "x": 156.27, + "y": 112.635 + }, + "uuid": "59ca6db7-554b-4942-ae59-edb01ea84d1a" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "Pad 2 [JTAG_TMS] of J202 on B.Cu", + "pos": { + "x": 156.27, + "y": 111.365 + }, + "uuid": "ad055352-afa0-406c-bf1d-1c6b9547040e" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "NPTH pad of J202", + "pos": { + "x": 157.54, + "y": 112.0 + }, + "uuid": "341a4604-b601-4d02-a353-e29361a0a892" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "NPTH pad of J202", + "pos": { + "x": 157.54, + "y": 112.0 + }, + "uuid": "341a4604-b601-4d02-a353-e29361a0a892" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "PCB text 'DRAFT - NOT FABRICATION RELEASE' on B.Silkscreen", + "pos": { + "x": 75.0, + "y": 116.5 + }, + "uuid": "d20b2117-a16e-5c86-86a2-87b202be9ff4" + }, + { + "description": "PTH pad 2 [unconnected-(J201-Pad2)] of J201", + "pos": { + "x": 87.3, + "y": 115.3 + }, + "uuid": "ab4758d4-d3ea-4f1f-94b9-bb4a1d048a03" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "PCB text '12 V DESKTOP / RACK +12 ONLY' on B.Silkscreen", + "pos": { + "x": 82.0, + "y": 111.0 + }, + "uuid": "69d97ec7-f7bb-5336-88a2-256ee2d1d115" + }, + { + "description": "PTH pad 1 [DESKTOP_12V] of J201", + "pos": { + "x": 85.0, + "y": 110.0 + }, + "uuid": "4fca9989-d4c1-4985-a404-57068768e893" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "Pad 1 [V3V3] of J202 on B.Cu", + "pos": { + "x": 156.27, + "y": 112.635 + }, + "uuid": "59ca6db7-554b-4942-ae59-edb01ea84d1a" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by board edge", + "items": [ + { + "description": "Segment on Edge.Cuts", + "pos": { + "x": 162.5, + "y": 118.5 + }, + "uuid": "0fe558f3-ad59-5104-ad0c-e0651732322f" + } + ], + "severity": "warning", + "type": "silk_edge_clearance" + } + ] +} diff --git a/hardware/panel/reports/native/production-parts-v2-drc.json b/hardware/panel/reports/native/production-parts-v2-drc.json new file mode 100644 index 0000000..ea0cf24 --- /dev/null +++ b/hardware/panel/reports/native/production-parts-v2-drc.json @@ -0,0 +1,2525 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T05:13:14", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "radian_panel.kicad_pcb", + "unconnected_items": [], + "violations": [ + { + "description": "Rear solder mask aperture bridges items with different nets", + "items": [ + { + "description": "Track [JTAG_TMS] on B.Cu, length 4.0257 mm", + "pos": { + "x": 56.27, + "y": 44.365 + }, + "uuid": "6e9a48a8-8974-4886-8e9c-d7c6159eab0b" + }, + { + "description": "Pad 1 [V3V3] of J202 on B.Cu", + "pos": { + "x": 56.27, + "y": 45.635 + }, + "uuid": "89e8b9d6-ec91-40cf-883b-f08445d723df" + } + ], + "severity": "error", + "type": "solder_mask_bridge" + }, + { + "description": "Front solder mask aperture bridges items with different nets", + "items": [ + { + "description": "Track [MIDI4] on F.Cu, length 7.8102 mm", + "pos": { + "x": 58.0, + "y": 66.0 + }, + "uuid": "217112ca-ea10-4392-8b2c-84cc4123137c" + }, + { + "description": "Pad 2 [RACK_FUSED] of F1 on F.Cu", + "pos": { + "x": 54.5, + "y": 63.5 + }, + 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"severity": "error", + "type": "solder_mask_bridge" + }, + { + "description": "Rear solder mask aperture bridges items with different nets", + "items": [ + { + "description": "Track [JTAG_TDO] on B.Cu, length 2.8900 mm", + "pos": { + "x": 49.0, + "y": 54.98 + }, + "uuid": "5d872f2e-0b1d-41a2-a62f-ffb052c7ec10" + }, + { + "description": "PTH pad 16 [reset_n] of J101", + "pos": { + "x": 49.35, + "y": 54.98 + }, + "uuid": "6d3c33e5-f491-4b6d-8550-b4a64a4725e9" + } + ], + "severity": "error", + "type": "solder_mask_bridge" + }, + { + "description": "Rear solder mask aperture bridges items with different nets", + "items": [ + { + "description": "Track [JTAG_TDO] on B.Cu, length 4.9800 mm", + "pos": { + "x": 49.0, + "y": 50.0 + }, + "uuid": "69c49c9d-a550-4737-b0c3-24c5c896eb24" + }, + { + "description": "PTH pad 16 [reset_n] of J101", + "pos": { + "x": 49.35, + "y": 54.98 + }, + "uuid": "6d3c33e5-f491-4b6d-8550-b4a64a4725e9" + } + ], + "severity": "error", + "type": "solder_mask_bridge" + }, + { + "description": "Rear solder mask aperture bridges items with different nets", + "items": [ + { + "description": "Track [JTAG_TDI] on B.Cu, length 7.1318 mm", + "pos": { + "x": 55.0, + "y": 45.635 + }, + "uuid": "0a0be06c-ada5-40d7-9c54-1592dbf31e7b" + }, + { + "description": "Pad 1 [V3V3] of J202 on B.Cu", + "pos": { + "x": 56.27, + "y": 45.635 + }, + "uuid": "89e8b9d6-ec91-40cf-883b-f08445d723df" + } + ], + "severity": "error", + "type": "solder_mask_bridge" + }, + { + "description": "Rear solder mask aperture bridges items with different nets", + "items": [ + { + "description": "Track [JTAG_TDI] on B.Cu, length 7.5700 mm", + "pos": { + "x": 62.0, + "y": 57.52 + }, + "uuid": "29a109c0-1e81-4c43-9843-b985e160f95f" + }, + { + "description": "PTH pad MP1 [unconnected-(RV4-PadMP1)] of RV4", + "pos": { + "x": 60.7, + "y": 58.5 + }, + "uuid": "6af844c8-df51-5cc2-bf62-c75b1f62f086" + } + ], + "severity": "error", + "type": "solder_mask_bridge" + }, + { + "description": "Rear solder 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"description": "Track [RACK_12V] on F.Cu, length 0.3536 mm", + "pos": { + "x": 53.25, + "y": 61.75 + }, + "uuid": "08831a66-369a-5654-bb3e-433f45709cb8" + }, + { + "description": "Track [MIDI4] on F.Cu, length 7.8102 mm", + "pos": { + "x": 58.0, + "y": 66.0 + }, + "uuid": "217112ca-ea10-4392-8b2c-84cc4123137c" + } + ], + "severity": "error", + "type": "shorting_items" + }, + { + "description": "Items shorting two nets (nets MIDI4 and RACK_12V)", + "items": [ + { + "description": "Track [MIDI4] on F.Cu, length 7.8102 mm", + "pos": { + "x": 58.0, + "y": 66.0 + }, + "uuid": "217112ca-ea10-4392-8b2c-84cc4123137c" + }, + { + "description": "Track [RACK_12V] on F.Cu, length 0.2500 mm", + "pos": { + "x": 53.0, + "y": 61.75 + }, + "uuid": "4b33061b-a6f4-5280-a142-d4cf525429ec" + } + ], + "severity": "error", + "type": "shorting_items" + }, + { + "description": "Items shorting two nets (nets MIDI4 and RACK_12V)", + "items": [ + { + "description": "Track [MIDI4] on F.Cu, length 7.8102 mm", + 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"description": "Track [MIDI4] on F.Cu, length 7.8102 mm", + "pos": { + "x": 58.0, + "y": 66.0 + }, + "uuid": "217112ca-ea10-4392-8b2c-84cc4123137c" + } + ], + "severity": "error", + "type": "shorting_items" + }, + { + "description": "Tracks crossing", + "items": [ + { + "description": "Track [JTAG_TDI] on B.Cu, length 40.2500 mm", + "pos": { + "x": 60.5, + "y": 104.0 + }, + "uuid": "0df71aa7-c20e-5701-a014-ad63042157c8" + }, + { + "description": "Track [DESKTOP_12V] on B.Cu, length 7.0711 mm", + "pos": { + "x": 65.0, + "y": 95.0 + }, + "uuid": "fb6f4e94-136a-45d4-9562-24df138c514b" + } + ], + "severity": "error", + "type": "tracks_crossing" + }, + { + "description": "Tracks crossing", + "items": [ + { + "description": "Track [MIDI4] on B.Cu, length 16.0000 mm", + "pos": { + "x": 58.75, + "y": 89.5 + }, + "uuid": "a628fdca-077b-5337-88db-1904f76356cc" + }, + { + "description": "Track [DESKTOP_12V] on B.Cu, length 10.7703 mm", + "pos": { + "x": 60.0, + "y": 80.0 + }, + "uuid": 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54.98 + }, + "uuid": "6d3c33e5-f491-4b6d-8550-b4a64a4725e9" + } + ], + "severity": "error", + "type": "shorting_items" + }, + { + "description": "Hole clearance violation (board setup constraints hole clearance 0.2500 mm; actual 0.2385 mm)", + "items": [ + { + "description": "Track [JTAG_TDO] on B.Cu, length 4.0726 mm", + "pos": { + "x": 53.73, + "y": 44.365 + }, + "uuid": "e1ac89b2-308e-4e89-ac62-322a35bc1b6a" + }, + { + "description": "NPTH pad of J202", + "pos": { + "x": 52.46, + "y": 43.984 + }, + "uuid": "4cf20dfd-1619-433b-8aa8-7d48b0643ebf" + } + ], + "severity": "error", + "type": "hole_clearance" + }, + { + "description": "Hole clearance violation (board minimum hole clearance 0.2500 mm; actual 0.0000 mm)", + "items": [ + { + "description": "Track [JTAG_TDO] on B.Cu, length 4.9800 mm", + "pos": { + "x": 49.0, + "y": 50.0 + }, + "uuid": "69c49c9d-a550-4737-b0c3-24c5c896eb24" + }, + { + "description": "PTH pad 16 [reset_n] of J101", + "pos": { + "x": 49.35, + "y": 54.98 + }, + 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], + "severity": "error", + "type": "clearance" + }, + { + "description": "Items shorting two nets (nets GND and JTAG_TCK)", + "items": [ + { + "description": "Pad 5 [GND] of J202 on B.Cu", + "pos": { + "x": 53.73, + "y": 45.635 + }, + "uuid": "b0c4c250-814c-41ee-af6d-03991a722828" + }, + { + "description": "Track [JTAG_TCK] on B.Cu, length 4.1489 mm", + "pos": { + "x": 55.0, + "y": 44.365 + }, + "uuid": "cb6f1a50-f995-43fb-a26d-1b83c778f2f6" + } + ], + "severity": "error", + "type": "shorting_items" + }, + { + "description": "Non-Mirrored text on back layer", + "items": [], + "severity": "warning", + "type": "nonmirrored_text_on_back_layer" + }, + { + "description": "Non-Mirrored text on back layer", + "items": [], + "severity": "warning", + "type": "nonmirrored_text_on_back_layer" + }, + { + "description": "Non-Mirrored text on back layer", + "items": [], + "severity": "warning", + "type": "nonmirrored_text_on_back_layer" + }, + { + "description": "Non-Mirrored text on back layer", + "items": [], + "severity": "warning", + "type": "nonmirrored_text_on_back_layer" + }, + { + "description": "Silkscreen clearance", + "items": [], + "severity": "warning", + "type": "silk_overlap" + }, + { + "description": "Silkscreen clearance", + "items": [ + { + "description": "Segment of J201 on F.Silkscreen", + "pos": { + "x": 83.415, + "y": 109.5 + }, + "uuid": "12866a60-70f9-42be-8897-70b0ff9c60a2" + } + ], + "severity": "warning", + "type": "silk_overlap" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "PTH pad 1 [DESKTOP_12V] of J201", + "pos": { + "x": 85.0, + "y": 110.0 + }, + "uuid": "24e12cd1-6025-4ece-bbbe-ee661a817bbb" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "PTH pad 1 [DESKTOP_12V] of J201", + "pos": { + "x": 85.0, + "y": 110.0 + }, + "uuid": "24e12cd1-6025-4ece-bbbe-ee661a817bbb" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clearance", + "items": [ + { + "description": "Rectangle of J200 on B.Silkscreen", + "pos": { + "x": 169.465, + "y": 54.21 + }, + "uuid": "f32c0fe6-c35a-42c7-82c3-0819244c2b9a" + } + ], + "severity": "warning", + "type": "silk_overlap" + }, + { + "description": "Silkscreen clearance", + "items": [ + { + "description": "Rectangle of JP1 on B.Silkscreen", + "pos": { + "x": 160.25, + "y": 39.0 + }, + "uuid": "6e552bc2-102c-48d5-bbb8-9268bad2c05c" + } + ], + "severity": "warning", + "type": "silk_overlap" + }, + { + "description": "Silkscreen clearance", + "items": [], + "severity": "warning", + "type": "silk_overlap" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "PTH pad 2 [unconnected-(J200-Pad2)] of J200", + "pos": { + "x": 172.73, + "y": 59.42 + }, + "uuid": "4f4428f7-9810-4527-b89f-d336f82f1e5c" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "PTH pad 1 [unconnected-(J200-Pad1)] of J200", + "pos": { + "x": 175.27, + "y": 59.42 + }, + "uuid": "971fe4cc-e89e-463a-af83-2f432470383d" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "PTH pad 1 [MOD_IN] of JP1", + "pos": { + "x": 165.5, + "y": 40.5 + }, + "uuid": "d8f457ea-ba9f-4581-9adb-4b3fefbc3d7d" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "PTH pad 2 [MOD_BIPOLAR] of JP1", + "pos": { + "x": 162.96, + "y": 40.5 + }, + "uuid": "c8c23181-c202-4807-bce7-4197816f9726" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "PTH pad 3 [MOD_RAW] of JP1", + "pos": { + "x": 168.04, + "y": 40.5 + }, + "uuid": "7955e95a-c911-4618-aa49-7600880f8cda" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "PCB text 'DRAFT - NOT FABRICATION RELEASE' on B.Silkscreen", + "pos": { + "x": 75.0, + "y": 116.5 + }, + "uuid": "d20b2117-a16e-5c86-86a2-87b202be9ff4" + }, + { + "description": "PTH pad 2 [unconnected-(J201-Pad2)] of J201", + "pos": { + "x": 87.3, + "y": 115.3 + }, + "uuid": "83889800-911d-42b6-ae55-7ce4a20a4af2" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "PCB text '12 V DESKTOP / RACK +12 ONLY' on B.Silkscreen", + "pos": { + "x": 82.0, + "y": 111.0 + }, + "uuid": "69d97ec7-f7bb-5336-88a2-256ee2d1d115" + }, + { + "description": "PTH pad 1 [DESKTOP_12V] of J201", + "pos": { + "x": 85.0, + "y": 110.0 + }, + "uuid": "24e12cd1-6025-4ece-bbbe-ee661a817bbb" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "NPTH pad of J202", + "pos": { + "x": 52.46, + "y": 43.984 + }, + "uuid": "4cf20dfd-1619-433b-8aa8-7d48b0643ebf" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "NPTH pad of J202", + "pos": { + "x": 52.46, + "y": 46.016 + }, + "uuid": "06e129a6-10e2-4f58-8993-5089febe6ebd" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "Pad 6 [JTAG_TDO] of J202 on B.Cu", + "pos": { + "x": 53.73, + "y": 44.365 + }, + "uuid": "a556f190-42c8-4b1f-996b-0b281f0cac29" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "Pad 3 [JTAG_TDI] of J202 on B.Cu", + "pos": { + "x": 55.0, + "y": 45.635 + }, + "uuid": "42647c46-4e79-4586-8505-e63051eeaf7a" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "Pad 5 [GND] of J202 on B.Cu", + "pos": { + "x": 53.73, + "y": 45.635 + }, + "uuid": "b0c4c250-814c-41ee-af6d-03991a722828" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "Pad 6 [JTAG_TDO] of J202 on B.Cu", + "pos": { + "x": 53.73, + "y": 44.365 + }, + "uuid": "a556f190-42c8-4b1f-996b-0b281f0cac29" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "Pad 4 [JTAG_TCK] of J202 on B.Cu", + "pos": { + "x": 55.0, + "y": 44.365 + }, + "uuid": "c415f3a9-e4de-4c88-97e2-5db7a15d7629" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "Pad 5 [GND] of J202 on B.Cu", + "pos": { + "x": 53.73, + "y": 45.635 + }, + "uuid": "b0c4c250-814c-41ee-af6d-03991a722828" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "Pad 2 [JTAG_TMS] of J202 on B.Cu", + "pos": { + "x": 56.27, + "y": 44.365 + }, + "uuid": "7ee152a6-7b0b-450e-8b50-fc15b2fac40d" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "Pad 1 [V3V3] of J202 on B.Cu", + "pos": { + "x": 56.27, + "y": 45.635 + }, + "uuid": "89e8b9d6-ec91-40cf-883b-f08445d723df" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "Pad 1 [V3V3] of J202 on B.Cu", + "pos": { + "x": 56.27, + "y": 45.635 + }, + "uuid": "89e8b9d6-ec91-40cf-883b-f08445d723df" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "Pad 2 [JTAG_TMS] of J202 on B.Cu", + "pos": { + "x": 56.27, + "y": 44.365 + }, + "uuid": "7ee152a6-7b0b-450e-8b50-fc15b2fac40d" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "NPTH pad of J202", + "pos": { + "x": 57.54, + "y": 45.0 + }, + "uuid": "96f0090e-3004-4007-b9c5-661e0c84c078" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Silkscreen clipped by solder mask", + "items": [ + { + "description": "NPTH pad of J202", + "pos": { + "x": 57.54, + "y": 45.0 + }, + "uuid": "96f0090e-3004-4007-b9c5-661e0c84c078" + } + ], + "severity": "warning", + "type": "silk_over_copper" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [MIDI4] on B.Cu, length 0.0200 mm", + "pos": { + "x": 58.77, + "y": 89.5 + }, + "uuid": "631ba5c5-aa47-53d2-94d9-c297ddd416fe" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [MIDI5] on B.Cu, length 0.2300 mm", + "pos": { + "x": 56.23, + "y": 89.5 + }, + "uuid": "da07d234-27bd-50c3-a481-1f317e70decd" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [JTAG_TCK] on F.Cu, length 0.0200 mm", + "pos": { + "x": 132.27, + "y": 99.5 + }, + "uuid": "d4021ab9-6e51-5cfb-a905-4adfee253a31" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [JTAG_TDO] on F.Cu, length 0.2300 mm", + "pos": { + "x": 129.73, + "y": 99.5 + }, + "uuid": "0893bf52-e5dc-5b9e-84c0-6c90cd717aea" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [JTAG_TDI] on B.Cu, length 0.1900 mm", + "pos": { + "x": 127.19, + "y": 99.5 + }, + "uuid": "d9b595d0-6394-5767-99c8-d59cc2756cf7" + } + ], + "severity": "warning", + "type": "track_dangling" + }, + { + "description": "Track has unconnected end", + "items": [ + { + "description": "Track [JTAG_TMS] on B.Cu, length 0.1500 mm", + "pos": { + "x": 124.65, + "y": 99.5 + }, + "uuid": "7846691b-1449-5e10-a1a8-9c5c73cf8c7e" + } + ], + "severity": "warning", + "type": "track_dangling" + } + ] +} diff --git a/hardware/panel/reports/native/production-placement-drc.json b/hardware/panel/reports/native/production-placement-drc.json new file mode 100644 index 0000000..f952f6a --- /dev/null +++ b/hardware/panel/reports/native/production-placement-drc.json @@ -0,0 +1,292 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-18T05:22:27", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "radian_panel.kicad_pcb", + "unconnected_items": [ + { + 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+ "y": 54.98 + }, + "uuid": "c417ab40-72ad-41b8-99ff-c3c9e16ce2e8" + }, + { + "description": "PTH pad 5 [MIDI5] of J306", + "pos": { + "x": 81.110913, + "y": 89.389087 + }, + "uuid": "8ce509bf-970d-4732-89f3-8ba5ff536fb8" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Pad 1 [DESKTOP_12V] of F2 on F.Cu", + "pos": { + "x": 24.5, + "y": 69.5 + }, + "uuid": "a3c2b3cd-ba8a-5279-84d0-101c4b134a37" + }, + { + "description": "PTH pad 1 [DESKTOP_12V] of J201", + "pos": { + "x": 90.0, + "y": 110.0 + }, + "uuid": "c00270e9-094b-4b68-a5d2-dc59c86fb0eb" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Pad 1 [V3V3] of J202 on B.Cu", + "pos": { + "x": 71.27, + "y": 97.635 + }, + "uuid": "149cc440-4f66-42aa-adb2-b3701a1fd9e1" + }, + { + "description": "Track [V3V3] on B.Cu, length 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"severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 19 [JTAG_TDI] of J101", + "pos": { + "x": 54.43, + "y": 57.52 + }, + "uuid": "1299caea-88a2-434d-a78f-f87a7af4ff3a" + }, + { + "description": "Pad 3 [JTAG_TDI] of J202 on B.Cu", + "pos": { + "x": 70.0, + "y": 97.635 + }, + "uuid": "89ee0a76-bdae-4863-ba80-8059e24a4930" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 20 [JTAG_TMS] of J101", + "pos": { + "x": 54.43, + "y": 54.98 + }, + "uuid": "140088ad-61d8-4e1f-9be9-0df357b24e43" + }, + { + "description": "Pad 2 [JTAG_TMS] of J202 on B.Cu", + "pos": { + "x": 71.27, + "y": 96.365 + }, + "uuid": "3c938b79-6e34-4561-b58b-a6950f0352e2" + } + ], + "severity": "error", + "type": "unconnected_items" + } + ], + "violations": [ + { + "description": "Silkscreen clipped by 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b/hardware/panel/reports/native/restored_pre_exact_drc.json new file mode 100644 index 0000000..fb2897e --- /dev/null +++ b/hardware/panel/reports/native/restored_pre_exact_drc.json @@ -0,0 +1,1725 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-17T22:51:19", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": 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"description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 1 [GND] of J301", + "pos": { + "x": 186.5, + "y": 35.98 + }, + "uuid": "55f6746f-d57c-5074-addc-a73a868feb6e" + }, + { + "description": "PTH pad 2 [GND] of J301", + "pos": { + "x": 186.5, + "y": 32.88 + }, + "uuid": "5830b651-5ed2-55fd-ae72-263db09b72ea" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 2 [GND] of J302", + "pos": { + "x": 186.5, + "y": 50.88 + }, + "uuid": "26f4cc92-8c14-500c-aebf-8787b00ea6b1" + }, + { + "description": "PTH pad 1 [GND] of J301", + "pos": { + "x": 186.5, + "y": 35.98 + }, + "uuid": "55f6746f-d57c-5074-addc-a73a868feb6e" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "PTH pad 1 [GND] of J302", + "pos": { + "x": 186.5, + "y": 53.98 + }, + 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b/hardware/panel/reports/native/status.txt new file mode 100644 index 0000000..9c7a477 --- /dev/null +++ b/hardware/panel/reports/native/status.txt @@ -0,0 +1,2 @@ +ERC exit=0 +DRC exit=0 diff --git a/hardware/panel/reports/native/version.txt b/hardware/panel/reports/native/version.txt new file mode 100644 index 0000000..80f86ac --- /dev/null +++ b/hardware/panel/reports/native/version.txt @@ -0,0 +1 @@ +10.0.6 diff --git a/hardware/panel/reports/native/work/controls.kicad_sch b/hardware/panel/reports/native/work/controls.kicad_sch new file mode 100644 index 0000000..51224df --- /dev/null +++ b/hardware/panel/reports/native/work/controls.kicad_sch @@ -0,0 +1,3121 @@ +(kicad_sch + (version 20231120) + (generator "radian_panel_generator") + (uuid "457489a2-9460-526e-a43d-77e41ace7837") + (paper "A2") + (title_block + (title "02 | FRONT-PANEL CONTROLS") + (date "2026-09-15") + (rev "P1 DRAFT") + (comment 1 "Native ERC, footprint verification and hardware testing REQUIRED")) + (lib_symbols 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Check encoder direction and nut stack." + (at 501.65 135.89 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "Bourns" + (at 501.65 135.89 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 488.95 132.08) + (xy 483.87 132.08)) + (stroke + (width 0) + (type default)) + (uuid "e4fe8ca2-88fd-58ec-8f25-a8c968954570")) + (global_label "ENC_A_RAW" + (shape bidirectional) + (at 483.87 132.08 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "4b358b02-2bea-56a8-bc07-d05dbe4ee58d")) + (wire + (pts + (xy 488.95 134.62) + (xy 483.87 134.62)) + (stroke + (width 0) + (type default)) + (uuid "fa9dba91-37a7-53e7-9f40-cfd27d945ba1")) + (global_label "GND" + (shape bidirectional) + (at 483.87 134.62 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "5db3643f-0e43-59c7-8430-1ba1e028ebff")) + (wire + (pts + (xy 488.95 137.16) + (xy 483.87 137.16)) + (stroke + (width 0) + (type default)) + (uuid "08f5f06e-ad3f-5e79-91a8-18fed5153819")) + (global_label "ENC_B_RAW" + (shape bidirectional) + (at 483.87 137.16 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "1341b1d4-cf66-5aaf-90ab-cb593069d919")) + (wire + (pts + (xy 488.95 139.7) + (xy 483.87 139.7)) + (stroke + (width 0) + (type default)) + (uuid "ffc35bdb-db1d-5e1b-b43a-fe9d1942a0d3")) + (global_label "ENC_SW_RAW" + (shape bidirectional) + (at 483.87 139.7 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "c9e3db04-e652-5191-8560-926f7927e125")) + (wire + (pts + (xy 514.35 133.35) + (xy 519.43 133.35)) + (stroke + (width 0) + (type default)) + (uuid "6a09e4e7-7672-5ad6-b913-ea82de53bf1c")) + (global_label "GND" + (shape bidirectional) + (at 519.43 133.35 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "556d4043-8c7c-5c2b-af18-d033925ba23f")) + (no_connect + (at 514.35 135.89) + (uuid "8b149355-53c9-57bb-8508-36a8c1c975e1")) + (no_connect + (at 514.35 138.43) + (uuid "c8a91d6e-43cb-5b92-8b65-4415233aa73c")) + (symbol + (lib_id "RadianPanel:SW1") + (at 78.74 199.39 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "f5afaab2-c860-5fc4-9b76-5a05e19eaa7a") + (property "Reference" "SW1" + (at 78.74 190.31 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "MODE / SPDT ON-ON" + (at 78.74 208.47 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:E_Switch_100SP_M2" + (at 78.74 199.39 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "100SP1T1B1M2REH" + (at 78.74 199.39 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "fd8fa6b7-d257-5c4e-bf74-1b760f05e37f")) + (pin "2" + (uuid "9c9131a9-3fd5-5e91-997a-a1fa8d1a5f0a")) + (pin "3" + (uuid "aec72b04-a480-578f-aab9-3229f950ef04")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/fe425aa9-89e9-5e5b-9592-3f1bdae47718" + (reference "SW1") + (unit 1)))) + (property "Description" "Gold contact option for low-level logic. ST110001 mechanical M2 pattern, 4.7 mm pitch. R contact selection from manufacturer configurator; purchase/stack validation required." + (at 78.74 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "E-Switch" + (at 78.74 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 66.04 198.12) + (xy 60.96 198.12)) + (stroke + (width 0) + (type default)) + (uuid "2ee2eee1-a9a7-585f-a766-ca4cef264c61")) + (global_label "GND" + (shape bidirectional) + (at 60.96 198.12 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "70a95291-9918-5c79-bbc4-60a089af2803")) + (wire + (pts + (xy 66.04 200.66) + (xy 60.96 200.66)) + (stroke + (width 0) + (type default)) + (uuid "e1175de9-d4f0-5c5c-9045-e82981dca934")) + (global_label "cv_select" + (shape bidirectional) + (at 60.96 200.66 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "69a09108-4f29-51bc-aae9-8488969cf0ff")) + (wire + (pts + (xy 91.44 199.39) + (xy 96.52 199.39)) + (stroke + (width 0) + (type default)) + (uuid "04c8a0b5-70ed-5e1d-a4b6-fc33191809a9")) + (global_label "V3V3" + (shape bidirectional) + (at 96.52 199.39 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "63bb2fe6-9193-535b-9fba-b5f4dba05c2a")) + (symbol + (lib_id "RadianPanel:D10") + (at 219.71 199.39 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "fe276ab0-ff85-5ab2-898b-ed8075966655") + (property "Reference" "D10" + (at 219.71 190.31 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "VOICE 1" + (at 219.71 208.47 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:LED_D3.0_P2.54" + (at 219.71 199.39 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "L-934GD" + (at 219.71 199.39 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "30d9f0b5-2578-5e39-9848-77378a6e3cba")) + (pin "2" + (uuid "9c721976-1f8a-5d46-a7e0-bd878654162b")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/fe425aa9-89e9-5e5b-9592-3f1bdae47718" + (reference "D10") + (unit 1)))) + (property "Description" "3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." + (at 219.71 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "Kingbright" + (at 219.71 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 209.55 199.39) + (xy 204.47 199.39)) + (stroke + (width 0) + (type default)) + (uuid "e6ff21ee-51c8-5e90-b95a-87e56a2d0576")) + (global_label "GND" + (shape bidirectional) + (at 204.47 199.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "069b74bf-d299-5271-8364-1855e60ef048")) + (wire + (pts + (xy 229.87 199.39) + (xy 234.95 199.39)) + (stroke + (width 0) + (type default)) + (uuid "c95580d0-6c86-5e40-bf2d-8c378b9fa415")) + (global_label "LED0_A" + (shape bidirectional) + (at 234.95 199.39 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "b7fcf4ac-d86b-591e-a65a-fc641577aa28")) + (symbol + (lib_id "RadianPanel:D11") + (at 360.68 199.39 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "b36d9fe8-1d28-5e73-9188-b569959c7a35") + (property "Reference" "D11" + (at 360.68 190.31 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "VOICE 2" + (at 360.68 208.47 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:LED_D3.0_P2.54" + (at 360.68 199.39 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "L-934GD" + (at 360.68 199.39 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "113595dc-c7f4-529f-807b-d5f414844c40")) + (pin "2" + (uuid "89652a53-cad3-563b-bb01-5a66092af042")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/fe425aa9-89e9-5e5b-9592-3f1bdae47718" + (reference "D11") + (unit 1)))) + (property "Description" "3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." + (at 360.68 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "Kingbright" + (at 360.68 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 350.52 199.39) + (xy 345.44 199.39)) + (stroke + (width 0) + (type default)) + (uuid "fb86d0bc-db9c-5748-b878-62a8d04631e2")) + (global_label "GND" + (shape bidirectional) + (at 345.44 199.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "ab1a9d31-5e69-5a10-8682-70e5e9881ac9")) + (wire + (pts + (xy 370.84 199.39) + (xy 375.92 199.39)) + (stroke + (width 0) + (type default)) + (uuid "171bb763-3fea-5a8c-8a0b-6e7c0e564228")) + (global_label "LED1_A" + (shape bidirectional) + (at 375.92 199.39 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "fac1ac4c-7474-55c9-927c-eb59bb5acde1")) + (symbol + (lib_id "RadianPanel:D12") + (at 501.65 199.39 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "8581a420-1ba2-5d16-a609-c9a592c237c5") + (property "Reference" "D12" + (at 501.65 190.31 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "VOICE 3" + (at 501.65 208.47 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:LED_D3.0_P2.54" + (at 501.65 199.39 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "L-934GD" + (at 501.65 199.39 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "93846911-8b2d-5024-b8e6-3c4fde2f7fbb")) + (pin "2" + (uuid "83eb9c20-8928-5fe6-a52e-b6022580fc85")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/fe425aa9-89e9-5e5b-9592-3f1bdae47718" + (reference "D12") + (unit 1)))) + (property "Description" "3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." + (at 501.65 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "Kingbright" + (at 501.65 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 491.49 199.39) + (xy 486.41 199.39)) + (stroke + (width 0) + (type default)) + (uuid "1e559ea4-3e2c-5bcd-b3d8-95da1d197ced")) + (global_label "GND" + (shape bidirectional) + (at 486.41 199.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "4f08cd1f-5d88-58ac-83cb-08c37eca50ec")) + (wire + (pts + (xy 511.81 199.39) + (xy 516.89 199.39)) + (stroke + (width 0) + (type default)) + (uuid "1da79964-e68c-59a8-ac12-2853cf023a82")) + (global_label "LED2_A" + (shape bidirectional) + (at 516.89 199.39 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "2e856806-c28f-5e2f-a4ae-743b02dfb99c")) + (symbol + (lib_id "RadianPanel:D13") + (at 78.74 264.16 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "cb84da0a-7689-587d-8688-e97d2e4c3449") + (property "Reference" "D13" + (at 78.74 255.08 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "VOICE 4" + (at 78.74 273.24 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:LED_D3.0_P2.54" + (at 78.74 264.16 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "L-934GD" + (at 78.74 264.16 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "53f06f5d-2665-5ec2-8c1a-23d830d70e68")) + (pin "2" + (uuid "389c1e1e-baf0-52e3-a4e2-f321f578255e")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/fe425aa9-89e9-5e5b-9592-3f1bdae47718" + (reference "D13") + (unit 1)))) + (property "Description" "3 mm LED, anode pad 2, cathode pad 1. Mainboard already has series resistor. Set flange height with assembly jig; envelope is not seated LED height." + (at 78.74 264.16 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "Kingbright" + (at 78.74 264.16 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 68.58 264.16) + (xy 63.5 264.16)) + (stroke + (width 0) + (type default)) + (uuid "cfbefef9-8d7e-5fa0-a0da-146ea9c2bac7")) + (global_label "GND" + (shape bidirectional) + (at 63.5 264.16 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "c0e520e4-bf30-50e5-a765-ee9fcabef13c")) + (wire + (pts + (xy 88.9 264.16) + (xy 93.98 264.16)) + (stroke + (width 0) + (type default)) + (uuid "025358f0-b9cc-5e85-beec-64900091af12")) + (global_label "LED3_A" + (shape bidirectional) + (at 93.98 264.16 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "41855ab2-749e-5c76-a9c7-52324d9d6539")) + (text "No additional pot wiper RC or LED series resistors: these are already on the RADIAN mainboard." + (at 20 365 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "788a3fdc-0e51-59f7-8d4a-723b8b10eec3")) + (text "RV physical pin 1 = CCW/GND; physical pin 3 = CW/VREF25. This is not the main header pin order." + (at 20 373 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "6a3962b5-0d4b-5977-8162-19203822c196")) + (text "Encoder part changes to 20 mm shaft / 7 mm bushing. Match knob heights and verify turn direction." + (at 20 381 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "3b4643f5-8ec6-53ca-9005-596db171b081")) + (text "SW1 logic mapping depends on installed orientation and firmware. Mechanical tab pins are intentionally NC." + (at 20 389 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "c6eccb55-c407-59a5-baca-1cb3cb0fe48e"))) diff --git a/hardware/panel/reports/native/work/fp-lib-table b/hardware/panel/reports/native/work/fp-lib-table new file mode 100644 index 0000000..3487e2e --- /dev/null +++ b/hardware/panel/reports/native/work/fp-lib-table @@ -0,0 +1 @@ +(fp_lib_table (version 7) (lib (name "RadianPanel") (type "KiCad") (uri "${KIPRJMOD}/../library/RadianPanel.pretty") (options "") (descr "Project-local draft footprints; check against actual components"))) diff --git a/hardware/panel/reports/native/work/io.kicad_sch b/hardware/panel/reports/native/work/io.kicad_sch new file mode 100644 index 0000000..194e2f9 --- /dev/null +++ b/hardware/panel/reports/native/work/io.kicad_sch @@ -0,0 +1,1060 @@ +(kicad_sch + (version 20231120) + (generator "radian_panel_generator") + (uuid "32a0fbd8-9981-5a75-9f13-b39ca692f8b0") + (paper "A2") + (title_block + (title "03 | PATCH JACKS AND MIDI") + (date "2026-09-15") + (rev "P1 DRAFT") + (comment 1 "Native ERC, footprint verification and hardware testing REQUIRED")) + (lib_symbols + (symbol "RadianPanel:J301" + (pin_names + (offset 0.508)) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 7.62 0) + (effects + (font + (size 1.27 1.27)))) + (property "Value" "PITCH 0-5V" + (at 0 -7.62 0) + (effects + (font + (size 1.27 1.27)))) + (property "Footprint" "RadianPanel:WQP518MA_PJ398SM_Vertical" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (symbol "J301_0_1" + (rectangle + (start -10.16 5.08) + (end 10.16 -5.08) + (stroke + (width 0.254) + (type default)) + (fill + (type background)))) + (symbol "J301_1_1" + (pin passive line + (at -12.7 2.54 0) + (length 2.54) + (name "SLEEVE" + (effects + (font + (size 1.0 1.0)))) + (number "1" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 0.0 0) + (length 2.54) + (name "NORMAL" + (effects + (font + (size 1.0 1.0)))) + (number "2" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -2.54 0) + (length 2.54) + (name "TIP" + (effects + (font + (size 1.0 1.0)))) + (number "3" + (effects + (font + (size 1.0 1.0)))))) + (property "Description" "Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check." + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "QingPu / Thonk" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (symbol "RadianPanel:J302" + (pin_names + (offset 0.508)) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 7.62 0) + (effects + (font + (size 1.27 1.27)))) + (property "Value" "MOD" + (at 0 -7.62 0) + (effects + (font + (size 1.27 1.27)))) + (property "Footprint" "RadianPanel:WQP518MA_PJ398SM_Vertical" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (symbol "J302_0_1" + (rectangle + (start -10.16 5.08) + (end 10.16 -5.08) + (stroke + (width 0.254) + (type default)) + (fill + (type background)))) + (symbol "J302_1_1" + (pin passive line + (at -12.7 2.54 0) + (length 2.54) + (name "SLEEVE" + (effects + (font + (size 1.0 1.0)))) + (number "1" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 0.0 0) + (length 2.54) + (name "NORMAL" + (effects + (font + (size 1.0 1.0)))) + (number "2" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -2.54 0) + (length 2.54) + (name "TIP" + (effects + (font + (size 1.0 1.0)))) + (number "3" + (effects + (font + (size 1.0 1.0)))))) + (property "Description" "Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check." + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "QingPu / Thonk" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (symbol "RadianPanel:J303" + (pin_names + (offset 0.508)) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 7.62 0) + (effects + (font + (size 1.27 1.27)))) + (property "Value" "GATE" + (at 0 -7.62 0) + (effects + (font + (size 1.27 1.27)))) + (property "Footprint" "RadianPanel:WQP518MA_PJ398SM_Vertical" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (symbol "J303_0_1" + (rectangle + (start -10.16 5.08) + (end 10.16 -5.08) + (stroke + (width 0.254) + (type default)) + (fill + (type background)))) + (symbol "J303_1_1" + (pin passive line + (at -12.7 2.54 0) + (length 2.54) + (name "SLEEVE" + (effects + (font + (size 1.0 1.0)))) + (number "1" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 0.0 0) + (length 2.54) + (name "NORMAL" + (effects + (font + (size 1.0 1.0)))) + (number "2" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -2.54 0) + (length 2.54) + (name "TIP" + (effects + (font + (size 1.0 1.0)))) + (number "3" + (effects + (font + (size 1.0 1.0)))))) + (property "Description" "Vertical mono, grounded normal for inputs only. Sleeve=1, switched contact=2, tip=3. Imported supplier dimension drawing needs sample fit check." + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "QingPu / Thonk" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (symbol "RadianPanel:J304" + (pin_names + (offset 0.508)) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 7.62 0) + (effects + (font + (size 1.27 1.27)))) + (property "Value" "LINE L" + (at 0 -7.62 0) + (effects + (font + (size 1.27 1.27)))) + (property "Footprint" "RadianPanel:WQP518MA_PJ398SM_Vertical" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (symbol "J304_0_1" + (rectangle + (start -10.16 5.08) + (end 10.16 -5.08) + (stroke + (width 0.254) + (type default)) + (fill + (type background)))) + (symbol "J304_1_1" + (pin passive line + (at -12.7 2.54 0) + (length 2.54) + (name "SLEEVE" + (effects + (font + (size 1.0 1.0)))) + (number "1" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 0.0 0) + (length 2.54) + (name "NORMAL" + (effects + (font + (size 1.0 1.0)))) + (number "2" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -2.54 0) + (length 2.54) + (name "TIP" + (effects + (font + (size 1.0 1.0)))) + (number "3" + (effects + (font + (size 1.0 1.0)))))) + (property "Description" "Vertical mono, grounded normal for inputs only. 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verify effective capacitance at DC bias" + (at 78.74 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "" + (at 78.74 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 68.58 199.39) + (xy 63.5 199.39)) + (stroke + (width 0) + (type default)) + (uuid "fb275b2a-a4a0-5186-8932-99a07754850f")) + (global_label "VIN5" + (shape bidirectional) + (at 63.5 199.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "bcbb7647-f761-5c94-806d-64733254ca18")) + (wire + (pts + (xy 88.9 199.39) + (xy 93.98 199.39)) + (stroke + (width 0) + (type default)) + (uuid "7d02fb18-62a4-5c2f-8f7c-cd01c7af81ee")) + (global_label "GND" + (shape bidirectional) + (at 93.98 199.39 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "aee1a280-56c9-54b3-8dce-a38c356e82f7")) + (symbol + (lib_id "RadianPanel:C21") + (at 219.71 199.39 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "9b8308d0-0230-537b-ac42-dd90818e7824") + (property "Reference" "C21" + (at 219.71 190.31 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "1uF" + (at 219.71 208.47 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:C_0805" + (at 219.71 199.39 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "SELECT 1uF 16V X7R 0805" + (at 219.71 199.39 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "6e50762f-dbe7-5183-a3f2-3e67b26e1281")) + (pin "2" + (uuid "2a0766a4-f4c6-532f-b5b9-a346c9cbda78")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/a353e908-e1f3-5887-a37d-be1463de1afa" + (reference "C21") + (unit 1)))) + (property "Description" "16V X7R; verify effective capacitance at DC bias" + (at 219.71 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "" + (at 219.71 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 209.55 199.39) + (xy 204.47 199.39)) + (stroke + (width 0) + (type default)) + (uuid "92038c36-dd9c-5220-a51e-1a52eec72fb5")) + (global_label "VIN5" + (shape bidirectional) + (at 204.47 199.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "cccdfe0b-f559-5a35-9656-b7d81d1ee184")) + (wire + (pts + (xy 229.87 199.39) + (xy 234.95 199.39)) + (stroke + (width 0) + (type default)) + (uuid "3cbb3317-68fb-59ca-a17a-6af067d64ac8")) + (global_label "GND" + (shape bidirectional) + (at 234.95 199.39 180) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "c0dd7b7a-b0b2-5cab-99b7-bce53a19d519")) + (symbol + (lib_id "RadianPanel:TP4") + (at 360.68 199.39 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "9a57579e-c67c-5118-aa2a-a9574281fbeb") + (property "Reference" "TP4" + (at 360.68 190.31 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "VREF25" + (at 360.68 208.47 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:TestPoint_D2" + (at 360.68 199.39 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "PCB test pad" + (at 360.68 199.39 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "9fe26028-336f-51f2-be4d-0991fb7b7f4a")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/a353e908-e1f3-5887-a37d-be1463de1afa" + (reference "TP4") + (unit 1)))) + (property "Description" "Exposed soldermask aperture, no component." + (at 360.68 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "" + (at 360.68 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 350.52 199.39) + (xy 345.44 199.39)) + (stroke + (width 0) + (type default)) + (uuid "900a9d99-6875-542f-9e32-51802380b40a")) + (global_label "VREF25" + (shape bidirectional) + (at 345.44 199.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "0f806622-af09-57cc-8763-377aea8d2e98")) + (symbol + (lib_id "RadianPanel:TP5") + (at 501.65 199.39 0) + (unit 1) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "2d0eae80-797a-549c-a27f-4473fbcee434") + (property "Reference" "TP5" + (at 501.65 190.31 0) + (effects + (font + (size 1.6 1.6)))) + (property "Value" "MOD_BIPOLAR" + (at 501.65 208.47 0) + (effects + (font + (size 1.05 1.05)))) + (property "Footprint" "RadianPanel:TestPoint_D2" + (at 501.65 199.39 0) + (effects + (font + (size 1.0 1.0)) + hide)) + (property "MPN" "PCB test pad" + (at 501.65 199.39 0) + (effects + (font + (size 1 1)) + hide)) + (pin "1" + (uuid "fcd5c1a3-e915-52d2-bf6c-6f2e14641155")) + (instances + (project "radian_panel" + (path "/7d46cc62-3a7a-5bb5-ab56-ed22db4ad276/a353e908-e1f3-5887-a37d-be1463de1afa" + (reference "TP5") + (unit 1)))) + (property "Description" "Exposed soldermask aperture, no component." + (at 501.65 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "" + (at 501.65 199.39 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (wire + (pts + (xy 491.49 199.39) + (xy 486.41 199.39)) + (stroke + (width 0) + (type default)) + (uuid "a9e2ce91-6b3e-52c3-8c5e-436ed2905da9")) + (global_label "MOD_BIPOLAR" + (shape bidirectional) + (at 486.41 199.39 0) + (effects + (font + (size 1.0 1.0)) + (justify right)) + (uuid "6654fa26-404b-5d1e-adba-648711604406")) + (text "JP1 is an SPDT configuration switch: one throw selects direct unipolar MOD_RAW; the other selects MOD_BIPOLAR." + (at 20 365 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "7b4fd508-b5b2-5b07-a689-d7b3c79560be")) + (text "OPTIONAL: shunt 2-3 = bipolar conversion. Ideal Vout = 0.5*Vin + VREF25. -5/0/+5 V -> 0/2.5/5 V." + (at 20 373 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "80fe7b41-6f2a-594b-9af8-0ccef96fee07")) + (text "5 V op-amp cannot reach exact rails under load. Endpoints, tolerance, saturation and calibration need testing." + (at 20 381 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "bfcafe52-723e-50e4-8f4c-e66cc98f2f45")) + (text "Do not rescale the PITCH input implicitly. Bipolar MOD requires a matching firmware range/zero configuration." + (at 20 389 0) + (effects + (font + (size 1.35 1.35)) + (justify left top)) + (uuid "7bbf9558-4806-565e-baf8-58c797d11d3b"))) diff --git a/hardware/panel/reports/native/work/power.kicad_sch b/hardware/panel/reports/native/work/power.kicad_sch new file mode 100644 index 0000000..eab2ec4 --- /dev/null +++ b/hardware/panel/reports/native/work/power.kicad_sch @@ -0,0 +1,4449 @@ +(kicad_sch + (version 20231120) + (generator "radian_panel_generator") + (uuid "c6d6c3a3-edd3-53cf-85a7-68fcc04adacf") + (paper "A2") + (title_block + (title "01 | POWER INPUTS AND 5 V CONVERTER") + (date "2026-09-15") + (rev "P1 DRAFT") + (comment 1 "Native ERC, footprint verification and hardware testing REQUIRED")) + (lib_symbols + (symbol "RadianPanel:J200" + (pin_names + (offset 0.508)) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 16.509999999999998 0) + (effects + (font + (size 1.27 1.27)))) + (property "Value" "61201021621" + (at 0 -16.509999999999998 0) + (effects + (font + (size 1.27 1.27)))) + (property "Footprint" "RadianPanel:Wurth_61201021621_Exact_B" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (symbol "J200_0_1" + (rectangle + (start -10.16 13.969999999999999) + (end 10.16 -13.969999999999999) + (stroke + (width 0.254) + (type default)) + (fill + (type background)))) + (symbol "J200_1_1" + (pin passive line + (at -12.7 11.43 0) + (length 2.54) + (name "1" + (effects + (font + (size 1.0 1.0)))) + (number "1" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 8.89 0) + (length 2.54) + (name "2" + (effects + (font + (size 1.0 1.0)))) + (number "2" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 6.35 0) + (length 2.54) + (name "3" + (effects + (font + (size 1.0 1.0)))) + (number "3" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 3.81 0) + (length 2.54) + (name "4" + (effects + (font + (size 1.0 1.0)))) + (number "4" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 1.27 0) + (length 2.54) + (name "5" + (effects + (font + (size 1.0 1.0)))) + (number "5" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -1.27 0) + (length 2.54) + (name "6" + (effects + (font + (size 1.0 1.0)))) + (number "6" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -3.81 0) + (length 2.54) + (name "7" + (effects + (font + (size 1.0 1.0)))) + (number "7" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -6.35 0) + (length 2.54) + (name "8" + (effects + (font + (size 1.0 1.0)))) + (number "8" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -8.89 0) + (length 2.54) + (name "9" + (effects + (font + (size 1.0 1.0)))) + (number "9" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -11.43 0) + (length 2.54) + (name "10" + (effects + (font + (size 1.0 1.0)))) + (number "10" + (effects + (font + (size 1.0 1.0)))))) + (property "Description" "Module-side 10-pin: 1/2=-12 NC, 3-8=GND, 9/10=+12. Use 16-to-10 cable to bus. Red stripe at pins 1/2; verify both cable ends. No bus +5/CV/gate connections." + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (property "Manufacturer" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide))) + (symbol "RadianPanel:J201" + (pin_names + (offset 0.508)) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 7.62 0) + (effects + (font + (size 1.27 1.27)))) + (property "Value" "22-27-2021" + (at 0 -7.62 0) + (effects + (font + (size 1.27 1.27)))) + (property "Footprint" "RadianPanel:Molex_22-27-2021_J201_B" + (at 0 0 0) + (effects + (font + (size 1.27 1.27)) + hide)) + (symbol "J201_0_1" + (rectangle + (start -10.16 5.08) + (end 10.16 -5.08) + (stroke + (width 0.254) + (type default)) + (fill + (type background)))) + (symbol "J201_1_1" + (pin passive line + (at -12.7 1.27 0) + (length 2.54) + (name "1" + (effects + (font + (size 1.0 1.0)))) + (number "1" + (effects + (font + (size 1.0 1.0))))) + (pin passive line + (at -12.7 -1.27 0) + (length 2.54) + (name "2" + (effects + (font + (size 1.0 1.0)))) + (number "2" + (effects + (font + (size 1.0 1.0)))))) + (property "Description" "From panel-mounted centre-positive 12 V DC inlet in dock. NOT a 5 V inlet. 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"J106.2", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 32, + "seconds": 0.41 + }, + { + "net": "LED0_A", + "from": "D10.2", + "to": "J111.2", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 521, + "seconds": 0.48 + }, + { + "net": "POT_DECAY_RAW", + "from": "RV2.2", + "to": "J107.2", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 50, + "seconds": 0.4 + }, + { + "net": "POT_TIMBRE_RAW", + "from": "RV3.2", + "to": "J108.2", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 49, + "seconds": 0.41 + }, + { + "net": "ENC_SW_RAW", + "from": "ENC1.S1", + "to": "J109.4", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 683, + "seconds": 0.45 + }, + { + "net": "LED1_A", + "from": "D11.2", + "to": "J111.3", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 375, + "seconds": 0.48 + }, + { + "net": "cv_select", + "from": "SW1.2", + "to": "J110.2", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 943, + "seconds": 0.42 + }, + { + "net": "PROGRAM_B", + "from": "SW3.1", + "to": "J103.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 225, + "seconds": 0.44 + }, + { + "net": "PROGRAM_B", + "from": "SW3.1", + "to": "SW3.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 18, + "seconds": 0.44 + }, + { + "net": "reset_n", + "from": "SW4.1", + "to": "J104.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 468, + "seconds": 0.44 + }, + { + "net": "reset_n", + "from": "SW4.1", + "to": "SW4.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 18, + "seconds": 0.41 + }, + { + "net": "ENC_B_RAW", + "from": "ENC1.B", + "to": "J109.3", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 1751, + "seconds": 0.44 + }, + { + "net": "PITCH_IN", + "from": "J301.3", + "to": "J112.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 3503, + "seconds": 0.5 + }, + { + "net": "LED2_A", + "from": "D12.2", + "to": "J111.4", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 4184, + "seconds": 0.54 + }, + { + "net": "GATE_IN", + "from": "J303.3", + "to": "J114.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 2527, + "seconds": 0.52 + }, + { + "net": "ENC_A_RAW", + "from": "ENC1.A", + "to": "J109.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 717, + "seconds": 0.47 + }, + { + "net": "LED3_A", + "from": "D13.2", + "to": "J111.5", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 7658, + "seconds": 0.55 + }, + { + "net": "LINE_L", + "from": "J304.3", + "to": "J105.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 8014, + "seconds": 0.55 + }, + { + "net": "MOD_RAW", + "from": "JP1.1", + "to": "J302.3", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 1439, + "seconds": 0.53 + }, + { + "net": "MOD_RAW", + "from": "R20.1", + "to": "JP1.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 427, + "seconds": 0.47 + }, + { + "net": "LINE_R", + "from": "J305.3", + "to": "J105.3", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 16430, + "seconds": 0.6 + }, + { + "net": "V3V3", + "from": "J202.1", + "to": "J102.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 113, + "seconds": 0.53 + }, + { + "net": "V3V3", + "from": "J110.1", + "to": "J202.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 17668, + "seconds": 0.64 + }, + { + "net": "V3V3", + "from": "SW1.3", + "to": "J110.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 2096, + "seconds": 0.57 + }, + { + "net": "VREF25", + "from": "RV1.3", + "to": "J106.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 63, + "seconds": 0.54 + }, + { + "net": "VREF25", + "from": "RV2.3", + "to": "RV1.3", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 1498, + "seconds": 0.47 + }, + { + "net": "VREF25", + "from": "J107.1", + "to": "RV2.3", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 77, + "seconds": 0.54 + }, + { + "net": "VREF25", + "from": "J108.1", + "to": "J107.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 2217, + "seconds": 0.59 + }, + { + "net": "VREF25", + "from": "RV3.3", + "to": "J108.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 51, + "seconds": 0.52 + }, + { + "net": "VREF25", + "from": "TP4.1", + "to": "J108.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 7493, + "seconds": 0.44 + }, + { + "net": "VREF25", + "from": "U2.3", + "to": "TP4.1", + "width": 0.25, + "success": true, + "reason": null, + "expanded": 812, + "seconds": 0.31 + } +] \ No newline at end of file diff --git a/hardware/panel/source/build_cad.py b/hardware/panel/source/build_cad.py new file mode 100644 index 0000000..3446553 --- /dev/null +++ b/hardware/panel/source/build_cad.py @@ -0,0 +1,233 @@ +#!/usr/bin/env python3 +"""Panel P1 reference CAD from the exact PCB graph. No manufacturer STEP is asserted. +Optional --previous points to the unpacked Rev F.1 CAD package to integrate the case. +""" +from __future__ import annotations +import argparse,json,math,sys +from pathlib import Path +import cadquery as cq +from OCP.Bnd import Bnd_Box +from OCP.BRepBndLib import BRepBndLib +from design_data import ROOT,PARTS,OUTLINE,WINDOWS,MOUNTS,allpads,CONFIG +CAD=ROOT/'cad';(CAD/'models').mkdir(parents=True,exist_ok=True) + +def rect(x,y,w,h,z,t): + return cq.Workplane('XY').box(w,h,t,centered=(False,False,False)).translate((x,y,z)).val() +def cyl(x,y,z,r,h):return cq.Workplane('XY').circle(r).extrude(h).translate((x,y,z)).val() +def ring(x,y,z,ro,ri,h):return cyl(x,y,z,ro,h).cut(cyl(x,y,z-.01,ri,h+.02)) +def comp(ss):return cq.Compound.makeCompound(list(ss)) +def outline(poly,z,t):return cq.Workplane('XY').polyline(poly).close().extrude(t).translate((0,0,z)).val() +def bb(s): + b=Bnd_Box();BRepBndLib.AddOptimal_s(s.wrapped,b,False,False);return list(b.Get()) +def overlap(a,b): + x=bb(a);y=bb(b) + if any(min(x[i+3],y[i+3])-max(x[i],y[i])<1e-6 for i in range(3)):return 0. + return abs(a.intersect(b).Volume()) +def place(s,p): + if p['side']=='B':s=s.rotate((0,0,0),(0,1,0),180) + s=s.rotate((0,0,0),(0,0,1),p['angle']) + return s.translate((p['x'],p['y'],-8 if p['side']=='F' else -9.6)) +def localmodel(p): + f=p['fp'];name=f['name'];w,h=f['body'];z=f['height'];out={} + if name.startswith('TestPoint'):return {} + if name.startswith('Bourns_PTV'): + # Real PTV09A-series mechanical CAD, aligned to the selected + # PTV09A-4020F-B103 rear-mount footprint. Keep shaft/pins split so the + # enclosure clearance validator can still test the physical shaft. + s=cq.importers.importStep(str(CAD/'models'/'Bourns_PTV09A_4020F_family_actual.step')).val() + ss=s.Solids() + out['body']=comp([ss[0],ss[5]]) + out['shaft']=ss[1] + out['pins']=comp(ss[2:5]) + return out + # Production-selected connector/switch models. These STEP files are aligned to + # the native footprint local origin; B-side placement is applied by place(). + exact_models={ + 'Wurth_61201021621_Exact_B':'Wurth_61201021621_native.step', + 'Molex_22-27-2021_J201_B':'Molex_22-27-2021_centered.step', + 'Molex_22-27-2021_J306_B':'Molex_22-27-2021_centered.step', + 'Molex_22-27-2061_J202_B':'Molex_22-27-2061_centered.step', + 'Wurth_450301014042_Exact_B':'Wurth_450301014042_native.step', + 'WQP518MA_PJ398SM_Vertical':'QingPu_PJ398SM_Knurl_actual.step', + 'SW_PUSH_6x6_P6.5x4.5':'Omron_B3F_1000_centered.step', + 'TI_DDC0006A_SOT23_6':'TPS54302_SOT23_6_package.step', + 'SOIC8_3.9x4.9_P1.27':'OPA2192_SOIC8_package.step', + 'SOT23_BAT54S':'BAT54S_SOT23_package.step', + 'Fuse_1206':'Fuse_1206_package.step', + 'D_SMB':'D_SMB_package.step', + 'R_0603':'R_0603_package.step', + 'C_0603':'C_0603_package.step', + 'C_0805':'C_0805_package.step', + 'C_1210':'C_1210_package.step', + 'LED_D3.0_P2.54':'Kingbright_L934GD_package_green_centered.step', + } + if name in exact_models: + out['body']=cq.importers.importStep(str(CAD/'models'/exact_models[name])).val() + return out + if name.startswith('LED_'): + out['body']=comp([cyl(0,0,7.,1.9,1),cyl(0,0,8.,1.5,3.5),cq.Solid.makeSphere(1.5,cq.Vector(0,0,11.5),angleDegrees1=0,angleDegrees2=90)]) + elif name.startswith('Header_'): + out['body']=rect(-w/2,-h/2,w,h,0,2.54) + elif name.startswith('Stack_2x10'): + # Use the Samtec-drawing-derived IPS1-110-01-L-D model, including all + # 20 socket towers and through-hole tails. This replaces the old generic + # rectangular connector envelope in the mechanical assembly. + model_path=ROOT.parent/'stack'/'models'/'Samtec_IPS1-110-01-L-D_drawing_reference.step' + out['body']=cq.importers.importStep(str(model_path)).val() + elif name.startswith('IDC_'): + out['body']=rect(-w/2,-h/2,w,h,0,z).cut(rect(-3,-h/2+1.5,6,h-3,2,z)) + elif name.startswith('WQP'): + # Underbody clearance is a separate NPTH in the real board. + out['body']=rect(-w/2,-h/2,w,h,0,z) + out['bushing']=ring(0,0,9,3,1.8,5.5) + elif name.startswith('Bourns_PTV'): + out['body']=rect(-w/2,-h/2,w,h,0,z) + out['shaft']=cyl(0,0,z,3,20).cut(rect(1.5,-4,3,8,z,20.1)) + elif name.startswith('Bourns_PEC'): + out['body']=rect(-w/2,-h/2,w,h,0,z) + out['bushing']=cyl(0,0,6.5,3.5,7) + out['shaft']=cyl(0,0,13.5,3,13).cut(rect(1.5,-4,3,8,13.5,13.1)) + elif name.startswith('E_Switch'): + out['body']=rect(-w/2,-h/2,w,h,0,z) + out['bushing']=cyl(0,0,z,3.175,6.35) + out['shaft']=cyl(0,0,z+6.35,1.46,10.41) + else:out['body']=rect(-w/2,-h/2,w,h,0,max(z,.2)) + # Simple pin references, not manufacturer lead-form geometry. + pins=[] + for q in f['pads']: + if q['kind']=='np_thru_hole':continue + if q['kind']=='thru_hole': + if q['n'].startswith('MP'): + d=q['drill'];dx,dy=d if isinstance(d,list) else (d,d) + pins.append(rect(q['x']-dx*.32,q['y']-dy*.32,dx*.64,dy*.64,-2.5,2.6)) + else:pins.append(cyl(q['x'],q['y'],-2.6,.28, (11.1 if name.startswith(('Header_','IDC_')) else 10.2 if name.startswith('LED_') else 2.7))) + else:pins.append(rect(q['x']-q['sx']*.36,q['y']-q['sy']*.36,q['sx']*.72,q['sy']*.72,-.025,.15)) + if pins:out['pins']=comp(pins) + return out + +def board_shape(): + s=outline(OUTLINE,-9.6,1.6) + for q in WINDOWS:s=s.cut(outline(q,-9.7,1.8)) + tools=[] + for x,y,d in MOUNTS:tools.append(cyl(x,y,-9.7,d/2,1.8)) + for q in allpads(): + d=q['drill'] + if d is None:continue + if isinstance(d,list): + angle=q['angle']+(90 if d[1]>d[0] else 0) + tool=cq.Workplane('XY').slot2D(max(d),min(d),angle).extrude(1.8).translate((q['X'],q['Y'],-9.7)).val() + else:tool=cyl(q['X'],q['Y'],-9.7,d/2,1.8) + tools.append(tool) + return s.cut(comp(tools)).clean() + +def render(items,path,target=(105,64,-8),camera=(270,-200,240),scale=96,up=(0,0,1)): + import vtk + rr=vtk.vtkRenderer();rr.SetBackground(.924,.920,.895);rr.SetUseFXAA(True) + win=vtk.vtkRenderWindow();win.SetOffScreenRendering(1);win.SetSize(1800,1250);win.SetMultiSamples(0);win.AddRenderer(rr) + for name,(s,col) in items.items(): + mapper=vtk.vtkPolyDataMapper();mapper.SetInputData(s.toVtkPolyData(.05,.18,True));mapper.ScalarVisibilityOff() + a=vtk.vtkActor();a.SetMapper(mapper);pr=a.GetProperty();pr.SetColor(*tuple(int(col.lstrip('#')[i:i+2],16)/255 for i in (0,2,4)));pr.SetAmbient(.25);pr.SetDiffuse(.7);pr.SetSpecular(.2);pr.SetSpecularPower(30);rr.AddActor(a) + rr.AutomaticLightCreationOff() + for xyz,power in [((-100,230,360),.9),((330,-200,250),.65),((100,40,-250),.45)]: + l=vtk.vtkLight();l.SetLightTypeToSceneLight();l.SetPosition(*xyz);l.SetFocalPoint(*target);l.SetIntensity(power);rr.AddLight(l) + cam=rr.GetActiveCamera();cam.SetPosition(*camera);cam.SetFocalPoint(*target);cam.SetViewUp(*up);cam.ParallelProjectionOn();cam.SetParallelScale(scale);rr.ResetCameraClippingRange();win.Render() + im=vtk.vtkWindowToImageFilter();im.SetInput(win);im.SetInputBufferTypeToRGB();im.ReadFrontBufferOff();im.Update();wr=vtk.vtkPNGWriter();wr.SetFileName(str(path));wr.SetInputConnection(im.GetOutputPort());wr.Write();win.Finalize() + +def export_assy(items,path,name): + assy=cq.Assembly(name=name) + for nm,(s,c) in items.items(): + col=tuple(int(c.lstrip('#')[i:i+2],16)/255 for i in (0,2,4));assy.add(s,name=nm,color=cq.Color(*col)) + assy.export(str(path));return assy + +def main(): + ap=argparse.ArgumentParser();ap.add_argument('--previous',type=Path);a=ap.parse_args() + items={};shapes={};board=board_shape();items['P1_BOARD']=(board,'#265944');shapes['P1_BOARD']=board + saved=set() + for p in PARTS: + local=localmodel(p);nn=p['fp']['name'] + if local and nn not in saved: + cq.exporters.export(comp(local.values()),str(CAD/'models'/(nn+'.step')));saved.add(nn) + if not local and nn not in saved: + # A zero-height copper pad has no physical model; the PCB still carries the net. + cq.exporters.export(cyl(0,0,0,.8,.025),str(CAD/'models'/(nn+'.step')));saved.add(nn) + for k,s in local.items(): + nm=p['ref']+'_'+k;ss=place(s,p);color='#A3A899' if k in ['pins','bushing','shaft'] else '#ADC873' if p['ref'] in ['D10','D11','D12','D13'] else '#30362F' + if p['ref'].startswith(('R','C')) and k=='body':color='#7E7862' + items[nm]=(ss,color);shapes[nm]=ss + print('Board and component references built',flush=True) + cq.exporters.export(board,str(CAD/'RADIAN_P1_bare_board.step')) + cq.exporters.export(board,str(CAD/'RADIAN_P1_fit_template.stl'),tolerance=.04,angularTolerance=.14) + export_assy(items,CAD/'RADIAN_P1_populated_reference.step','RADIAN_PANEL_P1_REFERENCE') + render(items,ROOT/'previews'/'panel_pcb_3d.png') + report={'scope':'Reference-envelope CAD only. No manufacturer STEP or component lead-form certification. Zero nominal intersections is not fit approval.','board_valid':board.isValid(),'board_solids':len(board.Solids()),'board_bounds_mm':bb(board),'component_reference_count':len(PARTS),'body_only_mechanical_checks':{},'reference_parts_valid':all(s.isValid() for s in shapes.values()),'mainboard_modified':False,'native_KiCad_3D_import':'NOT RUN; local model alignments require native 3D viewer validation'} + if a.previous: + old=a.previous;step=old/'step';load=lambda n:cq.importers.importStep(str(step/(n+'.step'))).val() + keep=['panel','grille','patch_strip','midi_insert','mode_blank','rear_guard','desktop_dock','dock_nuts_reference','corner_support_BL','corner_support_BR','corner_support_TL','corner_support_TR','spacers_reference','midi_support','midi_socket_reference','engraving_reference','accent_reference','patch_ink_reference','mode_ink_reference','screw_heads_reference'] + case={n:load(n) for n in keep} + case['panel']=case['panel'].cut(comp([cyl(x,y,-.1,1.35,2.2) for x,y in [(24,14),(55,14)]])) + case['mode_blank']=case['mode_blank'].cut(cyl(150.5,84.5,1.9,3.3,2.2)) + newmounts=comp([ring(x,y,-8,2.5,1.1,8) for x,y,d in MOUNTS]);case['P1_panel_standoffs_REFERENCE']=newmounts + case['P1_encoder_rear_spacer']=ring(42,43,-1.5,5,3.6,1.5) + case['P1_jack_rear_shims']=comp([ring(186.5,y,1,4.5,3.1,1) for y in [99,81,63,45,27]]) + case['P1_mode_rear_spacer']=ring(150.5,84.5,.89,5,3.3,1.11) + case['P1_encoder_nut_REFERENCE']=comp([ring(42,43,2,6,3.6,.5),ring(42,43,2.5,5,3.6,2)]) + case['P1_jack_nuts_REFERENCE']=comp([ring(186.5,y,4,4.5,3.1,.5).fuse(ring(186.5,y,4.5,4.3,3.1,1.5)) for y in [99,81,63,45,27]]) + case['P1_mode_nut_REFERENCE']=ring(150.5,84.5,4,4.5,3.3,2) + # Knob references only, with a deeper shaft cavity for the revised encoder. + knobs=[];markers=[] + for x,y,r in [(42,84,11.5),(80,84,11.5),(118,84,11.5),(42,43,13)]: + knobs.append(cyl(x,y,6,r,16).cut(cyl(x,y,5.9,3.7,14.6))) + markers.append(rect(x-.5,y+r-4,1,3,22.01,.05)) + case['P1_knobs_REFERENCE']=comp(knobs);case['P1_markers_REFERENCE']=comp(markers) + for n,s in case.items(): + color=('#874B40' if n=='panel' else '#D1EB1A' if n=='accent_reference' else '#DDDCCD' if n in ['engraving_reference','patch_ink_reference','mode_ink_reference','P1_markers_REFERENCE'] else '#A3A899' if any(k in n for k in ['nut','spacer','standoff']) else '#292F2A') + items[n]=(s,color) + # Export updated flat parts; existing dock remains unchanged. + for n in ['panel','mode_blank','P1_encoder_rear_spacer','P1_jack_rear_shims','P1_mode_rear_spacer']: + cq.exporters.export(case[n],str(CAD/(n+'.step'))) + print('Importing unchanged mainboard for fit checks',flush=True) + mainboard=cq.importers.importStep(str(old/'references'/'pcb_source_aligned.step')).val();items['MAINBOARD_UNCHANGED']=(mainboard,'#2E5745') + main_solids=[(q,bb(q)) for q in mainboard.Solids()] + print('Imported main solids',len(main_solids),flush=True) + def overlap_main(s): + b=bb(s);total=0. + for q,d in main_solids: + if all(min(b[i+3],d[i+3])-max(b[i],d[i])>1e-6 for i in range(3)):total+=abs(s.intersect(q).Volume()) + return total + tested={'new_board':board} + for n,s in shapes.items(): + if n!='P1_BOARD' and not n.endswith('_pins'):tested[n]=s + # Check the new card and all bodies against prior enclosure parts and the mainboard. + clashes=[] + for n,s in tested.items(): + print('Fit checking',n,flush=True) + for k in ['panel','grille','patch_strip','midi_insert','mode_blank','rear_guard','desktop_dock','corner_support_BL','corner_support_BR','corner_support_TL','corner_support_TR','midi_support','midi_socket_reference']: + v=overlap(s,case[k]) + if v>1e-4:clashes.append({'new':n,'existing':k,'volume_mm3':round(v,5)}) + v=overlap_main(s) + if v>1e-4:clashes.append({'new':n,'existing':'MAINBOARD','volume_mm3':round(v,5)}) + report['body_only_mechanical_checks']={'positive_volume_intersections':clashes,'exclusions':['leads, solder fillets, cables, fastener threads, torques and inserted plugs','DIN support is retained as a provisional bracket; its socket retention without the former carrier PCB is not validated','generic mating headers are separately bounded, not exact purchased assemblies']} + mating=[] + for p in PARTS: + if p['side']=='B' and p['ref'].startswith('J') and p['ref']!='JP1': + w,h=p['fp']['body'];s=rect(p['x']-w/2-.4,p['y']-h/2-.5,w+.8,h+1,-25.6,16) + # Non-shrouded single-row mates are represented by their width, not wire bend volume. + v=overlap_main(s) + if v>1e-4:mating.append({'reference':p['ref'],'volume_mm3':round(v,5)}) + report['assumed_16mm_panel_header_envelope_vs_mainboard']=mating + print('New fit clashes:',clashes,'mated clashes:',mating,flush=True) + print('Exporting desktop fit-study STEP',flush=True) + export_assy(items,CAD/'RADIAN_P1_desktop_fit_study.step','RADIAN_P1_DESKTOP_FIT_STUDY') + render(items,ROOT/'previews'/'desktop_fit_study.png',target=(101,64,-16),camera=(310,-230,300),scale=110) + # Side-by-side geometry is not faked: lift panel and front controls +60, board +35. + exploded={} + for n,(s,c) in items.items(): + if n in ['desktop_dock','dock_nuts_reference','MAINBOARD_UNCHANGED','rear_guard','spacers_reference'] or n.startswith('corner_support'):dz=0 + elif n in shapes:dz=40 + else:dz=65 + exploded[n]=(s.translate((0,0,dz)),c) + render(exploded,ROOT/'previews'/'stack_exploded.png',target=(101,64,15),camera=(345,-250,245),scale=150) + report['desktop_dock_geometry']='unchanged from Rev F.1; inlet cutout, strain relief and feet remain provisional' + report['panel_changes']=['two new M2.5 clearance holes at 24,14 and 55,14','6.6 mm mode-switch bore in existing raised insert','existing shaft and jack locations retained'] + (ROOT/'reports'/'cad_fit_checks.json').write_text(json.dumps(report,indent=2));print('CAD done',flush=True) +if __name__=='__main__':main() diff --git a/hardware/panel/source/check_placement.py b/hardware/panel/source/check_placement.py new file mode 100644 index 0000000..f2b2f61 --- /dev/null +++ b/hardware/panel/source/check_placement.py @@ -0,0 +1,18 @@ +import json +from design_data import * +from export_ecad import pad_shape,board_shape +from shapely.geometry import Polygon +P=allpads();G=[pad_shape(p) for p in P];bd=board_shape();viol=[] +for i,p in enumerate(P): + if p['kind']=='np_thru_hole':continue + if not bd.buffer(.01).covers(G[i]):viol.append({'type':'pad_edge','pad':p['ref']+'.'+p['n'],'overlap_area':G[i].difference(bd).area}) + for j in range(i): + q=P[j] + common=(p['kind']!='smd' or q['kind']!='smd' or p['side']==q['side']) + if not common:continue + if p['net'] and p['net']==q['net']:continue + if q['kind']=='np_thru_hole':minc=.25 + else:minc=.20 + d=G[i].distance(G[j]) + if d=32V',x,y,chip2('Fuse_1206','1206'),{'1':a,'2':b},block='power',mpn='SELECT 2 A >=32 V 1206 fuse',notes='Final fuse MPN, surge rating, derating and TVS coordination are an explicit release gate.') +for ref,x,y,a in [('D1',44,65,'RACK_FUSED'),('D2',35,59,'DESKTOP_FUSED')]: + add(ref,'SS54 / OR',x,y,chip2('D_SMB','SMB'),{'1':'VRAW','2':a},block='power',mpn='SS54-E3/57T',maker='Vishay',notes='Pad 1 cathode VRAW, pad 2 anode fused source. Diode OR, no priority, shared ground. Measure worst-case diode temperature.') +add('D3','SMBJ15A',25,46,chip2('D_SMB','SMB'),{'1':'VRAW','2':'GND'},block='power',mpn='SMBJ15A-E3/52',maker='Vishay',notes='Unidirectional input TVS. Verify source fault energy and fuse coordination before any fault test.') +# TPS54302 topology follows TI 5V/3A application. Footprint top-view pin numbering. +tpsfp=fp([sm(1,-1.1,.95,1.0,.6,'GND'),sm(2,-1.1,0,1.,.6,'SW'),sm(3,-1.1,-.95,1.,.6,'VIN'),sm(4,1.1,-.95,1.,.6,'FB'),sm(5,1.1,0,1.,.6,'EN'),sm(6,1.1,.95,1.,.6,'BOOT')],[1.6,2.9],1.1,'TI_DDC0006A_SOT23_6') +add('U1','TPS54302DDCR',34,25,tpsfp,{'1':'GND','2':'SW','3':'VRAW','4':'FB','5':'EN','6':'BOOT'},block='power',mpn='TPS54302DDCR',maker='Texas Instruments',notes='3 A IC rating is a design target, not validated system delivery. TI March 2026 datasheet 5 V reference circuit.') +indfp=fp([sm(1,-2.95,0,2.5,3.5),sm(2,2.95,0,2.5,3.5)],[7.3,6.6],5.,'Bourns_SRP7050TA') +add('L1','10uH 4A / Isat7.5A',26,25,indfp,{'1':'VIN5','2':'SW'},block='power',mpn='SRP7050TA-100M',maker='Bourns',notes='4 A Irms / 7.5 A Isat at stated datasheet conditions; temperature rise needs testing.') +capacitor('C1','10uF',31,18,'VRAW',size='1210',rating='50V X7R') +capacitor('C2','100nF',32,21.5,'VRAW',angle=270,rating='50V X7R') +capacitor('C3','100nF',34,29,'BOOT','SW',rating='16V X7R') +capacitor('C4','22uF',23,33,'VIN5',angle=90,size='1210',rating='25V X7R') +capacitor('C5','22uF',29,33,'VIN5',angle=90,size='1210',rating='25V X7R') +resistor('R1','100k',39.5,27,'FF_TOP','FB') +resistor('R2','13.3k',39,20,'FB','GND') +resistor('R3','511k',46,23,'VRAW','EN',angle=90) +resistor('R4','105k',43,19,'EN','GND') +resistor('R5','49.9',39,32,'VIN5','FF_TOP') +capacitor('C6','75pF',43,27,'FF_TOP','FB',rating='50V C0G') +capacitor('C7','10uF',43,59,'VRAW',size='1210',rating='50V X7R') + +# Optional bipolar MOD: Vout = 0.5*Vin + buffered mainboard VREF25. +# Default shunt 1-2 bypasses this stage; no default firmware/voltage convention change. +add('JP1','450301014042',165.5,88,exact_mod_switch(),{'1':'MOD_IN','2':'MOD_BIPOLAR','3':'MOD_RAW'},'B',block='mod',mpn='450301014042',maker='Wurth Elektronik',notes='Actual SPDT configuration switch replaces the removable shunt. One throw selects direct unipolar MOD_RAW; the other selects MOD_BIPOLAR. NOT the front MODE switch.') +opafp=fp([sm(i,-2.7,(2.5-i)*1.27,1.55,.6,n) for i,n in enumerate(['OUTA','INA-','INA+','V-'],1)]+[sm(i,2.7,(i-6.5)*1.27,1.55,.6,n) for i,n in zip(range(5,9),['INB+','INB-','OUTB','V+'])],[3.9,4.9],1.75,'SOIC8_3.9x4.9_P1.27') +add('U2','OPA2192ID',151,67,opafp,{'1':'VREF_BUF','2':'VREF_BUF','3':'VREF25','4':'GND','5':'MOD_SUM','6':'MOD_FB','7':'MOD_BIPOLAR','8':'VIN5'},block='mod',mpn='OPA2192ID',maker='Texas Instruments',notes='A buffers VREF25. B is non-inverting gain 2. 5 V single supply, output headroom limits rail endpoints; not rail-perfect mapping.') +resistor('R20','200k',164,75,'MOD_RAW','MOD_SUM',block='mod',tol='0.1%') +resistor('R21','100k',158,75,'VREF_BUF','MOD_SUM',block='mod',tol='0.1%') +resistor('R22','200k',164,71,'MOD_SUM','GND',block='mod',tol='0.1%') +resistor('R23','10k',159.5,57,'MOD_FB','GND',block='mod',tol='0.1%') +resistor('R24','10k',163,59,'MOD_BIPOLAR','MOD_FB',block='mod',tol='0.1%') +sotfp=fp([sm(1,-1.,.95,1.0,.6),sm(2,-1.,-.95,1.,.6),sm(3,1.,0,1.,.6)],[1.4,2.9],1.1,'SOT23_BAT54S') +add('D4','BAT54S',166,65,sotfp,{'1':'GND','2':'VIN5','3':'MOD_SUM'},block='mod',mpn='BAT54S,215',maker='Nexperia',notes='Series diode pair clamp: 1=bottom anode, 2=top cathode, 3=junction. Verify powered and unpowered fault behavior.') +capacitor('C20','100nF',157,69,'VIN5',block='mod',rating='16V X7R') +capacitor('C21','1uF',149,74,'VIN5',block='mod',size='0805',rating='16V X7R') + +# Internal service access. No new panel holes or user-facing service button fiction. +add('J202','22-27-2061',131,29,exact_6pin(),{str(i+1):n for i,n in enumerate(MAP[2])},'B',block='service',mpn='22-27-2061',maker='Molex',notes='Exact KK-254 6-circuit friction-lock service header; pin-for-pin to the JTAG nets already carried through J101/J18. No level conversion; validate JTAG frequency.') +buttonfp=fp([pad('1',-3.25,-2.25,1.8,1.8,1),pad('1',-3.25,2.25,1.8,1.8,1),pad('2',3.25,-2.25,1.8,1.8,1),pad('2',3.25,2.25,1.8,1.8,1)],[6,6],4.3,'SW_PUSH_6x6_P6.5x4.5') +add('SW3','PROGRAM / SERVICE',118.4,25,buttonfp,{'1':'PROGRAM_B','2':'GND'},'B',block='service',mpn='B3F-1000',maker='Omron',notes='Internal service push button, accessible after module removal.') +add('SW4','RESET / SERVICE',146,26,buttonfp,{'1':'reset_n','2':'GND'},'B',block='service',mpn='B3F-1000',maker='Omron') +# Named probe pads. 5V test point is intentionally before the direct-stack VIN5 feed to the mainboard. +for i,(x,y,net) in enumerate([(25,42,'GND'),(29,42,'VIN5'),(48,59,'VRAW'),(149,62,'VREF25'),(165,61,'MOD_BIPOLAR')],1): + add(f'TP{i}',net,x,y,fp([sm(1,0,0,2,2)],[2,2],0,f'TestPoint_D2'),{'1':net},'B',block=('mod' if i>=4 else 'power'),mpn='PCB test pad',notes='Exposed soldermask aperture, no component.') + +CONFIG={'name':'RADIAN Panel / Interface','revision':'P1','status':'ENGINEERING PROTOTYPE - NOT FABRICATION RELEASE','pcb_front_z':-8.,'pcb_thickness':1.6,'panel_size':[202.8,128.5,2.0],'mainboard_unchanged':False,'direct_stack_revision':STACK['revision'],'direct_stack_gap_mm':STACK['nominal_board_gap_mm'],'layers':['F.Cu','In1.Cu','In2.Cu','B.Cu'],'inner_layers':'GND planes (native refill and DRC required)','outline':OUTLINE,'windows':WINDOWS,'mounts':MOUNTS,'desktop_input':'12V regulated, centre positive via chassis-mounted Switchcraft 722A; short 2-wire harness to Molex J201','power_target':'5.08V nominal, up to 3A IC target, system current capability UNTESTED','default_mod_mode':'JP1 pin 1 common to pin 3 MOD_RAW = unipolar bypass','bipolar_mod':'JP1 pin 1 common to pin 2 MOD_BIPOLAR: ideal output 0.5*input+VREF25; firmware/calibration required','line_outputs':'Direct LINE_L and LINE_R from existing mainboard, not amplified Eurorack level','midi':'Same Sky SDS-50J right-angle DIN receptacle in enclosure; short 2-wire harness to Molex J306, no extra custom PCB'} + +def save(): + if (ROOT/"NATIVE_BASELINE.json").exists():raise RuntimeError('Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.') + ROOT.mkdir(exist_ok=True) + (ROOT/'design'/'design.json').write_text(json.dumps({'config':CONFIG,'parts':PARTS,'pads':allpads(),'legacy_mainboard_map':MAP,'direct_stack':STACK},indent=2)) + with (ROOT/'docs'/'BOM.csv').open('w',newline='') as f: + w=csv.writer(f);w.writerow(['Reference','Value','Manufacturer','MPN_or_selection_gate','Footprint','Side','X_panel_mm','Y_panel_mm','DNP','Notes']) + for p in PARTS:w.writerow([p['ref'],p['value'],p['maker'],p['mpn'],p['fp']['name'],p['side'],p['x'],p['y'],p['dnp'],p['notes']]) + with (ROOT/'docs'/'mainboard_stack.csv').open('w',newline='') as f: + w=csv.writer(f);w.writerow(['Stack','Panel_connector','Mainboard_connector','Physical_pin','Net','Panel_X_mm','Panel_Y_mm','Main_X_mm','Main_Y_mm','Note']) + for con in STACK['connectors']: + for i,n in enumerate(con['signals'],1):w.writerow([con['id'],con['panel_ref'],con['main_ref'],i,n,con['panel_xy_mm']['x'],con['panel_xy_mm']['y'],con['main_xy_mm']['x'],con['main_xy_mm']['y'],'Direct board-to-board mating site; no cable harness']) + with (ROOT/'docs'/'mainboard_harness.csv').open('w',newline='') as f: + w=csv.writer(f);w.writerow(['Status','Replacement']);w.writerow(['DEPRECATED - direct stack replaces J101..J116 cable harnesses','mainboard_stack.csv']) + return PARTS +if __name__=='__main__': + save();print(len(PARTS),'parts;',len(allpads()),'physical pads; mainboard pins',sum(map(len,MAP.values()))) diff --git a/hardware/panel/source/export_ecad.py b/hardware/panel/source/export_ecad.py new file mode 100644 index 0000000..7326a84 --- /dev/null +++ b/hardware/panel/source/export_ecad.py @@ -0,0 +1,221 @@ +#!/usr/bin/env python3 +"""Self-contained KiCad 10 PCB + KiCad 8+ schematic writer from design_data. +No native KiCad process is invoked. Run native ERC/DRC before fabrication. +""" +from __future__ import annotations +import json, math, re, sys, collections, copy +from pathlib import Path +if __name__ == "__main__" and (Path(__file__).resolve().parents[1]/"NATIVE_BASELINE.json").exists(): + raise SystemExit("Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.") +from design_data import * +import shapely +from shapely.geometry import Polygon, Point, LineString, box +from shapely import affinity + +BROOT=uid('root') +BLOCKS=['power','controls','io','mod','service'] +TITLES={'power':'01 | POWER INPUTS AND 5 V CONVERTER','controls':'02 | FRONT-PANEL CONTROLS','io':'03 | PATCH JACKS AND MIDI','mod':'04 | OPTIONAL BIPOLAR MODULATION','service':'05 | INTERNAL SERVICE ACCESS'} +Q=lambda x:json.dumps(str(x),ensure_ascii=False) +f=lambda v:f'{v:.6f}'.rstrip('0').rstrip('.') if isinstance(v,(int,float)) else str(v) +def xy(x,y):return f'(xy {f(x)} {f(H-y)})' +def ppcb(x,y):return f'{f(x)} {f(H-y)}' +def pcb_path(block):return '/'+BROOT+'/'+uid('sheet:'+block) +def pad_shape(p): + x,y=p['X'],p['Y'];sx,sy=p['sx'],p['sy'] + if p['shape']=='circle': q=Point(0,0).buffer(sx/2,quad_segs=12) + elif p['shape']=='oval': + r=min(sx,sy)/2 + q=LineString([(-(sx/2-r),-(sy/2-r)),((sx/2-r),(sy/2-r))]).buffer(r,quad_segs=12) + else:q=box(-sx/2,-sy/2,sx/2,sy/2) + q=affinity.rotate(q,p.get('angle',0),origin=(0,0));return affinity.translate(q,x,y) +def board_shape(): + q=Polygon(OUTLINE,WINDOWS) + for x,y,d in MOUNTS:q=q.difference(Point(x,y).buffer(d/2,quad_segs=16)) + for p in allpads(): + if p['kind']=='np_thru_hole':q=q.difference(Point(p['X'],p['Y']).buffer(float(p['drill'])/2,quad_segs=16)) + return q + +def fptext(s,x,y,side,layer='SilkS',size=1.,hide=False): + return f'(fp_text user {Q(s)} (at {f(x)} {f(y)}) (layer "{side}.{layer}"){(" hide" if hide else "")} (effects (font (size {size} {size}) (thickness 0.15)){(" (justify mirror)" if side=="B" else "")}))' + +def footprint(p,lib=False): + side='F' if lib else p['side'];libname=p['fp']['name'];ref='REF**' if lib else p['ref'] + name=libname if lib else 'RadianPanel:'+libname + a=0 if lib else p['angle'];xx=0 if lib else p['x'];yy=0 if lib else H-p['y'] + mir=-1 if side=='B' else 1 + b=p['fp']['body'];pieces=[f'(footprint {Q(name)} (layer "{side}.Cu") (uuid {Q(uid("footprint:"+ref))})'] + if lib:pieces.append('(version 20260206) (generator "radian_panel_generator")') + if not lib:pieces.append(f'(at {f(xx)} {f(yy)} {f(a)})') + pieces.append(f'(property "Reference" {Q(ref)} (at 0 {f(-b[1]/2-1.5)} {f(a)}) (layer "{side}.SilkS") (effects (font (size 1 1) (thickness 0.15)){(" (justify mirror)" if side=="B" else "")}))') + for nm,va in [('Value',p['value']),('Manufacturer',p['maker']),('MPN',p['mpn']),('Description',p['notes'])]: + pieces.append(f'(property {Q(nm)} {Q(va)} (at 0 0 {f(a)}) (layer "{side}.Fab") (hide yes) (effects (font (size 1 1) (thickness 0.15))))') + if not lib: + pieces.append(f'(path {Q(pcb_path(p["block"])+"/"+p["uuid"])})') + if p['dnp']:pieces.append('(attr smd dnp)') + pieces.append(f'(fp_rect (start {f(-b[0]/2)} {f(-b[1]/2)}) (end {f(b[0]/2)} {f(b[1]/2)}) (stroke (width 0.1) (type default)) (fill none) (layer "{side}.Fab"))') + # Courtyard includes the part envelope and all pad extents. + ps=p['fp']['pads'];xmax=max([b[0]/2]+[abs(s['x'])+s['sx']/2 for s in ps])+.25;ymax=max([b[1]/2]+[abs(s['y'])+s['sy']/2 for s in ps])+.25 + pieces.append(f'(fp_rect (start {f(-xmax)} {f(-ymax)}) (end {f(xmax)} {f(ymax)}) (stroke (width 0.05) (type default)) (fill none) (layer "{side}.CrtYd"))') + # Short corner ticks, rather than outlines crossing large through-hole pads. + for ax,ay,dx,dy in [(-b[0]/2,-b[1]/2,1,0),(b[0]/2,b[1]/2,-1,0)]: + pieces.append(f'(fp_line (start {f(ax)} {f(ay)}) (end {f(ax+dx*.6)} {f(ay+dy*.6)}) (stroke (width 0.15) (type default)) (layer "{side}.SilkS"))') + for i,s in enumerate(ps): + n=s['n'];sx,sy=s['sx'],s['sy'];lx=s['x']*mir;ly=-s['y'];kind=s['kind'];shape=s['shape'] + t=[f'(pad {Q(n)} {kind} {shape} (at {f(lx)} {f(ly)} {f(a)}) (size {f(sx)} {f(sy)})'] + if s['drill'] is not None: + if isinstance(s['drill'],list):t.append(f'(drill oval {f(s["drill"][0])} {f(s["drill"][1])})') + else:t.append(f'(drill {f(s["drill"])})') + if kind=='smd':t.append(f'(layers "{side}.Cu" "{side}.Paste" "{side}.Mask")') + else:t.append('(layers "*.Cu" "*.Mask")') + if shape=='roundrect':t.append('(roundrect_rratio 0.20)') + if not lib and p['nets'].get(n):t.append(f'(net {Q(p["nets"][n])})') + if kind!='np_thru_hole':t.append('(clearance 0.2)') + t.append(f'(uuid {Q(uid("pad:"+ref+":"+n+":"+str(i)))})');t.append(')');pieces.append(' '.join(t)) + # Stable local 3D model: one individual reference model per footprint family. + if not lib:pieces.append(f'(model "${{KIPRJMOD}}/../cad/models/{libname}.step" (offset (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)))') + pieces.append(')');return '\n'.join(pieces) + +def write_pcb(tracks=None,vias=None): + if (ROOT/"NATIVE_BASELINE.json").exists():raise RuntimeError('Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.') + tracks=tracks or [];vias=vias or [] + h=['(kicad_pcb (version 20260206) (generator "radian_panel_generator") (generator_version "P1")', '(general (thickness 1.6)) (paper "A3")', + '(layers (0 "F.Cu" signal) (4 "In1.Cu" signal) (6 "In2.Cu" signal) (2 "B.Cu" signal) (13 "F.Paste" user) (15 "B.Paste" user) (5 "F.SilkS" user) (7 "B.SilkS" user) (1 "F.Mask" user) (3 "B.Mask" user) (17 "Dwgs.User" user) (19 "Cmts.User" user) (25 "Edge.Cuts" user) (31 "F.CrtYd" user) (29 "B.CrtYd" user) (35 "F.Fab" user) (33 "B.Fab" user))', + '(setup (pad_to_mask_clearance 0.05))', + '(title_block (title "RADIAN Panel / Interface PCB") (date "2026-09-15") (rev "P1 DRAFT") (comment 1 "NOT FOR FABRICATION: footprint / power / thermal / physical validation outstanding"))'] + for poly in [OUTLINE]+WINDOWS: + for i,(a,b) in enumerate(zip(poly,poly[1:]+poly[:1])): + h.append(f'(gr_line (start {ppcb(*a)}) (end {ppcb(*b)}) (stroke (width 0.05) (type default)) (layer "Edge.Cuts") (uuid {Q(uid("edge:"+str(a)+str(b)))}) )') + for i,(x,y,d) in enumerate(MOUNTS): + h.append(f'(footprint "RadianPanel:Mount_NPTH" (layer "F.Cu") (at {ppcb(x,y)}) (uuid {Q(uid("mount"+str(i)))}) (attr board_only exclude_from_pos_files exclude_from_bom) (pad "" np_thru_hole circle (at 0 0) (size {d} {d}) (drill {d}) (layers "*.Cu" "*.Mask")))') + for p in PARTS:h.append(footprint(p)) + for i,t in enumerate(tracks): + h.append(f'(segment (start {ppcb(*t["a"])}) (end {ppcb(*t["b"])}) (width {t["width"]}) (layer {Q(t["layer"])}) (net {Q(t["net"])}) (uuid {Q(uid("track:"+str(i)))}) )') + for i,v in enumerate(vias): + h.append(f'(via (at {ppcb(v["x"],v["y"])}) (size {v.get("size",.7)}) (drill {v.get("drill",.3)}) (layers "F.Cu" "B.Cu") (net {Q(v["net"])}) (uuid {Q(uid("via:"+str(i)))}) )') + # Plane fills intentionally left to KiCad; explicit status, not fake connectivity. + for la in ['In1.Cu','In2.Cu']: + pts=' '.join(xy(x,y) for x,y in OUTLINE) + h.append(f'(zone (net "GND") (layer {Q(la)}) (uuid {Q(uid("plane"+la))}) (hatch edge 0.5) (connect_pads yes (clearance 0.25)) (min_thickness 0.2) (fill yes (thermal_gap 0.35) (thermal_bridge_width 0.4)) (polygon (pts {pts})))') + for txt,x,y,sz in [('RADIAN / PANEL P1',75,116,1.4),('DRAFT - NOT FABRICATION RELEASE',75,12,1.0),('12 V DESKTOP / RACK +12 ONLY',47,69,1.),('MOD SHUNT: 1-2 UNI / 2-3 BI',157,91, .9),('LINE OUTPUTS - NOT HEADPHONES',171,12.8,.85)]: + h.append(f'(gr_text {Q(txt)} (at {ppcb(x,y)}) (layer "B.SilkS") (effects (font (size {sz} {sz}) (thickness 0.15)) (justify mirror)) (uuid {Q(uid(txt))}))') + h.append(')');(ROOT/'design'/'radian_panel.kicad_pcb').write_text('\n'.join(h)) + # library footprint definitions are all FRONT oriented; board instances handle side. + seen=set() + for p in PARTS: + nm=p['fp']['name'] + if nm not in seen:(ROOT/'library'/'RadianPanel.pretty'/(nm+'.kicad_mod')).write_text(footprint(p,True));seen.add(nm) + (ROOT/'design'/'fp-lib-table').write_text('(fp_lib_table (version 7) (lib (name "RadianPanel") (type "KiCad") (uri "${KIPRJMOD}/../library/RadianPanel.pretty") (options "") (descr "Project-local draft footprints; check against actual components")))\n') + project={"meta":{"filename":"radian_panel.kicad_pro","version":1},"board":{"design_settings":{"rules":{"min_clearance":.2,"min_track_width":.2,"min_via_diameter":.6,"min_through_hole_diameter":.3,"min_hole_to_hole":.25,"min_copper_edge_clearance":.3},"defaults":{"track_width":.25}}},"net_settings":{"classes":[{"name":"Default","clearance":.2,"track_width":.25,"via_diameter":.7,"via_drill":.3},{"name":"Power","clearance":.2,"track_width":1.5,"via_diameter":.9,"via_drill":.4}],"netclass_patterns":[{"netclass":"Power","pattern":n} for n in ['VIN5','VRAW','RACK_12V','DESKTOP_12V','RACK_FUSED','DESKTOP_FUSED']],"meta":{"version":3}},"libraries":{"pinned_footprint_libs":["RadianPanel"],"pinned_symbol_libs":["RadianPanel"]}} + (ROOT/'design'/'radian_panel.kicad_pro').write_text(json.dumps(project,indent=2)) + +# Schematic symbol definitions: exact pin-labelled graphs, no reliance on installed libraries. +def sym_pins(p): + nums=list(dict.fromkeys(q['n'] for q in p['fp']['pads'] if q['n'])) + names={q['n']:q.get('name',q['n']) for q in p['fp']['pads']} + is_pass=p['ref'].startswith(('R','C','L','F','D','TP')) and len(nums)<=2 + if is_pass: + return [dict(n=n,name=names[n],x=(-10.16 if i==0 else 10.16),y=0,a=(0 if i==0 else 180),etype='passive') for i,n in enumerate(nums)] + # Split into two banks for complex parts; connectors on one bank to show pin sequence. + split=(len(nums)+1)//2 if not p['ref'].startswith('J') else len(nums) + left=nums[:split];right=nums[split:];pins=[] + for bank,sgn in [(left,-1),(right,1)]: + for j,n in enumerate(bank): + et='passive' + if p['ref']=='U1':et={'1':'power_in','2':'output','3':'power_in','4':'input','5':'input','6':'passive'}[n] + if p['ref']=='U2':et={'1':'output','2':'input','3':'input','4':'power_in','5':'input','6':'input','7':'output','8':'power_in'}[n] + pins.append(dict(n=n,name=names[n],x=sgn*12.7,y=((len(bank)-1)/2-j)*2.54,a=0 if sgn==-1 else 180,etype=et)) + return pins + +def symbol_definition(p,name): + pins=sym_pins(p);ys=[abs(x['y']) for x in pins];ht=max(5.08,max(ys,default=0)+2.54) + passive=len(pins)<=2 and p['ref'].startswith(('R','C','D','L','F','TP')) + g=[] + if passive and p['ref'].startswith('C'): + for x in [-.9,.9]:g.append(f'(polyline (pts (xy {x} -2.54) (xy {x} 2.54)) (stroke (width 0.254) (type default)) (fill (type none)))') + for a,b in [(-7.62,-.9),(.9,7.62)]:g.append(f'(polyline (pts (xy {a} 0) (xy {b} 0)) (stroke (width 0.15) (type default)) (fill (type none)))') + elif passive and not p['ref'].startswith('TP'): + g.append('(rectangle (start -3.81 1.52) (end 3.81 -1.52) (stroke (width 0.2) (type default)) (fill (type none)))') + for a,b in [(-7.62,-3.81),(3.81,7.62)]:g.append(f'(polyline (pts (xy {a} 0) (xy {b} 0)) (stroke (width 0.15) (type default)) (fill (type none)))') + if p['ref'].startswith('D'):g.append('(polyline (pts (xy -2.54 -1.52) (xy -2.54 1.52)) (stroke (width 0.3) (type default)) (fill (type none)))') + elif passive:g.append('(circle (center 0 0) (radius 1) (stroke (width 0.15) (type default)) (fill (type none)))') + else:g.append(f'(rectangle (start -10.16 {ht}) (end 10.16 {-ht}) (stroke (width 0.254) (type default)) (fill (type background)))') + pinstring=[] + for pin in pins: + pinstring.append(f'(pin {pin["etype"]} line (at {pin["x"]} {pin["y"]} {pin["a"]}) (length 2.54) (name {Q(pin["name"])} (effects (font (size 1.0 1.0)))) (number {Q(pin["n"])} (effects (font (size 1.0 1.0)))))') + return f'(symbol {Q(name)} (pin_names (offset 0.508)) (in_bom yes) (on_board yes) (property "Reference" {Q(re.sub("[0-9]", "",p["ref"]))} (at 0 {ht+2.54} 0) (effects (font (size 1.27 1.27)))) (property "Value" {Q(p["value"])} (at 0 {-ht-2.54} 0) (effects (font (size 1.27 1.27)))) (property "Footprint" {Q("RadianPanel:"+p["fp"]["name"])} (at 0 0 0) (effects (font (size 1.27 1.27)) hide)) (symbol {Q(name.split(":")[-1]+"_0_1")} {" ".join(g)}) (symbol {Q(name.split(":")[-1]+"_1_1")} {" ".join(pinstring)}))' + +def scheme_header(title,uuid): + return f'(kicad_sch (version 20231120) (generator "radian_panel_generator") (uuid {Q(uuid)}) (paper "A2") (title_block (title {Q(title)}) (date "2026-09-15") (rev "P1 DRAFT") (comment 1 "Native ERC, footprint verification and hardware testing REQUIRED"))' +def schtext(text,x,y,size=1.5): + return f'(text {Q(text)} (at {f(x)} {f(y)} 0) (effects (font (size {size} {size})) (justify left top)) (uuid {Q(uid("text:"+text+str((x,y))))}))' +def write_schematic(): + if (ROOT/"NATIVE_BASELINE.json").exists():raise RuntimeError('Repaired native PCB is authoritative. Use hardware/refresh_outputs.py. Run legacy reconstruction only in a separate experimental copy without NATIVE_BASELINE.json.') + locations={};symdefs=[] + # Exact graph is shown with one unique symbol per designator; reusable footprint families. + for p in PARTS:symdefs.append(symbol_definition(p,p['ref'])) + (ROOT/'library'/'RadianPanel.kicad_sym').write_text('(kicad_symbol_lib (version 20231120) (generator "radian_panel_generator")\n'+'\n'.join(symdefs)+'\n)') + (ROOT/'design'/'sym-lib-table').write_text('(sym_lib_table (version 7) (lib (name "RadianPanel") (type "KiCad") (uri "${KIPRJMOD}/../library/RadianPanel.kicad_sym") (options "") (descr "Embedded exact pin graph for RADIAN Panel P1")))\n') + warnings={ + 'power':['12 V desktop supply replaces the earlier direct 5 V proposal. J100/J17 is the regulated 5 V direct-stack feed to the mainboard.','Diode OR prevents positive-rail backfeed; shared GND is not galvanic isolation. Unused rack pins are NC.','TPS54302 3 A rating is NOT a measured system current rating. Fuse selection / inrush / TVS / thermal review required.','Native plane refill and DRC required. 5.08 V nominal TI feedback values; never connect +12 V to main J1.'], + 'controls':['No additional pot wiper RC or LED series resistors: these are already on the RADIAN mainboard.','RV physical pin 1 = CCW/GND; physical pin 3 = CW/VREF25. This is not the main header pin order.','Encoder part changes to 20 mm shaft / 7 mm bushing. Match knob heights and verify turn direction.','SW1 logic mapping depends on installed orientation and firmware. Mechanical tab pins are intentionally NC.'], + 'io':['Pitch and Gate follow the existing mainboard front ends. LINE L/R are NOT new modular-level or headphone drivers.','WQP518MA: 1=SLEEVE, 2=NORMAL, 3=TIP. Inputs normal to ground; output normal pins intentionally NC.','MIDI uses exact Molex 22-27-2021 J306 to a short two-wire lead into the enclosure-mounted Same Sky SDS-50J. Keep DIN pin 2/shield isolated from board GND.','Input overvoltage, unpowered behavior, jack insertion shorts and output back-drive still need bench validation.'], + 'mod':['JP1 is Wurth 450301014042 SPDT: pin 1 common to pin 3 selects direct unipolar MOD_RAW.','Pin 1 common to pin 2 selects MOD_BIPOLAR. Ideal Vout = 0.5*Vin + VREF25. -5/0/+5 V -> 0/2.5/5 V.','5 V op-amp cannot reach exact rails under load. Endpoints, tolerance, saturation and calibration need testing.','Do not rescale the PITCH input implicitly. Bipolar MOD requires a matching firmware range/zero configuration.'], + 'service':['Internal-only JTAG, PROGRAM and RESET. J202 is exact Molex 22-27-2061; no additional exterior cutouts assumed.','Keep programming cables short and verify the actual programmer pinout. No level shifting is added.']} + for bi,bl in enumerate(BLOCKS): + pp=[p for p in PARTS if p['block']==bl];defs=[symbol_definition(p,'RadianPanel:'+p['ref']) for p in pp] + doc=[scheme_header(TITLES[bl],uid('document:'+bl)),'(lib_symbols '+'\n'.join(defs)+')',schtext(TITLES[bl],20,20,3),schtext('RADIAN PANEL P1 | NET-LABELLED ELECTRICAL SCHEMATIC',20,30,1.5)] + # Four columns leave room for long net names without wire ambiguity. + cols=4;rows=math.ceil(len(pp)/cols);rowh=min(64.,290/max(1,rows));starty=72. + for k,p in enumerate(pp): + x=round((79+(k%cols)*141)/1.27)*1.27;y=round((starty+(k//cols)*rowh)/1.27)*1.27 + pins=sym_pins(p);ht=max(5.08,max((abs(q['y']) for q in pins),default=0)+2.54) + # Large 16-pin rack connector gets extra body height, enough within 64mm cell. + locations[p['ref']]={'sheet':bl,'x':x,'y':y,'height':ht,'pins':pins} + doc.append(f'(symbol (lib_id {Q("RadianPanel:"+p["ref"])}) (at {f(x)} {f(y)} 0) (unit 1) (in_bom yes) (on_board yes) (dnp {"yes" if p["dnp"] else "no"}) (uuid {Q(p["uuid"])}) (property "Reference" {Q(p["ref"])} (at {f(x)} {f(y-ht-4)} 0) (effects (font (size 1.6 1.6)))) (property "Value" {Q(p["value"])} (at {f(x)} {f(y+ht+4)} 0) (effects (font (size 1.05 1.05)))) (property "Footprint" {Q("RadianPanel:"+p["fp"]["name"])} (at {f(x)} {f(y)} 0) (effects (font (size 1.0 1.0)) hide)) (property "MPN" {Q(p["mpn"])} (at {f(x)} {f(y)} 0) (effects (font (size 1 1)) hide)) '+ ' '.join(f'(pin {Q(pin["n"])} (uuid {Q(uid("schpin"+p["ref"]+pin["n"]))}))' for pin in pins)+ f' (instances (project "radian_panel" (path {Q(pcb_path(bl))} (reference {Q(p["ref"])}) (unit 1)))))') + for pin in pins: + xx=x+pin['x'];yy=y-pin['y'];net=p['nets'].get(pin['n']);sgn=-1 if pin['x']<0 else 1;ox=xx+sgn*5.08 + if net: + doc.append(f'(wire (pts (xy {f(xx)} {f(yy)}) (xy {f(ox)} {f(yy)})) (stroke (width 0) (type default)) (uuid {Q(uid("wire:"+p["ref"]+pin["n"]))}))') + doc.append(f'(global_label {Q(net)} (shape bidirectional) (at {f(ox)} {f(yy)} {0 if sgn<0 else 180}) (effects (font (size 1.0 1.0)) (justify right)) (uuid {Q(uid("label:"+p["ref"]+pin["n"]))}))') + else:doc.append(f'(no_connect (at {f(xx)} {f(yy)}) (uuid {Q(uid("nc:"+p["ref"]+pin["n"]))}))') + for i,note in enumerate(warnings[bl]):doc.append(schtext(note,20,365+i*8,1.35)) + doc.append(')');(ROOT/'design'/(bl+'.kicad_sch')).write_text('\n'.join(doc)) + root=[scheme_header('RADIAN | SINGLE PANEL / INTERFACE PCB',BROOT),'(lib_symbols)',schtext('RADIAN / PANEL P1',30,25,5),schtext('One custom front-panel PCB with direct Samtec stack to the revised FPGA mainboard. 40 HP / 3U + removable desktop dock.',30,38,2)] + for i,bl in enumerate(BLOCKS): + x=30+(i%2)*265;y=65+(i//2)*75 + root.append(f'(sheet (at {x} {y}) (size 235 50) (stroke (width 0.3) (type default)) (fill (color 0 0 0 0)) (uuid {Q(uid("sheet:"+bl))}) (property "Sheetname" {Q(TITLES[bl])} (at {x} {y-2} 0) (effects (font (size 2 2)) (justify left bottom))) (property "Sheetfile" {Q(bl+".kicad_sch")} (at {x} {y+52} 0) (effects (font (size 1.5 1.5)) (justify left top))) (instances (project "radian_panel" (path {Q("/"+BROOT)} (page {Q(str(i+2))})))))') + root.extend([schtext('ENGINEERING DRAFT: not a fabrication release. Consult the latest native ERC/DRC reports.',30,320,2),schtext('Default build: unipolar PITCH and MOD; JP1 is a real SPDT selector; line-level outputs; 12 V desktop / rack +12 V to onboard 5 V conversion.',30,337,1.65),schtext('SDS-50J MIDI and Switchcraft 722A desktop inlet are the intentional chassis endpoints, each on a short harness. No extra custom carrier PCB is required.',30,350,1.65),schtext('See ../docs/README.md for explicit unverified items and the bring-up procedure.',30,363,1.65),'(sheet_instances (path "/" (page "1")))',')']) + (ROOT/'design'/'radian_panel.kicad_sch').write_text('\n'.join(root)) + (ROOT/'design'/'schematic_layout.json').write_text(json.dumps({'parts':locations,'warnings':warnings,'titles':TITLES},indent=2)) + # Reconcile generated fields, connection grid and explicit ERC power sources. + from native_cleanup import fix_schematics + fix_schematics(ROOT,metadata={p['ref']:{'Description':p['notes'],'Manufacturer':p['maker']} for p in PARTS}) + +def sexp_parse(text): + tokens=re.findall(r'"(?:\\.|[^"\\])*"|[()]|[^\s()]+',text) + stack=[];root=None + for tok in tokens: + if tok=='(': + node=[] + if stack:stack[-1].append(node) + else: + if root is not None:raise ValueError('multiple roots') + root=node + stack.append(node) + elif tok==')': + if not stack:raise ValueError('extra close') + stack.pop() + else: + if not stack:raise ValueError('atom outside root') + stack[-1].append(json.loads(tok) if tok.startswith('"') else tok) + if stack:raise ValueError('unclosed expression') + return root + +def main(): + save();write_schematic();write_pcb() + checks={} + for p in (ROOT/'design').glob('*.kicad_*'): + if p.suffix=='.kicad_pro':json.loads(p.read_text());checks[p.name]='valid JSON';continue + x=sexp_parse(p.read_text());checks[p.name]={'balanced_and_tokenized':True,'root':x[0]} + (ROOT/'reports'/'syntax.json').write_text(json.dumps(checks,indent=2));print('ECAD written',len(PARTS),'parts') +if __name__=='__main__':main() diff --git a/hardware/panel/source/export_tscircuit_snapshot.py b/hardware/panel/source/export_tscircuit_snapshot.py new file mode 100644 index 0000000..756806b --- /dev/null +++ b/hardware/panel/source/export_tscircuit_snapshot.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +"""Export the canonical panel graph/geometry as a tscircuit input snapshot.""" +from __future__ import annotations +import json +from pathlib import Path +from design_data import PARTS, OUTLINE, WINDOWS, MOUNTS, CONFIG, STACK + +ROOT = Path(__file__).resolve().parents[1] +CENTER = STACK["panel_product_center_mm"] +CX, CY = CENTER["x"], CENTER["y"] + +def pt(p): + return {"x": p[0] - CX, "y": p[1] - CY} + +def part_record(p): + pads = [] + for i, q in enumerate(p["fp"]["pads"], 1): + pads.append({**q, "port": f"pin{i}", "net": p["nets"].get(q["n"])}) + return { + "ref": p["ref"], "value": p["value"], "block": p["block"], + "x": p["x"] - CX, "y": p["y"] - CY, + "side": "bottom" if p["side"] == "B" else "top", + "rotation": p["angle"], "body": p["fp"]["body"], "pads": pads, + } +data = { + "revision": CONFIG["revision"], + "status": CONFIG["status"], + "center_product_mm": CENTER, + "outline": [pt(p) for p in OUTLINE], + "windows": [[pt(p) for p in poly] for poly in WINDOWS], + "mounts": [{"x": x-CX, "y": y-CY, "diameter": d} for x,y,d in MOUNTS], + "parts": [part_record(p) for p in PARTS], + "stack": STACK, +} +out = ROOT / "tscircuit-design.json" +out.write_text(json.dumps(data, indent=2) + "\n") +print(out, len(data["parts"]), "parts") diff --git a/hardware/panel/source/native_cleanup.py b/hardware/panel/source/native_cleanup.py new file mode 100644 index 0000000..c265920 --- /dev/null +++ b/hardware/panel/source/native_cleanup.py @@ -0,0 +1,119 @@ +#!/usr/bin/env python3 +"""Reconcile RADIAN generated schematics without changing their electrical graph. +Run only against a backed-up project; native netlist/ERC/DRC are still required. +""" +from pathlib import Path +import json, re, uuid, copy, argparse + +def parse(text): + stack=[]; root=None + for tok in re.findall(r'"(?:\\.|[^"\\])*"|[()]|[^\s()]+',text): + if tok=='(': + node=[] + if stack: stack[-1].append(node) + elif root is not None: raise ValueError('Multiple roots') + else: root=node + stack.append(node) + elif tok==')': + if not stack: raise ValueError('Unbalanced close') + stack.pop() + else: stack[-1].append(tok) + if stack: raise ValueError('Unclosed expression') + return root + +def children(node,key): return [x for x in node if isinstance(x,list) and x and x[0]==key] +def child(node,key): return next(iter(children(node,key)),None) +def val(tok): return json.loads(tok) if tok.startswith('"') else tok +def q(v): return json.dumps(str(v),ensure_ascii=False) +def number(v): return f'{float(v):.6f}'.rstrip('0').rstrip('.') or '0' +def ident(text): return str(uuid.uuid5(uuid.UUID('7cfa5422-3a38-4c31-a2d2-e3ea799ebfff'),text)) + +def render(node,level=0): + if not isinstance(node,list): return node + if not any(isinstance(x,list) for x in node): return '('+' '.join(node)+')' + head=[]; tail=[]; seen=False + for x in node: + if isinstance(x,list): seen=True + (tail if seen else head).append(x) + return '('+' '.join(head)+''.join('\n'+' '*(level+1)+render(x,level+1) for x in tail)+')' + +def properties(node): return {val(x[1]):val(x[2]) for x in children(node,'property')} +def set_property(node,name,value,x=0,y=0): + p=next((p for p in children(node,'property') if val(p[1])==name),None) + if p is not None: p[2]=q(value) + else: node.append(parse(f'(property {q(name)} {q(value)} (at {number(x)} {number(y)} 0) (effects (font (size 1.27 1.27)) hide))')) +def snap(v): return number(round(float(v)/1.27)*1.27) +def snap_at(n): + a=child(n,'at') + if a: a[1:3]=[snap(a[1]),snap(a[2])] + +FLAG='''(symbol "PWR_FLAG" (power) (pin_names (offset 0) hide) (in_bom yes) (on_board yes) +(property "Reference" "#FLG" (at 0 1.905 0) (effects (font (size 1.27 1.27)) hide)) +(property "Value" "PWR_FLAG" (at 0 3.81 0) (effects (font (size 1.27 1.27)))) +(property "Footprint" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide)) +(property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide)) +(property "Description" "ERC power-source declaration; not a physical regulator" (at 0 0 0) (effects (font (size 1.27 1.27)) hide)) +(symbol "PWR_FLAG_0_0" (pin power_out line (at 0 0 90) (length 0) (name "~" (effects (font (size 1.27 1.27)))) (number "1" (effects (font (size 1.27 1.27)))))) +(symbol "PWR_FLAG_0_1" (polyline (pts (xy 0 0) (xy 0 1.27) (xy -1.016 1.905) (xy 0 2.54) (xy 1.016 1.905) (xy 0 1.27)) (stroke (width 0) (type default)) (fill (type none)))))''' + +def add_flags(doc,path): + libs=child(doc,'lib_symbols'); definition=parse(FLAG); definition[1]=q('RadianPanel:PWR_FLAG') + if not any(val(x[1])=='RadianPanel:PWR_FLAG' for x in children(libs,'symbol')): libs.append(definition) + existing={properties(s).get('Reference') for s in children(doc,'symbol')} + for i,net in enumerate(['GND','VRAW','VIN5'],1): + ref=f'#FLG0{i}'; x=40.64+(i-1)*129.54; y=347.98 + if ref in existing: continue + tag=ident('erc-flag:'+net) + doc.append(parse(f'''(symbol (lib_id "RadianPanel:PWR_FLAG") (at {x} {y} 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (uuid "{tag}") +(property "Reference" "{ref}" (at {x} {y-1.905} 0) (effects (font (size 1.27 1.27)) hide)) +(property "Value" "PWR_FLAG" (at {x} {y-3.81} 0) (effects (font (size 1.27 1.27)))) +(pin "1" (uuid "{ident('erc-flag-pin:'+net)}")) +(instances (project "radian_panel" (path "{path}" (reference "{ref}") (unit 1)))))''')) + doc.append(parse(f'(wire (pts (xy {x} {y}) (xy {x+5.08} {y})) (stroke (width 0) (type default)) (uuid "{ident("erc-wire:"+net)}"))')) + doc.append(parse(f'(global_label "{net}" (shape bidirectional) (at {x+5.08} {y} 180) (effects (font (size 1.27 1.27)) (justify right)) (uuid "{ident("erc-label:"+net)}"))')) + +def fix_schematics(root, metadata=None): + root=Path(root); design=root/'design' + if metadata is None: + pcb=parse((design/'radian_panel.kicad_pcb').read_text()) + meta={properties(f).get('Reference'):properties(f) for f in children(pcb,'footprint')} + else: meta=metadata + master=parse((design/'radian_panel.kicad_sch').read_text()); rootid=val(child(master,'uuid')[1]) + power_sheet=next(s for s in children(master,'sheet') if properties(s).get('Sheetfile')=='power.kicad_sch') + flagpath='/'+rootid+'/'+val(child(power_sheet,'uuid')[1]) + count=0 + for file in sorted(design.glob('*.kicad_sch')): + doc=parse(file.read_text()) + for inst in children(doc,'symbol'): + at=child(inst,'at'); x,y=map(float,at[1:3]); snap_at(inst) + dx,dy=float(at[1])-x,float(at[2])-y + for prop in children(inst,'property'): + a=child(prop,'at') + if a: a[1:3]=[number(float(a[1])+dx),number(float(a[2])+dy)] + m=meta.get(properties(inst).get('Reference'),{}) + for key in ['Description','Manufacturer']: + if key in m: set_property(inst,key,m[key],float(at[1]),float(at[2])) + count+=int(dx!=0 or dy!=0) + for kind in ['wire','bus']: + for wire in children(doc,kind): + for pt in children(child(wire,'pts'),'xy'): pt[1:3]=[snap(pt[1]),snap(pt[2])] + for kind in ['global_label','label','hierarchical_label','no_connect','junction']: + for item in children(doc,kind): snap_at(item) + for definition in children(child(doc,'lib_symbols'),'symbol'): + m=meta.get(val(definition[1]).split(':')[-1],{}) + for key in ['Description','Manufacturer']: + if key in m: set_property(definition,key,m[key]) + if file.name=='power.kicad_sch': add_flags(doc,flagpath) + file.write_text(render(doc)+'\n') + libfile=root/'library/RadianPanel.kicad_sym'; library=parse(libfile.read_text()) + for definition in children(library,'symbol'): + m=meta.get(val(definition[1]).split(':')[-1],{}) + for key in ['Description','Manufacturer']: + if key in m: set_property(definition,key,m[key]) + if not any(val(s[1])=='PWR_FLAG' for s in children(library,'symbol')): library.append(parse(FLAG)) + libfile.write_text(render(library)+'\n') + return {'moved_symbols':count,'power_source_declarations':['GND','VRAW','VIN5']} + +if __name__=='__main__': + import sys + print(json.dumps(fix_schematics(sys.argv[1]),indent=2)) diff --git a/hardware/panel/source/pcb_cleanup.py b/hardware/panel/source/pcb_cleanup.py new file mode 100644 index 0000000..e6b8d33 --- /dev/null +++ b/hardware/panel/source/pcb_cleanup.py @@ -0,0 +1,94 @@ +#!/usr/bin/env python3 +"""Native KiCad metadata/artwork reconciliation. Never reroutes copper.""" +from pathlib import Path +import json, copy, xml.etree.ElementTree as ET +import pcbnew +from native_cleanup import parse,render,children,child,val,q + +def xy(v): return (v.x,v.y) +def copper_signature(board): + tracks=[] + for t in board.GetTracks(): + item=[t.GetClass(),t.GetNetname(),xy(t.GetStart()),xy(t.GetEnd()),(t.GetWidth(pcbnew.F_Cu) if isinstance(t,pcbnew.PCB_VIA) else t.GetWidth()),t.GetLayer()] + if isinstance(t,pcbnew.PCB_VIA): item.append(t.GetDrillValue()) + tracks.append(item) + pads=[] + for f in board.GetFootprints(): + for p in f.Pads(): + net=p.GetNetname(); net='' if net.startswith('unconnected-') else net + pads.append([f.GetReference(),p.GetNumber(),xy(p.GetPosition()),xy(p.GetSize()),xy(p.GetDrillSize()),p.GetShape(),round(p.GetOrientationDegrees()%180,5),net,p.GetLayerSet().FmtHex()]) + return {'tracks':sorted(tracks,key=str),'pads':sorted(pads,key=str)} + +def missing_mount_library(root): + board=parse((root/'design/radian_panel.kicad_pcb').read_text()) + mounts=[f for f in children(board,'footprint') if val(f[1])=='RadianPanel:Mount_NPTH'] + if not mounts: return + signatures={render([p for p in children(f,'pad')][0]) for f in mounts} + normalized=[] + for f in mounts: + pad=copy.deepcopy(children(f,'pad')[0]);pad[:]=[n for n in pad if not (isinstance(n,list) and n[0]=='uuid')]; normalized.append(render(pad)) + assert len(set(normalized))==1,'Mount diameters differ: separate library members required' + f=copy.deepcopy(mounts[0]);f[1]=q('Mount_NPTH') + f[:]=[n for n in f if not (isinstance(n,list) and n[0] in ['at','uuid'])] + f.insert(2,['version','20260206']);f.insert(3,['generator',q('radian_native_cleanup')]) + for p in children(f,'pad'):p[:]=[n for n in p if not (isinstance(n,list) and n[0]=='uuid')] + (root/'library/RadianPanel.pretty/Mount_NPTH.kicad_mod').write_text(render(f)+'\n') + +def normalize_back_footprints(board,root): + changes=[]; temp=pcbnew.BOARD() + for f in board.GetFootprints(): + if f.GetLayer()!=pcbnew.B_Cu or abs(f.GetOrientationDegrees())>1e-6:continue + lib=pcbnew.FootprintLoad(str(root/'library/RadianPanel.pretty'),f.GetFPID().GetLibItemName()) + if lib is None:raise ValueError('Missing library: '+f.GetReference()) + temp.Add(lib);lib.SetPosition(f.GetPosition());lib.Flip(lib.GetPosition(),pcbnew.FLIP_DIRECTION_LEFT_RIGHT) + oldpad=sorted((p.GetNumber(),xy(p.GetPosition()),xy(p.GetSize()),xy(p.GetDrillSize())) for p in f.Pads()) + newpad=sorted((p.GetNumber(),xy(p.GetPosition()),xy(p.GetSize()),xy(p.GetDrillSize())) for p in lib.Pads()) + assert oldpad==newpad,'Cannot normalize without moving copper: '+f.GetReference() + fields=[(a,xy(a.GetPosition()),a.GetTextAngleDegrees()) for a in f.GetFields()] + pads=[(p,xy(p.GetPosition())) for p in f.Pads()] + f.SetOrientationDegrees(180) + for p,pos in pads:p.SetPosition(pcbnew.VECTOR2I(*pos)) + for field,pos,angle in fields: + field.SetPosition(pcbnew.VECTOR2I(*pos));field.SetTextAngleDegrees(angle) + oldgroups={};newgroups={} + for g in f.GraphicalItems():oldgroups.setdefault((g.GetLayer(),g.GetShape()),[]).append(g) + for g in lib.GraphicalItems():newgroups.setdefault((g.GetLayer(),g.GetShape()),[]).append((xy(g.GetStart()),xy(g.GetEnd()))) + assert set(oldgroups)==set(newgroups) + for key,old in oldgroups.items(): + new=sorted(newgroups[key]);assert len(old)==len(new) + for g,(start,end) in zip(old,new): + g.SetStart(pcbnew.VECTOR2I(*start));g.SetEnd(pcbnew.VECTOR2I(*end)) + for model in f.Models(): + model.m_Rotation.z+=180 + model.m_Offset.x=-model.m_Offset.x;model.m_Offset.y=-model.m_Offset.y + changes.append(f.GetReference()) + return changes + +def fix_board(root,netlist): + root=Path(root).resolve();missing_mount_library(root) + target=root/'design/radian_panel.kicad_pcb';board=pcbnew.LoadBoard(str(target)) + before=copper_signature(board);normalized=normalize_back_footprints(board,root) + refs={f.GetReference():f for f in board.GetFootprints() if f.GetReference()};assigned=[] + for net in ET.parse(netlist).getroot().findall('nets/net'): + name=net.get('name','') + if not name.startswith('unconnected-'):continue + nodes=net.findall('node');assert len(nodes)==1,'Expected a one-pin isolated net' + ref,pin=nodes[0].get('ref'),nodes[0].get('pin') + pad=[p for p in refs[ref].Pads() if p.GetNumber()==pin];assert len(pad)==1 + assert pad[0].GetNetname() in ['',name],'Refusing to replace an existing signal net' + ni=board.FindNet(name) + if ni is None: + ni=pcbnew.NETINFO_ITEM(board,name);board.Add(ni) + pad[0].SetNet(ni);assigned.append([ref,pin,name]) + after=copper_signature(board) + assert before==after,'Copper geometry, functional pad nets or routing changed' + pcbnew.SaveBoard(str(target),board,True) + check=pcbnew.LoadBoard(str(target));assert copper_signature(check)==before + result={'normalized_back_footprints':normalized,'isolated_pad_net_metadata':assigned,'copper_and_signal_nets_unchanged':True} + (root/'reports/pcb_metadata_repair.json').write_text(json.dumps(result,indent=2)) + return result + +if __name__=='__main__': + import argparse + ap=argparse.ArgumentParser();ap.add_argument('root');ap.add_argument('netlist');a=ap.parse_args() + print(json.dumps(fix_board(a.root,a.netlist),indent=2)) diff --git a/hardware/panel/source/render_docs.py b/hardware/panel/source/render_docs.py new file mode 100644 index 0000000..3d5cfeb --- /dev/null +++ b/hardware/panel/source/render_docs.py @@ -0,0 +1,127 @@ +#!/usr/bin/env python3 +"""Engineering previews from the same pad/track graph, not a generative render.""" +from pathlib import Path +import json,math,html,textwrap +import shapely +from shapely.geometry import Point,Polygon,LineString +from shapely import affinity +from reportlab.pdfgen import canvas +from reportlab.lib.colors import HexColor +from reportlab.pdfbase import pdfmetrics +from reportlab.pdfbase.ttfonts import TTFont +import cairosvg,fitz +from design_data import * +from export_ecad import board_shape,pad_shape,sym_pins +E=lambda x:html.escape(str(x)) + +def geom_path(g): + if g.is_empty:return '' + if hasattr(g,'geoms'):return ' '.join(geom_path(a) for a in g.geoms) + def ring(r): + pts=list(r.coords);return 'M'+' L'.join(f'{x:.5f},{H-y:.5f}' for x,y in pts)+' Z' + return ring(g.exterior)+' '+' '.join(ring(r) for r in g.interiors) + +def svg_header(view='0 0 220 152',w=2200,h=1520): + return [f'', ''] +def pcb_svg(side='F'): + r=json.load(open(ROOT/'design'/'routing.json'));s=svg_header();s.append('') + s.append('RADIAN / PANEL P1') + s.append(f'{side}.Cu • ENGINEERING DRAFT • 4 layers / 1.6 mm • front-panel coordinates') + s.append('') + s.append(f'') + for t in r['tracks']: + if t['layer']!=side+'.Cu':continue + s.append(f'') + for p in PARTS: + if p['side']!=side:continue + bx,by=p['fp']['body'];b=Polygon([(-bx/2,-by/2),(bx/2,-by/2),(bx/2,by/2),(-bx/2,by/2)]) + b=affinity.rotate(b,p['angle']);b=affinity.translate(b,p['x'],p['y']) + s.append(f'') + # Reference labels match physical placements. Body-based centre shown without fictional silk claims. + s.append(f'{E(p["ref"])}') + for p in allpads(): + if p['kind']=='smd' and p['side']!=side:continue + if p['kind']=='np_thru_hole':continue + g=pad_shape(p);s.append(f'') + if p['drill'] is not None: + pp=dict(p) + if isinstance(p['drill'],list):pp.update(sx=p['drill'][0],sy=p['drill'][1],shape='oval') + else:pp.update(sx=p['drill'],sy=p['drill'],shape='circle') + s.append(f'') + for v in r['vias']: + s.append(f'') + s.append('DIN / CRADLE WINDOW') + s.append('VENT') + for txt,x,y in [('PITCH',42,86),('DECAY',80,86),('TIMBRE',118,86)]: + if side=='F':s.append(f'{txt}') + s.append('') + s.append('NATIVE KiCad ERC / DRC / GND refill + physical fit + power tests remain mandatory.') + s.append('This view is generated from the actual draft pad and routed-track geometry. It is not a fabrication approval.') + s.append('');txt='\n'.join(s);path=ROOT/'previews'/f'pcb_{side}.svg';path.write_text(txt);cairosvg.svg2png(bytestring=txt.encode(),write_to=str(path.with_suffix('.png'))) + +# PDF pages intentionally mirror the explicit native net-labelled schematic. +def schematic_pdf(): + fonts=Path('/usr/share/fonts/truetype/dejavu') + pdfmetrics.registerFont(TTFont('DV',str(fonts/'DejaVuSans.ttf'))) + pdfmetrics.registerFont(TTFont('DVB',str(fonts/'DejaVuSans-Bold.ttf'))) + sf=72/25.4;c=canvas.Canvas(str(ROOT/'docs'/'RADIAN_Panel_P1_schematic.pdf'),pagesize=(594*sf,420*sf));c.setTitle('RADIAN Panel P1 — electrical schematic review') + layout=json.load(open(ROOT/'design'/'schematic_layout.json')) + def text(t,x,y,sz=1.5,font='DV',col='#283b35',align='left'): + c.setFillColor(HexColor(col));c.setFont(font,sz*sf) + fn={'left':c.drawString,'right':c.drawRightString,'center':c.drawCentredString}[align];fn(x*sf,(420-y)*sf,t) + def line(x1,y1,x2,y2,col='#416b55',width=.18): + c.setStrokeColor(HexColor(col));c.setLineWidth(width*sf);c.line(x1*sf,(420-y1)*sf,x2*sf,(420-y2)*sf) + for b in ['power','controls','io','mod','service']: + text('RADIAN / PANEL P1',20,20,4.,'DVB');text(layout['titles'][b],20,31,2.5,'DVB') + text('Exact pin/net graph • named nets connect across sheets • generated review drawing, not a native KiCad plot',20,40,1.7) + pp=[p for p in PARTS if p['block']==b] + for p in pp: + loc=layout['parts'][p['ref']];x=loc['x'];y=loc['y'];ht=loc['height'];pins=loc['pins'] + passive=len(pins)<=2 and p['ref'].startswith(('R','C','D','L','F','TP')) + text(p['ref'],x,y-ht-4,2.,'DVB',align='center') + if passive: + if p['ref'].startswith('C'): + line(x-.9,y-2.5,x-.9,y+2.5,'#604b42',.35);line(x+.9,y-2.5,x+.9,y+2.5,'#604b42',.35) + line(x-10.16,y,x-.9,y);line(x+.9,y,x+10.16,y) + else: + c.setStrokeColor(HexColor('#604b42'));c.setLineWidth(.25*sf);c.rect((x-3.81)*sf,(420-y-1.52)*sf,7.62*sf,3.04*sf) + line(x-10.16,y,x-3.81,y);line(x+3.81,y,x+10.16,y) + if p['ref'].startswith('D'):line(x-2.54,y-1.52,x-2.54,y+1.52,'#604b42',.4) + else: + c.setFillColor(HexColor('#f4f2e9'));c.setStrokeColor(HexColor('#604b42'));c.setLineWidth(.25*sf);c.rect((x-10.16)*sf,(420-y-ht)*sf,20.32*sf,2*ht*sf,fill=1) + for pin in pins: + xx=x+pin['x'];yy=y-pin['y'];sgn=-1 if pin['x']<0 else 1;end=xx+sgn*5.08;net=p['nets'].get(pin['n']) + if not passive: + line(xx,yy,x+sgn*10.16,yy,'#604b42');text(pin['name'],x+sgn*9.2,yy+.35,1.0,align='left' if sgn<0 else 'right');text(pin['n'],xx-sgn*.6,yy-.65,.85,align='center') + if net: + line(xx,yy,end,yy) + text(net,end+sgn*1.,yy+.5,1.18,col='#245b42',align='right' if sgn<0 else 'left') + else:line(xx-1,yy-1,xx+1,yy+1,'#a34d42');line(xx-1,yy+1,xx+1,yy-1,'#a34d42') + text(p['value'],x,y+ht+4,1.35,align='center') + for i,note in enumerate(layout['warnings'][b]):text(note,20,365+i*8,1.65) + line(20,401,574,401,'#9bafa3',.25);text('ENGINEERING DRAFT — NOT FOR FABRICATION',20,409,1.8,'DVB',col='#874b40');text(b.upper(),574,409,1.5,align='right') + c.showPage() + c.save() + doc=fitz.open(ROOT/'docs'/'RADIAN_Panel_P1_schematic.pdf') + for idx in [0,1,3]:doc[idx].get_pixmap(matrix=fitz.Matrix(.85,.85)).save(str(ROOT/'previews'/f'schematic_{idx+1}.png')) + +def drilling_dxf(): + # Plain ASCII DXF, mm. Projection uses panel's +Y-up CAD axes. + rows=['0','SECTION','2','HEADER','9','$INSUNITS','70','4','0','ENDSEC','0','SECTION','2','ENTITIES'] + def line(a,b,layer):rows.extend(['0','LINE','8',layer,'10',str(a[0]),'20',str(a[1]),'30','0','11',str(b[0]),'21',str(b[1]),'31','0']) + for poly in [OUTLINE]+WINDOWS: + for a,b in zip(poly,poly[1:]+poly[:1]):line(a,b,'BOARD_EDGE') + for x,y,d in MOUNTS:rows.extend(['0','CIRCLE','8','MOUNT_NPTH','10',str(x),'20',str(y),'30','0','40',str(d/2)]) + # PCB hole centres/major dimensions listed separately to avoid pretending slots are circles. + for p in allpads(): + if p['drill'] is None:continue + if isinstance(p['drill'],list): + line((p['X']-.5,p['Y']),(p['X']+.5,p['Y']),'SLOT_CENTRE');line((p['X'],p['Y']-.5),(p['X'],p['Y']+.5),'SLOT_CENTRE') + else:rows.extend(['0','CIRCLE','8','COMPONENT_DRILL','10',str(p['X']),'20',str(p['Y']),'30','0','40',str(p['drill']/2)]) + rows.extend(['0','ENDSEC','0','EOF']);(ROOT/'cad'/'RADIAN_panel_P1_outline_reference.dxf').write_text('\n'.join(rows)+'\n') + with (ROOT/'docs'/'drill_reference.csv').open('w',newline='') as f: + w=csv.writer(f);w.writerow(['Reference','Pin','X_panel_mm','Y_panel_mm','Drill_mm_or_slot_xy','Type']) + for p in allpads(): + if p['drill'] is not None:w.writerow([p['ref'],p['n'],p['X'],p['Y'],p['drill'],p['kind']]) +if __name__=='__main__': + pcb_svg('F');pcb_svg('B');schematic_pdf();drilling_dxf();print('Review previews/PDF/DXF written.') diff --git a/hardware/panel/source/requirements.txt b/hardware/panel/source/requirements.txt new file mode 100644 index 0000000..230a039 --- /dev/null +++ b/hardware/panel/source/requirements.txt @@ -0,0 +1,10 @@ +# Reference environment used for this engineering draft; native KiCad 10 is separate. +cadquery>=2.5,<3 +shapely>=2,<3 +numpy>=2,<3 +scipy>=1.13,<2 +reportlab>=4,<5 +CairoSVG>=2.7,<3 +PyMuPDF>=1.24,<2 +vtk>=9.3,<10 +Pillow>=10 diff --git a/hardware/panel/source/route_board.py b/hardware/panel/source/route_board.py new file mode 100644 index 0000000..2885ea4 --- /dev/null +++ b/hardware/panel/source/route_board.py @@ -0,0 +1,209 @@ +#!/usr/bin/env python3 +"""Conservative 0.25 mm two-outer-layer draft router, inner layers reserved for GND. +This is NOT KiCad's DRC/router. Routed results must undergo native clearance, +thermal, impedance, return-path, mask and manufacturing review. +""" +import json, math, heapq, time, itertools +import numpy as np +import shapely +from shapely.geometry import Point, LineString +from design_data import * +from export_ecad import pad_shape,board_shape,write_pcb,write_schematic +STEP=.25; NX=821;NY=521;LAYERS=['F.Cu','B.Cu'];CLEAR=.22 +PADS=allpads();PG=[pad_shape(p) for p in PADS];BOARD=board_shape() +TRACKS=[];VIAS=[];OBJS=[];LOG=[] + +def relevant(p,layer):return p['kind']!='smd' or p['side']==('F' if layer==0 else 'B') +def indices(g): + a,b,c,d=g.bounds + return max(0,int(math.floor(a/STEP))),max(0,int(math.floor(b/STEP))),min(NX-1,int(math.ceil(c/STEP))),min(NY-1,int(math.ceil(d/STEP))) +def stamp(a,g,value=True): + x0,y0,x1,y1=indices(g) + if x1=(2 if power else 1):break + if found==0:LOG.append({'type':'ground_stitch_failed','pad':p['ref']+'.'+p['n']}) + +# Wide power routes use short, explicit narrow escapes from the SOT23 pins. +SPECIAL={} +def make_special(): + for net,n,pts in [('SW','2',[(32.9,25),(31.0,25)]),('VRAW','3',[(32.9,24.05),(31.4,24.05),(31.4,22.95)])]: + okay=all(clear_geom(LineString([a,b]).buffer(.35/2),net,0) for a,b in zip(pts,pts[1:])) + if not okay:LOG.append({'type':'special_escape_blocked','net':net});continue + for a,b in zip(pts,pts[1:]):addtrack(a,b,net,.35,'F.Cu') + SPECIAL[('U1',n)]=dict(X=pts[-1][0],Y=pts[-1][1],kind='smd',side='F',net=net,ref='U1',n=n) + +cachedpad={} +def blocks(net,width): + rad=width/2+CLEAR + b=np.stack([~getinside(.30+width/2)]*2) + if net=='SW': + from shapely.geometry import box + avoid=box(33.2,23.55,34.8,26.45).buffer(width/2+.2) + for l in [0,1]:stamp(b[l],avoid) + cachekey=round(rad,5) + if cachekey not in cachedpad:cachedpad[cachekey]=[g.buffer(rad,quad_segs=6) for g in PG] + for p,g in zip(PADS,cachedpad[cachekey]): + if p['net']==net and p['net'] is not None:continue + for l in [0,1]: + if relevant(p,l):stamp(b[l],g) + for n,l,g in OBJS: + if n!=net:stamp(b[l],g.buffer(rad,quad_segs=6)) + # Via centre mask with complete two-sided pad and trace clearance. + vb=~getinside(.7) + for p,g in zip(PADS,PG): + if p['net']!=net or p['kind'] in ['smd','np_thru_hole']:stamp(vb,g.buffer(.57,quad_segs=6)) + for n,l,g in OBJS: + if n!=net:stamp(vb,g.buffer(.57,quad_segs=6)) + pth=np.zeros((NY,NX),bool) + for p,g in zip(PADS,PG): + if p['net']==net and p['kind']=='thru_hole':stamp(pth,g.buffer(-.25)) + return b,vb,pth + +def endpoint(p,b): + layers=[0,1] if p['kind']=='thru_hole' else ([0] if p['side']=='F' else [1]) + # Exact pad centres aren't always on grid. Choose a clear, nearby connected grid point. + opts=[];ix=int(round(p['X']/STEP));iy=int(round(p['Y']/STEP)) + for l in layers: + for dx,dy in [(0,0)]+list(itertools.product(range(-2,3),repeat=2)): + xx=ix+dx;yy=iy+dy + if not (0<=xx.55:continue + if clear_geom(LineString([(p['X'],p['Y']),(xx*STEP,yy*STEP)]).buffer(.125),p['net'],l):opts.append((d,l,xx,yy)) + return sorted(set(opts))[:4] +MOVES=[(-1,0,1),(1,0,1),(0,-1,1),(0,1,1),(-1,-1,1.41421356),(-1,1,1.41421356),(1,-1,1.41421356),(1,1,1.41421356)] +def astar(start,end,net,width,flayers=None,maxsteps=350000): + b,vb,pth=blocks(net,width);es=endpoint(start,b);ee=endpoint(end,b) + if flayers is not None:es=[s for s in es if s[1] in flayers];ee=[s for s in ee if s[1] in flayers] + if not es or not ee:return None,'endpoint blocked',0 + goals={(l,x,y) for _,l,x,y in ee};gx=np.mean([x for _,_,x,_ in ee]);gy=np.mean([y for _,_,_,y in ee]);area=NX*NY + def enc(l,x,y):return l*area+y*NX+x + def dec(n):l,rem=divmod(n,area);y,x=divmod(rem,NX);return l,x,y + def heur(x,y):dx=abs(x-gx);dy=abs(y-gy);return max(dx,dy)+.4142*min(dx,dy) + gscore={};prev={};heap=[];count=0 + for _,l,x,y in es: + n=enc(l,x,y);gscore[n]=0;prev[n]=None;heapq.heappush(heap,(heur(x,y),0,n)) + closed=set() + while heap: + f0,g0,n=heapq.heappop(heap) + if n in closed:continue + closed.add(n);count+=1;l,x,y=dec(n) + if (l,x,y) in goals: + path=[] + while n is not None:path.append(dec(n));n=prev[n] + return path[::-1],None,count + if count>maxsteps:return None,'search limit',count + for dx,dy,cost in MOVES: + xx=x+dx;yy=y+dy + if xx<0 or xx>=NX or yy<0 or yy>=NY or b[l,yy,xx]:continue + if dx and dy and (b[l,y,xx] or b[l,yy,x]):continue + nn=enc(l,xx,yy);ng=g0+cost + if ng',b['ref']+'.'+b['n'],width,'OK' if path else err,flush=True) + # Failed nodes aren't marked connected. Ratlines remain explicit for honest handoff. + +def main(): + ground_stitching();make_special() + nets=set(p['net'] for p in PADS if p['net'])-{'GND'} + priority=['SW','BOOT','FB','FF_TOP','EN','VIN5','VRAW','RACK_FUSED','DESKTOP_FUSED','RACK_12V','DESKTOP_12V','VREF25','VREF_BUF','MOD_SUM','MOD_FB','MOD_BIPOLAR'] + order=[n for n in priority if n in nets]+sorted(nets-set(priority),key=lambda n:sum(math.hypot(p['X']-net_nodes(n)[0]['X'],p['Y']-net_nodes(n)[0]['Y']) for p in net_nodes(n))) + for net in order: + route_net(net) + (ROOT/'design'/'routing.json').write_text(json.dumps({'tracks':TRACKS,'vias':VIAS},indent=2));(ROOT/'reports'/'routing_log.json').write_text(json.dumps(LOG,indent=2)) + write_pcb(TRACKS,VIAS) + write_schematic();save() + print('TOTAL',len(TRACKS),'tracks',len(VIAS),'vias; failed',sum(1 for x in LOG if x.get('success') is False),flush=True) +if __name__=='__main__':main() diff --git a/hardware/panel/source/silk_cleanup.py b/hardware/panel/source/silk_cleanup.py new file mode 100644 index 0000000..28f5b5d --- /dev/null +++ b/hardware/panel/source/silk_cleanup.py @@ -0,0 +1,63 @@ +#!/usr/bin/env python3 +"""Trim pad-crossing decorative footprint ticks; preserve all copper and labels.""" +from pathlib import Path +import math,json +from native_cleanup import parse,render,children,child,val,properties,number + +def hits(a,b,m):return a[0]<=b[2]+m and b[0]-m<=a[2] and a[1]<=b[3]+m and b[1]-m<=a[3] +def strip(fp): + angle=float(child(fp,'at')[3]) if child(fp,'at') and len(child(fp,'at'))>3 else 0 + boxes=[] + for p in children(fp,'pad'): + a=child(p,'at');x,y=map(float,a[1:3]);sx,sy=map(float,child(p,'size')[1:3]) + pa=float(a[3]) if len(a)>3 else 0 + theta=math.radians(pa-angle);c,s=abs(math.cos(theta)),abs(math.sin(theta)) + dx,dy=(sx*c+sy*s)/2,(sx*s+sy*c)/2;boxes.append((x-dx,y-dy,x+dx,y+dy)) + bad=[] + for g in children(fp,'fp_line'): + if val(child(g,'layer')[1]) not in ['F.SilkS','B.SilkS']:continue + a=list(map(float,child(g,'start')[1:3]));b=list(map(float,child(g,'end')[1:3])) + rect=(min(a[0],b[0]),min(a[1],b[1]),max(a[0],b[0]),max(a[1],b[1])) + width=float(child(child(g,'stroke'),'width')[1]) + if any(hits(rect,p,.20+width/2) for p in boxes):bad.append(g) + for g in bad:fp.remove(g) + return len(bad) + +def position_labels(board): + # Placement-specific positions: refuse to apply them to a different floorplan. + moves={'U1':((34,103.5),(37.1,103.5)), 'C1':((31,110.5),(31,113)), + 'U2':((151,61.5),(149,54)), 'D1':((44,63.5),(48,66.2)), + 'J101':((43,56.25),(43,59.45)), 'JP1':((165.5,40.5),(165.5,44.5))} + for fp in children(board,'footprint'): + ref=properties(fp).get('Reference') + if ref not in moves:continue + at=child(fp,'at');x,y=map(float,at[1:3]);expected,target=moves[ref] + assert math.dist((x,y),expected)<1e-5,'Changed placement: '+ref + a=math.radians(float(at[3]) if len(at)>3 else 0);dx,dy=target[0]-x,target[1]-y + field=next(f for f in children(fp,'property') if val(f[1])=='Reference') + fa=child(field,'at');fa[1:3]=[number(dx*math.cos(a)-dy*math.sin(a)),number(dx*math.sin(a)+dy*math.cos(a))] + for text in children(board,'gr_text'): + label=val(text[1]);target=None + if label.startswith('12 V DESKTOP'):target=(82,111) + elif label.startswith('MOD SHUNT:'):target=(145.5,30.5) + elif label.startswith('LINE OUTPUTS'):target=(136,112) + if target:child(text,'at')[1:3]=[number(v) for v in target] + +def clean(root): + root=Path(root).resolve();target=root/'design/radian_panel.kicad_pcb';board=parse(target.read_text()) + stats={'board':{},'library':{}} + for fp in children(board,'footprint'): + n=strip(fp) + if n:stats['board'][properties(fp).get('Reference','')]=n + position_labels(board) + target.write_text(render(board)+'\n') + for file in sorted((root/'library/RadianPanel.pretty').glob('*.kicad_mod')): + fp=parse(file.read_text());n=strip(fp) + if n: + stats['library'][file.stem]=n;file.write_text(render(fp)+'\n') + (root/'reports/silk_tick_cleanup.json').write_text(json.dumps(stats,indent=2)) + print('Removed only decorative ticks:',stats) + +if __name__=='__main__': + import sys + clean(sys.argv[1]) diff --git a/hardware/panel/source/update_case_direct_stack.py b/hardware/panel/source/update_case_direct_stack.py new file mode 100755 index 0000000..8ef7cfc --- /dev/null +++ b/hardware/panel/source/update_case_direct_stack.py @@ -0,0 +1,324 @@ +#!/usr/bin/env python3 +"""Update the retained RADIAN enclosure for the two-row six-pot direct-stack hardware. + +Uses the existing case solids as the design source for unchanged geometry, rebuilds +all panel-board reference components from the active panel source, and changes only +mechanical features required by the current panel/mainboard stack. The primary row +uses three large knobs; DRIVE / DELAY / REVERB use three smaller FX knobs below. +""" +from __future__ import annotations +from pathlib import Path +import json, math, re +import cadquery as cq + +ROOT=Path(__file__).resolve().parents[1] +CAD=ROOT/'cad'; PREV=ROOT/'previews'; REPORTS=ROOT/'reports' +BASE=CAD/'RADIAN_P1_case_legacy_reference.step' # immutable pre-direct-stack enclosure reference +STACK=json.loads((ROOT.parent/'stack'/'panel-stack.json').read_text()) + +from design_data import PARTS +import build_cad as model + +SHIFT_Z=STACK['mating']['max_gap_mm']-STACK['mating']['fully_mated_gap_mm'] # 0.46 mm +PANEL_BOARD_BACK_Z=-9.6 +MAIN_BOARD_TOP_OLD=-30.05 +MAIN_BOARD_TOP_NEW=MAIN_BOARD_TOP_OLD+SHIFT_Z +MAIN_BOARD_BOTTOM_OLD=-31.56 +MAIN_BOARD_BOTTOM_NEW=MAIN_BOARD_BOTTOM_OLD+SHIFT_Z +FRONT_SUPPORT_ZMIN=-30.0+SHIFT_Z +REAR_SPACER_ZMAX=-31.6+SHIFT_Z + +OLD_POTS=[(42,84),(80,84),(118,84)] +PRIMARY_POTS=[(38,96),(76,96),(114,96)] +FX_POTS=[(66,70),(88,70),(110,70)] +NEW_POTS=PRIMARY_POTS+FX_POTS +MODE=(150.5,84.5) +POT_HOLE_R=3.4 +MODE_HOLE_R=3.3 + +def color_hex(c, default='#30362F'): + if c is None:return default + rgb=c.toTuple()[:3] + return '#'+''.join(f'{max(0,min(255,round(v*255))):02x}' for v in rgb) + +def bbox(s): + b=s.BoundingBox(); return [float(x) for x in (b.xmin,b.ymin,b.zmin,b.xmax,b.ymax,b.zmax)] + +def centered_box(cx,cy,w,h,z0,z1,rot=0): + s=cq.Workplane('XY').box(w,h,z1-z0,centered=(True,True,False)).val().translate((cx,cy,z0)) + return s.rotate((cx,cy,0),(cx,cy,1),rot) if rot else s + +def cyl(cx,cy,r,z0,z1): + return cq.Workplane('XY').circle(r).extrude(z1-z0).val().translate((cx,cy,z0)) + +def component_color(name): + if name.endswith(('_shaft','_bushing','_pins')):return '#A3A899' + if name.startswith(('D10_','D11_','D12_','D13_')):return '#ADC873' + if re.match(r'^[RC]\d+_body$',name):return '#7E7862' + return '#30362F' + +print('Loading retained enclosure assembly...',flush=True) +base=cq.Assembly.importStep(str(BASE)) +old={c.name:(c.obj.moved(c.loc),color_hex(c.color)) for c in base.children} + +# Retain non-PCB enclosure/mechanical items only. Current panel electrical parts +# are regenerated below, so obsolete cable-header/component models cannot survive. +elec=re.compile(r'^(?:RV|ENC|SW|TP|JP|[RCUJFLOD])\d+_') +items={} +for name,(shape,col) in old.items(): + if name in {'P1_BOARD','MAINBOARD_REPAIRED','MAINBOARD_UNCHANGED', + 'P1_knobs_REFERENCE','P1_markers_REFERENCE', + 'engraving_reference'}: continue + if elec.match(name): continue + items[name]=(shape,col) + +# Rebuild the active six-pot panel reference from the active electrical/mechanical source. +board=model.board_shape() +items['P1_BOARD']=(board,'#265944') +panel_component_names=[] +for p in PARTS: + for suffix,shape in model.localmodel(p).items(): + name=p['ref']+'_'+suffix + items[name]=(model.place(shape,p), old.get(name,(None,component_color(name)))[1] if name in old else component_color(name)) + panel_component_names.append(name) + +# Front plate: repair the three legacy macro holes, then cut the six current +# two-row pot openings. MODE remains in its original raised insert. +panel=old['panel'][0] +panel=panel.fuse(cq.Compound.makeCompound([cyl(x,y,3.5,-.02,2.04) for x,y in OLD_POTS])).clean() +panel=panel.intersect(model.rect(-1,-1,205,131,0,2)).clean() # retain exact 2.00 mm faceplate thickness +for x,y in NEW_POTS: + panel=panel.cut(cyl(x,y,POT_HOLE_R,-.05,2.10)).clean() +items['panel']=(panel,old['panel'][1]) + +# The original raised MODE insert and its support/nut stack are retained unchanged. +mode_insert=old['mode_blank'][0] +items['mode_blank']=(mode_insert,old['mode_blank'][1]) + +# Replace old 3-macro knob references with a visual hierarchy: +# three large primary knobs, three smaller FX knobs, plus the encoder. +knobs=[];markers=[] +for x,y in PRIMARY_POTS: + knobs.append(model.cyl(x,y,6,11.5,16).cut(model.cyl(x,y,5.9,3.7,14.6))) + markers.append(model.rect(x-.5,y+7.5,1,3,22.01,.05)) +for x,y in FX_POTS: + knobs.append(model.cyl(x,y,6,7.0,12).cut(model.cyl(x,y,5.9,3.7,11.0))) + markers.append(model.rect(x-.4,y+3.5,.8,2.2,18.01,.05)) +knobs.append(model.cyl(42,43,6,13,16).cut(model.cyl(42,43,5.9,3.7,14.6))) +markers.append(model.rect(41.5,52,1,3,22.01,.05)) +items['P1_knobs_REFERENCE']=(cq.Compound.makeCompound(knobs),'#292F2A') +items['P1_markers_REFERENCE']=(cq.Compound.makeCompound(markers),'#DDDCCD') + +# Retain all legacy engraving except the old three macro names, then add +# row-specific labels. MODE keeps the original dedicated insert artwork. +eng=old['engraving_reference'][0] +keep=[] +for s in eng.Solids(): + b=s.BoundingBox() + old_macro=(66.5<=b.ymin<=70.0 and b.ymax<=70.5 and + ((37.5<=b.xmin<=46.0) or (75.5<=b.xmin<=84.5) or (114.5<=b.xmin<=121.0))) + if not old_macro: keep.append(s) +def text_shape(txt,x,y,size=2.0,z=1.77): + q=cq.Workplane('XY').text(txt,size,.21,halign='center',valign='center',font='DejaVu Sans').val() + return q.translate((x,y,z)) +for txt,(x,_) in zip(['TENSION','DECAY','CHAOS'],PRIMARY_POTS): + keep.append(text_shape(txt,x,112.5,2.0)) +keep.append(text_shape('FX',50,70,1.6)) +for txt,(x,_) in zip(['DRIVE','DELAY','REVERB'],FX_POTS): + keep.append(text_shape(txt,x,59.0,1.65)) +engraving=cq.Compound.makeCompound(keep) +items['engraving_reference']=(engraving,old['engraving_reference'][1]) + +# Use the freshly exported current native mainboard assembly, not the retained +# legacy case copy. This keeps the enclosure model synchronized when obsolete +# edge headers are physically removed from the canonical PCB. +main_step=ROOT.parent/'courant'/'deliverables'/'courant-assembly.step' +main_raw=cq.importers.importStep(str(main_step)).val() +# KiCad STEP: board center z=0, x/y native coordinates. Product transform is +# x-12, y+164.25; board midpoint maps to the current direct-stack PCB plane. +main_z_mid=(MAIN_BOARD_TOP_NEW+MAIN_BOARD_BOTTOM_NEW)/2 +main=main_raw.translate((-12.0,164.25,main_z_mid)) +items['MAINBOARD_REPAIRED']=(main,old['MAINBOARD_REPAIRED'][1]) + +# Shorten front support posts by 0.46 mm while retaining their front attachment. +clip=model.rect(-50,-50,300,230,FRONT_SUPPORT_ZMIN,35) +for name in [n for n in list(items) if n.startswith('corner_support_')]: + s,c=items[name];items[name]=(s.intersect(clip).clean(),c) + +# Extend the rear board spacers toward the shifted PCB by 0.46 mm. +if 'spacers_reference' in items: + s,c=items['spacers_reference'] + ext=[] + for q in s.Solids(): ext.append(q.fuse(q.translate((0,0,SHIFT_Z))).clean()) + items['spacers_reference']=(cq.Compound.makeCompound(ext),c) + +# Exact stack-reference connector geometry. The panel sockets are generated from +# the active PARTS source using the drawing-derived IPS1 STEP; here we place the +# matching IPT1-110-06-L-D model on the mainboard. Both models contain all 20 +# contacts/tails and the elevated -06 shroud geometry from the Samtec prints. +main_spec=STACK['connector_footprint']['main'] +main_model_path=ROOT.parent/'stack'/'models'/'Samtec_IPT1-110-06-L-D_drawing_reference.step' +main_model_local=cq.importers.importStep(str(main_model_path)).val() +main_connector_refs={} +for con in STACK['connectors']: + cx=STACK['mainboard_product_offset_mm']['x']+con['main_xy_mm']['x'] + cy=STACK['mainboard_product_offset_mm']['y']+con['main_xy_mm']['y'] + shape=main_model_local.rotate((0,0,0),(0,0,1),con['rotation_deg']).translate((cx,cy,MAIN_BOARD_TOP_NEW)) + main_connector_refs[con['main_ref']]=shape + +# Mechanical validation. +checks={} +checks['panel_valid']=panel.isValid();checks['mode_insert_valid']=mode_insert.isValid() +checks['panel_bbox_mm']=[round(x,4) for x in bbox(panel)] +checks['mainboard_bbox_mm']=[round(x,4) for x in bbox(main)] +checks['support_zmin_mm']=round(min(bbox(items[n][0])[2] for n in items if n.startswith('corner_support_')),4) +checks['rear_spacer_zmax_mm']=round(bbox(items['spacers_reference'][0])[5],4) +checks['pcb_gap_mm']=round(abs(MAIN_BOARD_TOP_NEW-PANEL_BOARD_BACK_Z),4) +checks['target_gap_mm']=STACK['mating']['fully_mated_gap_mm'] + +# All control shafts/bushings must clear their enclosure holes. +shaft_clear={} +for ref in ['RV1','RV2','RV3','RV4','RV5','RV6']: + sh=items[ref+'_shaft'][0];shaft_clear[ref]=abs(sh.intersect(panel).Volume()) +for suffix in ['bushing','shaft']: + shaft_clear['SW1_'+suffix]=abs(items['SW1_'+suffix][0].intersect(mode_insert).Volume()) +checks['control_enclosure_intersection_mm3']={k:round(v,7) for k,v in shaft_clear.items()} + +# Verify panel-side components do not hit the shifted mainboard, excluding nothing: +# the two Samtec socket bodies should still stop before the mainboard header bodies. +clashes=[] +for name in panel_component_names: + # J100/J101 intentionally mate the mainboard's J17/J18 and are validated + # separately below using the exact stack reference geometry. + if name.startswith(('J100_','J101_')):continue + s=items[name][0] + b1=bbox(s);b2=bbox(main) + if any(min(b1[i+3],b2[i+3])-max(b1[i],b2[i])<=0 for i in range(3)):continue + v=abs(s.intersect(main).Volume()) + if v>1e-4:clashes.append({'panel_part':name,'volume_mm3':round(v,5)}) +checks['panel_component_vs_mainboard_clashes']=clashes + +# Samtec full reference-model mating. Both sides now include all 20 pins/tails, +# socket towers and the elevated -06 shroud. The rounded REF dimensions in the +# official drawings close the IPT shroud top and IPS base by 0.01 mm at the +# nominal 19.99 mm board gap; the detailed vendor geometry resolves that mating +# interface. We therefore report/limit that drawing-rounding overlap separately, +# while independently verifying board gap, insertion and official contact wipe. +samtec=[] +nominal_insertion=(MAIN_BOARD_TOP_NEW+main_spec['insulation_height_mm'])-(PANEL_BOARD_BACK_Z-STACK['connector_footprint']['panel']['body_height_mm']) +max_gap_insertion=main_spec['insulation_height_mm']+STACK['connector_footprint']['panel']['body_height_mm']-STACK['mating']['max_gap_mm'] +checks['samtec_nominal_geometric_insertion_mm']=round(nominal_insertion,3) +checks['samtec_geometric_insertion_at_max_gap_mm']=round(max_gap_insertion,3) +checks['samtec_fully_mated_wipe_mm']=STACK['mating']['fully_mated_wipe_mm'] +checks['samtec_min_wipe_at_max_gap_mm']=STACK['mating']['min_wipe_at_max_gap_mm'] +checks['samtec_housing_ref_rounding_depth_mm']=round(main_spec['insulation_height_mm']+(STACK['connector_footprint']['panel']['body_height_mm']-STACK['connector_footprint']['panel']['socket_tower_height_mm'])-checks['pcb_gap_mm'],3) +for con in STACK['connectors']: + pbody=items[con['panel_ref']+'_body'][0] + mbody=main_connector_refs[con['main_ref']] + bp=bbox(pbody);bm=bbox(mbody) + inter=pbody.intersect(mbody); iv=abs(inter.Volume()) + ib=bbox(inter) if iv>1e-9 else [0,0,0,0,0,0] + # The series drawings use rounded REF dimensions: 15.30 + 8.51 - 19.99 + # gives 3.82 mm nominal insertion while the IPS1 tower is quoted as 3.81 mm. + # The resulting 0.01 mm contact-plane overlap is accepted as drawing-rounding, + # but no deeper solid penetration is allowed. + iz=max(0.0,ib[5]-ib[2]) if iv>1e-9 else 0.0 + samtec.append({'id':con['id'],'panel_model_z':[round(bp[2],3),round(bp[5],3)], + 'main_model_z':[round(bm[2],3),round(bm[5],3)], + 'solid_overlap_mm3':round(iv,7), + 'solid_overlap_z_mm':round(iz,5)}) +checks['samtec_reference_models']=samtec + +# Check the changed assembly against the retained enclosure. Positive volume at +# the four corner supports/rear spacers is intentional structural board contact; +# all other changed mainboard/control vs enclosure intersections must be zero. +changed_fit=[] +for other in ['rear_guard','desktop_dock','panel','mode_blank', + 'corner_support_BL','corner_support_BR','corner_support_TL','corner_support_TR','spacers_reference']: + if other not in items: continue + v=abs(main.intersect(items[other][0]).Volume()) + changed_fit.append({'a':'MAINBOARD_REPAIRED','b':other,'volume_mm3':round(v,7)}) +for ref in ['RV4_body','RV5_body','RV6_body','SW1_body']: + if ref not in items: continue + for other in ['rear_guard','desktop_dock']: + if other not in items: continue + v=abs(items[ref][0].intersect(items[other][0]).Volume()) + changed_fit.append({'a':ref,'b':other,'volume_mm3':round(v,7)}) +unintended=[x for x in changed_fit + if x['volume_mm3']>1e-4 and not (x['a']=='MAINBOARD_REPAIRED' and + (x['b'].startswith('corner_support_') or x['b']=='spacers_reference'))] +checks['changed_enclosure_intersections']=changed_fit +checks['changed_enclosure_unintended_intersections']=unintended + +assert checks['panel_valid'] and checks['mode_insert_valid'] +assert abs(checks['pcb_gap_mm']-STACK['mating']['fully_mated_gap_mm'])<1e-6 +assert not clashes +assert max(shaft_clear.values())<1e-4,shaft_clear +assert abs(checks['samtec_nominal_geometric_insertion_mm']-STACK['mating']['geometric_insertion_fully_mated_mm'])<1e-6 +assert abs(checks['samtec_geometric_insertion_at_max_gap_mm']-STACK['mating']['geometric_insertion_at_max_gap_mm'])<1e-6 +assert all(x['solid_overlap_z_mm']<=0.011 for x in samtec),samtec +assert not unintended,unintended + +# Export updated mechanical artifacts. +model.export_assy(items,CAD/'RADIAN_P1_desktop_fit_study.step','RADIAN_TWO_ROW_CASE_P3') +model.export_assy(items,CAD/'RADIAN_P1_case_updated.step','RADIAN_TWO_ROW_CASE_P3') +cq.exporters.export(panel,str(CAD/'panel.step')) +cq.exporters.export(panel,str(CAD/'RADIAN_P1_front_panel_updated.step')) +cq.exporters.export(mode_insert,str(CAD/'mode_blank.step')) +stale_reverb=CAD/'reverb_insert.step' +if stale_reverb.exists(): stale_reverb.unlink() +cq.exporters.export(engraving,str(CAD/'RADIAN_current_engraving_reference.step')) +if 'P1_mode_rear_spacer' in items:cq.exporters.export(items['P1_mode_rear_spacer'][0],str(CAD/'P1_mode_rear_spacer.step')) + +# Case-only assembly excludes PCB/component references but includes enclosure/support hardware. +case_names=[n for n in items if n not in panel_component_names and n not in {'P1_BOARD','MAINBOARD_REPAIRED'} and not n.endswith('_IPT1_REFERENCE')] +model.export_assy({n:items[n] for n in case_names},CAD/'RADIAN_P1_case_shell_updated.step','RADIAN_CASE_SHELL_P3') + +report={ + 'revision':'CASE-P3-TWO-ROW', + 'source_case':str(BASE.relative_to(ROOT)), + 'stack_revision':STACK['revision'], + 'mainboard_shift_forward_mm':SHIFT_Z, + 'panel_to_mainboard_pcb_gap_mm':checks['pcb_gap_mm'], + 'samtec':{'main':main_spec['mpn'],'panel':STACK['connector_footprint']['panel']['mpn'], + 'fully_mated_gap_mm':STACK['mating']['fully_mated_gap_mm'], + 'max_gap_mm':STACK['mating']['max_gap_mm'], + 'support_target_mm':STACK['mating']['assembly_standoff_target_mm']}, + 'front_panel':{'old_macro_holes_closed':OLD_POTS, + 'primary_large_knob_centers':PRIMARY_POTS, + 'fx_small_knob_centers':FX_POTS, + 'pot_hole_diameter_mm':2*POT_HOLE_R, + 'primary_knob_diameter_mm':23.0, + 'fx_knob_diameter_mm':14.0, + 'mode_center':MODE, + 'mode_hole_diameter_mm':2*MODE_HOLE_R, + 'mode_insert_role':'MODE'}, + 'supports':{'front_support_rear_z_mm':FRONT_SUPPORT_ZMIN, + 'rear_spacer_front_z_mm':REAR_SPACER_ZMAX,'rear_guard_unchanged':True}, + 'validation':checks, + 'limitations':['Samtec connector solids are drawing-derived reference models, not Samtec-supplied STEP downloads', + 'connector insertion/retention forces and case tolerances require first-article validation', + '0.01 mm nominal housing-plane overlap comes from rounded REF dimensions in the Samtec prints', + 'knob/nut/washer stack remains reference geometry'] +} +(REPORTS/'case_direct_stack_update.json').write_text(json.dumps(report,indent=2)+'\n') +print('CASE GEOMETRY PASS',json.dumps(report,indent=2),flush=True) + +# Previews are optional and must never invalidate a successful mechanical build. +# Run under Xvfb/headed DISPLAY to produce them; headless CAD generation exits cleanly. +import os +if os.environ.get('DISPLAY'): + model.render(items,PREV/'desktop_fit_study.png',target=(101,64,-15),camera=(310,-230,300),scale=110) + model.render(items,PREV/'case_front_updated.png',target=(101,64,1),camera=(101,64,300),scale=76,up=(0,1,0)) + nodock={n:v for n,v in items.items() if n not in {'desktop_dock','dock_nuts_reference'}} + model.render(nodock,PREV/'module_without_dock.png',target=(101,64,-10),camera=(310,-230,280),scale=105) + exploded={} + for n,(shape,c) in items.items(): + if n in ['desktop_dock','dock_nuts_reference','MAINBOARD_REPAIRED','rear_guard','spacers_reference'] or n.startswith('corner_support_') or n.endswith('_IPT1_REFERENCE'):dz=0 + elif n=='P1_BOARD' or n in panel_component_names:dz=40 + else:dz=65 + exploded[n]=(shape.translate((0,0,dz)),c) + model.render(exploded,PREV/'stack_exploded.png',target=(101,64,15),camera=(345,-250,245),scale=150) + print('CASE PREVIEWS DONE',flush=True) +else: + print('CASE PREVIEWS SKIPPED: no DISPLAY (geometry/report are complete)',flush=True) diff --git a/hardware/panel/source/validate_design.py b/hardware/panel/source/validate_design.py new file mode 100644 index 0000000..7590df3 --- /dev/null +++ b/hardware/panel/source/validate_design.py @@ -0,0 +1,93 @@ +#!/usr/bin/env python3 +"""Independent nominal-geometry and electrical-graph checks (NOT native DRC).""" +import json,csv,hashlib,math,collections,itertools +from pathlib import Path +import numpy as np +import shapely +from shapely.geometry import Point,LineString,Polygon +from shapely.strtree import STRtree +from design_data import * +from export_ecad import pad_shape,board_shape,sexp_parse + + +def main(): + d=json.load(open(ROOT/'design'/'routing.json'));ps=allpads();bd=board_shape();items=[] + for i,p in enumerate(ps): + if p['kind']=='np_thru_hole':continue + ls=['F.Cu','B.Cu','In1.Cu','In2.Cu'] if p['kind']=='thru_hole' else [p['side']+'.Cu'] + items.append({'id':f'pad {p["ref"]}.{p["n"]}#{i}','net':p['net'],'layers':ls,'geom':pad_shape(p),'pad':True}) + for i,t in enumerate(d['tracks']):items.append({'id':f'track {i}','net':t['net'],'layers':[t['layer']],'geom':LineString([t['a'],t['b']]).buffer(t['width']/2,quad_segs=12),'pad':False}) + for i,v in enumerate(d['vias']):items.append({'id':f'via {i}','net':v['net'],'layers':['F.Cu','B.Cu','In1.Cu','In2.Cu'],'geom':Point(v['x'],v['y']).buffer(v['size']/2,quad_segs=16),'pad':False}) + geom=[x['geom'] for x in items];tree=STRtree(geom);viol=[];ed=[] + for i,a in enumerate(items): + if not bd.buffer(1e-6).covers(a['geom']):ed.append({'id':a['id'],'kind':'outside outline or in cutout','area':a['geom'].difference(bd).area}) + elif a['geom'].distance(bd.boundary)<.3-1e-5:ed.append({'id':a['id'],'kind':'edge < 0.3 mm','distance':round(a['geom'].distance(bd.boundary),5)}) + for j in tree.query(a['geom'].buffer(.201)): + j=int(j) + if j>=i:continue + b=items[j] + if a['net'] is not None and a['net']==b['net']:continue + if not set(a['layers'])&set(b['layers']):continue + dd=a['geom'].distance(b['geom']) + if dd<.20-1e-5:viol.append({'a':a['id'],'b':b['id'],'nets':[a['net'],b['net']],'distance':round(dd,5),'overlap_area':round(a['geom'].intersection(b['geom']).area,6)}) + # Track/via connectivity for all NON-GND nets; intentional component internals not shorted. + parent=list(range(len(items))) + def find(i): + while parent[i]!=i:parent[i]=parent[parent[i]];i=parent[i] + return i + def join(i,j): + a=find(i);b=find(j) + if a!=b:parent[b]=a + for i,a in enumerate(items): + if not a['net']:continue + for j in tree.query(a['geom'].buffer(.002)): + j=int(j) + if j>=i:continue + b=items[j] + if a['net']==b['net'] and set(a['layers'])&set(b['layers']) and a['geom'].distance(b['geom'])<=.002:join(i,j) + nets={} + for i,a in enumerate(items): + if a['net'] and a['pad']:nets.setdefault(a['net'],{}).setdefault(find(i),[]).append(a['id']) + gaps={n:list(v.values()) for n,v in nets.items() if n!='GND' and len(v)>1} + report={'scope':'Custom nominal pad/track/via geometry and exact design graph, NOT native KiCad ERC/DRC, not thermal/signal integrity/manufacturing approval','components':len(PARTS),'pads':len(ps),'nets':len(nets),'tracks':len(d['tracks']),'vias':len(d['vias']),'routed_length_mm':sum(math.dist(t['a'],t['b']) for t in d['tracks']),'minimum_rule_mm':.2,'copper_edge_rule_mm':.3,'copper_clearance_violations':viol,'copper_edge_violations':ed,'disconnected_non_ground_nets':gaps,'ground_status':'Inner GND zone definitions provided. Native KiCad refill required; GND connectivity is not claimed by this test.','native_erc':'NOT RUN','native_drc':'NOT RUN','bench_tests':'NOT RUN','power_budget':'3 A IC target only; system capability not verified'} + # Pin-for-pin boundary against the uploaded CSV. + src=ROOT/'reference'/'courant-panel-interface.csv' + if not src.exists():src=Path('/mnt/data/courant-panel-interface.csv') + rr=list(csv.DictReader(src.open()));miss=[] + for r in rr: + k=int(r['Connector'][1:]);n=int(r['Pin']);exp=MAP[k][n-1] + if exp!=r['Net']:miss.append(r) + report['mainboard_pin_crosscheck']={'checked':len(rr),'mismatches':miss} + # Parse the emitted native files, extract the pin/net graph separately, and match graph data. + pcb=sexp_parse((ROOT/'design'/'radian_panel.kicad_pcb').read_text());fp_errors=[];stored=0 + for node in pcb: + if not isinstance(node,list) or node[0]!='footprint':continue + ref=next((z[2] for z in node if isinstance(z,list) and z[0]=='property' and z[1]=='Reference'),None) + if not ref:continue + part=next((p for p in PARTS if p['ref']==ref),None) + if part is None:continue + stored+=1 + for pad in [z for z in node if isinstance(z,list) and z[0]=='pad']: + pin=pad[1];got=next((z[1] for z in pad if isinstance(z,list) and z[0]=='net'),None) + exp=part['nets'].get(pin) + if got!=exp:fp_errors.append({'reference':ref,'pin':pin,'actual':got,'expected':exp}) + report['native_pcb_pin_net_crosscheck']={'footprints':stored,'mismatches':fp_errors} + syntax={} + for path in list((ROOT/'design').glob('*.kicad_sch'))+list((ROOT/'library'/'RadianPanel.pretty').glob('*.kicad_mod'))+[ROOT/'library'/'RadianPanel.kicad_sym']: + try: + node=sexp_parse(path.read_text());ids=[] + def walk(x): + if isinstance(x,list): + if x and x[0]=='uuid':ids.append(x[1]) + for z in x:walk(z) + walk(node);dups=[x for x,c in collections.Counter(ids).items() if c>1] + syntax[str(path.relative_to(ROOT))]={'balanced':True,'duplicate_uuids':dups} + except Exception as e:syntax[str(path.relative_to(ROOT))]={'error':str(e)} + report['syntax']=syntax + (ROOT/'reports'/'electrical_geometry_checks.json').write_text(json.dumps(report,indent=2)) + print(json.dumps({k:report[k] for k in ['components','pads','nets','tracks','vias','routed_length_mm','copper_clearance_violations','copper_edge_violations','disconnected_non_ground_nets','native_pcb_pin_net_crosscheck']},indent=2)) + # Evaluate the IDEAL resistor equations independently of PCB wiring; headroom not idealized away in text. + rng=np.random.default_rng(7);n=20000;r20=200e3*(1+rng.uniform(-.001,.001,n));r21=100e3*(1+rng.uniform(-.001,.001,n));r22=200e3*(1+rng.uniform(-.001,.001,n));rg=10e3*(1+rng.uniform(-.001,.001,n));rf=10e3*(1+rng.uniform(-.001,.001,n));den=1/r20+1/r21+1/r22;gain=(1+rf/rg)/(r20*den);zero=(1+rf/rg)*2.5/(r21*den) + dc={'model':'Ideal DC resistor network only. Not SPICE, no op-amp macro-model, no switching converter transient simulation. Monte Carlo assumes independent uniform resistor errors +/-0.1%.','mod_nominal_gain':.5,'mod_nominal_zero_V':2.5,'gain_range_sampled':[float(gain.min()),float(gain.max())],'zero_range_sampled_V':[float(zero.min()),float(zero.max())],'rail_endpoint_warning':'Nominal -5/+5 V maps to supply rails: real output swing and loading reduce usable endpoint range. Calibrate/limit firmware range.','power_feedback_nominal_V':.596*(1+(100000+49.9)/13300),'power_EN_at_VRAW_11V':11*105e3/(511e3+105e3),'inductor_ripple_nominal_A_at_VIN12':(.596*(1+(100000+49.9)/13300))*(1-.596*(1+(100000+49.9)/13300)/12)/(10e-6*400e3),'input_power_formula':'I_RACK = (Vout * Iout)/(VIN * converter_efficiency) + housekeeping; unknown actual FPGA load and efficiency'} + (ROOT/'reports'/'ideal_dc_checks.json').write_text(json.dumps(dc,indent=2)) +if __name__=='__main__':main() diff --git a/hardware/panel/source/verify_native.sh b/hardware/panel/source/verify_native.sh new file mode 100755 index 0000000..48290c4 --- /dev/null +++ b/hardware/panel/source/verify_native.sh @@ -0,0 +1,24 @@ +#!/usr/bin/env bash +# Run on a machine with KiCad 10 installed. DOES NOT order or fabricate anything. +# Official CLI options: https://docs.kicad.org/10.0/en/cli/cli.html +set -uo pipefail +ROOT="$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)" +command -v kicad-cli >/dev/null || { echo 'KiCad 10 kicad-cli is required.' >&2; exit 127; } +mkdir -p "$ROOT/reports/native" +kicad-cli version | tee "$ROOT/reports/native/version.txt" +# The generator did not invoke KiCad. Parsing/export failure is itself a blocker. +kicad-cli sch export netlist --format kicadxml --output "$ROOT/reports/native/panel_netlist.xml" "$ROOT/design/radian_panel.kicad_sch" || exit $? +kicad-cli sch erc --format json --severity-all --exit-code-violations --output "$ROOT/reports/native/erc.json" "$ROOT/design/radian_panel.kicad_sch" +ERC=$? +# --save-board deliberately saves KiCad's filled planes to a COPY, preserving draft source. +TMP="$ROOT/reports/native/work";mkdir -p "$TMP" +cp "$ROOT/design/"*.kicad_pcb "$ROOT/design/"*.kicad_pro "$ROOT/design/"*.kicad_sch "$TMP/" +cp "$ROOT/design/fp-lib-table" "$ROOT/design/sym-lib-table" "$TMP/" +# Preserve relative project libraries for the temporary project. +ln -sfn "$ROOT/library" "$ROOT/reports/native/library" +ln -sfn "$ROOT/cad" "$ROOT/reports/native/cad" +kicad-cli pcb drc --refill-zones --save-board --schematic-parity --all-track-errors --format json --severity-all --exit-code-violations --output "$ROOT/reports/native/drc.json" "$TMP/radian_panel.kicad_pcb" +DRC=$? +printf 'ERC exit=%s\nDRC exit=%s\n' "$ERC" "$DRC" | tee "$ROOT/reports/native/status.txt" +echo 'Inspect ALL reports. No excluded error is automatically accepted. Even zero ERC/DRC does not verify circuit behavior, chosen footprints, electrical safety, or physical fit.' +if [[ "$ERC" -ne 0 || "$DRC" -ne 0 ]];then exit 1;fi diff --git a/hardware/panel/tscircuit-design.json b/hardware/panel/tscircuit-design.json new file mode 100644 index 0000000..394cf85 --- /dev/null +++ b/hardware/panel/tscircuit-design.json @@ -0,0 +1,4032 @@ +{ + "revision": "P1", + "status": "ENGINEERING PROTOTYPE - NOT FABRICATION RELEASE", + "center_product_mm": { + "x": 103.25, + "y": 64.25 + }, + "outline": [ + { + "x": -85.25, + "y": -54.25 + }, + { + "x": 59.25, + "y": -54.25 + }, + { + "x": 59.25, + "y": -44.75 + }, + { + "x": 68.25, + "y": -44.75 + }, + { + "x": 68.25, + "y": -54.25 + }, + { + "x": 95.25, + "y": -54.25 + }, + { + "x": 95.25, + "y": 53.75 + }, + { + "x": 68.25, + "y": 53.75 + }, + { + "x": 68.25, + "y": 44.75 + }, + { + "x": 59.25, + "y": 44.75 + }, + { + "x": 59.25, + "y": 53.75 + }, + { + "x": -85.25, + "y": 53.75 + } + ], + "windows": [ + [ + { + "x": -42.25, + "y": -39.25 + }, + { + "x": 5.75, + "y": -39.25 + }, + { + "x": 5.75, + "y": -3.25 + }, + { + "x": -42.25, + "y": -3.25 + } + ], + [ + { + "x": 13.25, + "y": -28.75 + }, + { + "x": 46.25, + "y": -28.75 + }, + { + "x": 46.25, + "y": -15.75 + }, + { + "x": 13.25, + "y": -15.75 + } + ] + ], + "mounts": [ + { + "x": -78.25, + "y": 8.75, + "diameter": 2.7 + }, + { + "x": 31.75, + "y": 8.75, + "diameter": 2.7 + }, + { + "x": -78.25, + "y": 32.75, + "diameter": 2.7 + }, + { + "x": 31.75, + "y": 32.75, + "diameter": 2.7 + }, + { + "x": 73.25, + "y": -48.75, + "diameter": 2.7 + }, + { + "x": 93.25, + "y": -48.75, + "diameter": 2.7 + }, + { + "x": 73.25, + "y": 48.25, + "diameter": 2.7 + }, + { + "x": 93.25, + "y": 48.25, + "diameter": 2.7 + }, + { + "x": -79.25, + "y": -50.25, + "diameter": 2.7 + }, + { + "x": -48.25, + "y": -50.25, + "diameter": 2.7 + } + ], + "parts": [ + { + "ref": "J100", + "value": "IPS1-110-01-L-D", + "block": "controls", + "x": 20.75, + "y": -2.5, + "side": "bottom", + "rotation": 0, + "body": [ + 4.95, + 25.78 + ], + "pads": [ + { + "n": "1", + "x": 1.27, + "y": 11.43, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "rect", + "name": "1", + "port": "pin1", + "net": "GND" + }, + { + "n": "2", + "x": -1.27, + "y": 11.43, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "2", + "port": "pin2", + "net": "VIN5" + }, + { + "n": "3", + "x": 1.27, + "y": 8.89, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "3", + "port": "pin3", + "net": "VIN5" + }, + { + "n": "4", + "x": -1.27, + "y": 8.89, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "4", + "port": "pin4", + "net": "VREF25" + }, + { + "n": "5", + "x": 1.27, + "y": 6.35, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "5", + "port": "pin5", + "net": "GND" + }, + { + "n": "6", + "x": -1.27, + "y": 6.35, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "6", + "port": "pin6", + "net": "POT_PITCH_RAW" + }, + { + "n": "7", + "x": 1.27, + "y": 3.81, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "7", + "port": "pin7", + "net": "POT_DECAY_RAW" + }, + { + "n": "8", + "x": -1.27, + "y": 3.81, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "8", + "port": "pin8", + "net": "POT_TIMBRE_RAW" + }, + { + "n": "9", + "x": 1.27, + "y": 1.27, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "9", + "port": "pin9", + "net": "POT_DRIVE_RAW" + }, + { + "n": "10", + "x": -1.27, + "y": 1.27, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "10", + "port": "pin10", + "net": "POT_DELAY_RAW" + }, + { + "n": "11", + "x": 1.27, + "y": -1.27, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "11", + "port": "pin11", + "net": "POT_REVERB_RAW" + }, + { + "n": "12", + "x": -1.27, + "y": -1.27, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "12", + "port": "pin12", + "net": "GND" + }, + { + "n": "13", + "x": 1.27, + "y": -3.81, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "13", + "port": "pin13", + "net": "PITCH_IN" + }, + { + "n": "14", + "x": -1.27, + "y": -3.81, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "14", + "port": "pin14", + "net": "MOD_IN" + }, + { + "n": "15", + "x": 1.27, + "y": -6.35, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "15", + "port": "pin15", + "net": "GATE_IN" + }, + { + "n": "16", + "x": -1.27, + "y": -6.35, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "16", + "port": "pin16", + "net": "GND" + }, + { + "n": "17", + "x": 1.27, + "y": -8.89, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "17", + "port": "pin17", + "net": "LINE_L" + }, + { + "n": "18", + "x": -1.27, + "y": -8.89, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "18", + "port": "pin18", + "net": "GND" + }, + { + "n": "19", + "x": 1.27, + "y": -11.43, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "19", + "port": "pin19", + "net": "LINE_R" + }, + { + "n": "20", + "x": -1.27, + "y": -11.43, + "sx": 1.8, + "sy": 1.8, + "drill": 1.04, + "kind": "thru_hole", + "shape": "circle", + "name": "20", + "port": "pin20", + "net": "GND" + } + ] + }, + { + "ref": "J101", + "value": "IPS1-110-01-L-D", + "block": "service", + "x": -60.25, + "y": 8.0, + "side": "bottom", + "rotation": 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"side": "bottom", + "rotation": 0, + "body": [ + 2, + 2 + ], + "pads": [ + { + "n": "1", + "x": 0, + "y": 0, + "sx": 2, + "sy": 2, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1", + "port": "pin1", + "net": "VIN5" + } + ] + }, + { + "ref": "TP3", + "value": "VRAW", + "block": "power", + "x": -55.25, + "y": -5.25, + "side": "bottom", + "rotation": 0, + "body": [ + 2, + 2 + ], + "pads": [ + { + "n": "1", + "x": 0, + "y": 0, + "sx": 2, + "sy": 2, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1", + "port": "pin1", + "net": "VRAW" + } + ] + }, + { + "ref": "TP4", + "value": "VREF25", + "block": "mod", + "x": 45.75, + "y": -2.25, + "side": "bottom", + "rotation": 0, + "body": [ + 2, + 2 + ], + "pads": [ + { + "n": "1", + "x": 0, + "y": 0, + "sx": 2, + "sy": 2, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1", + "port": "pin1", + "net": "VREF25" + } + ] + }, + { + "ref": "TP5", + "value": "MOD_BIPOLAR", + "block": "mod", + "x": 61.75, + "y": -3.25, + "side": "bottom", + "rotation": 0, + "body": [ + 2, + 2 + ], + "pads": [ + { + "n": "1", + "x": 0, + "y": 0, + "sx": 2, + "sy": 2, + "drill": null, + "kind": "smd", + "shape": "roundrect", + "name": "1", + "port": "pin1", + "net": "MOD_BIPOLAR" + } + ] + } + ], + "stack": { + "revision": "STACK-P2", + "description": "Direct panel-to-mainboard Samtec IPT1/IPS1 mezzanine interface; no per-function harnesses", + "nominal_board_gap_mm": 19.99, + "mainboard_product_offset_mm": { + "x": 88.0, + "y": 64.25 + }, + "panel_product_center_mm": { + "x": 103.25, + "y": 64.25 + }, + "connector_footprint": { + "rows": 2, + "positions_per_row": 10, + "pitch_mm": 2.54, + "row_spacing_mm": 2.54, + "pad_diameter_mm": 1.8, + "main": { + "manufacturer": "Samtec", + "mpn": "IPT1-110-06-L-D", + "hole_mm": 1.02, + "body_mm": { + "x": 5.08, + "y": 25.91 + }, + "body_height_mm": 6.35, + "mounting": "vertical through-hole terminal strip", + "insulation_height_mm": 15.3, + "shroud_lower_face_mm": 8.95, + "post_tail_mm": 2.35, + "mating_contact_length_mm": 3.94, + "pin_square_mm": 0.64, + "drawing_reference_model": "models/Samtec_IPT1-110-06-L-D_drawing_reference.step" + }, + "panel": { + "manufacturer": "Samtec", + "mpn": "IPS1-110-01-L-D", + "hole_mm": 1.04, + "body_mm": { + "x": 4.95, + "y": 25.78 + }, + "body_height_mm": 8.51, + "mounting": "vertical through-hole socket strip", + "socket_tower_height_mm": 3.81, + "post_tail_mm": 2.54, + "tail_section_mm": { + "x": 0.79, + "y": 0.41 + }, + "drawing_reference_model": "models/Samtec_IPS1-110-01-L-D_drawing_reference.step" + } + }, + "connectors": [ + { + "id": "A", + "role": "power / analog controls / CV-gate / stereo audio", + "main_ref": "J17", + "panel_ref": "J100", + "main_xy_mm": { + "x": 36.0, + "y": -2.5 + }, + "panel_xy_mm": { + "x": 124.0, + "y": 61.75 + }, + "rotation_deg": 0, + "signals": [ + "GND", + "VIN5", + "VIN5", + "VREF25", + "GND", + "POT_PITCH_RAW", + "POT_DECAY_RAW", + "POT_TIMBRE_RAW", + "POT_DRIVE_RAW", + "POT_DELAY_RAW", + "POT_REVERB_RAW", + "GND", + "PITCH_IN", + "MOD_IN", + "GATE_IN", + "GND", + "LINE_L", + "GND", + "LINE_R", + "GND" + ] + }, + { + "id": "B", + "role": "digital controls / LEDs / MIDI / configuration / JTAG", + "main_ref": "J18", + "panel_ref": "J101", + "main_xy_mm": { + "x": -45.0, + "y": 8.0 + }, + "panel_xy_mm": { + "x": 43.0, + "y": 72.25 + }, + "rotation_deg": 90, + "signals": [ + "GND", + "V3V3", + "GND", + "ENC_A_RAW", + "ENC_B_RAW", + "ENC_SW_RAW", + "cv_select", + "LED0_A", + "LED1_A", + "LED2_A", + "LED3_A", + "GND", + "MIDI4", + "MIDI5", + "PROGRAM_B", + "reset_n", + "JTAG_TCK", + "JTAG_TDO", + "JTAG_TDI", + "JTAG_TMS" + ] + } + ], + "mechanical": { + "load_path": "mounting standoffs; mezzanine connectors are electrical/alignment only", + "panel_side": "bottom", + "mainboard_side": "top", + "panel_footprint_mirror_x": true, + "main_connector": "Samtec IPT1-110-06-L-D", + "panel_connector": "Samtec IPS1-110-01-L-D", + "fully_mated_gap_mm": 19.99, + "max_mated_gap_mm": 20.45, + "assembly_release_gate": "bench-fit connector seating and 20.0 mm standoff tolerance stack before production quantity", + "model_status": "Samtec drawing-derived reference geometry; official vendor STEP download remains gated by Samtec email access" + }, + "mating": { + "fully_mated_gap_mm": 19.99, + "max_gap_mm": 20.45, + "fully_mated_wipe_mm": 0.84, + "min_wipe_at_max_gap_mm": 0.38, + "assembly_standoff_target_mm": 20.0, + "note": "Use 20.0 mm nominal standoffs/spacing and verify assembled seating; 19.99 mm is Samtec nominal fully-mated PCB gap for IPT1 lead style -06 with IPS1 lead style -01.", + "drawing_verified": true, + "drawing_source": "Samtec IPX1 MATED DOCUMENT Rev C, Table 1: IPT1 -06 with IPS1 -01", + "geometric_insertion_fully_mated_mm": 3.82, + "geometric_insertion_at_max_gap_mm": 3.36 + }, + "native_coordinate_transform": { + "panel": { + "product_x": "pcb_x", + "product_y": "128.5 - pcb_y", + "pcb_thickness_mm": 1.6 + }, + "mainboard": { + "product_x": "pcb_x - 12.0", + "product_y": "164.25 - pcb_y", + "pcb_thickness_mm": 1.6 + } + } + } +} diff --git a/hardware/refresh_outputs.py b/hardware/refresh_outputs.py new file mode 100644 index 0000000..fb3b9cb --- /dev/null +++ b/hardware/refresh_outputs.py @@ -0,0 +1,137 @@ +#!/usr/bin/env python3 +"""Refresh review exports from the repaired native PCBs, never from router intermediates.""" +from pathlib import Path +import argparse,collections,csv,hashlib,json,os,shutil,subprocess,tempfile,zipfile +ROOT=Path(__file__).resolve().parent +CLI=os.environ.get('BACKPLANE_KICAD_CLI') or os.environ.get('KICAD_CLI') or shutil.which('kicad-cli') +LOG=[] +def digest(p):return hashlib.sha256(p.read_bytes()).hexdigest() +def run(args): + cmd=[str(CLI)]+[str(x) for x in args] + r=subprocess.run(cmd,capture_output=True,text=True,timeout=240) + LOG.append({'command':cmd,'exit_code':r.returncode,'stdout':r.stdout,'stderr':r.stderr}) + if r.returncode:raise RuntimeError('Command failed: '+str(cmd)+'\n'+r.stdout+r.stderr) + return r + +def checked(board,reports,schematic=None): + reports.mkdir(parents=True,exist_ok=True) + if schematic: + run(['sch','erc','--severity-all','--exit-code-violations','--format','json','-o',reports/'erc.json',schematic]) + args=['pcb','drc','--refill-zones','--all-track-errors','--severity-all','--exit-code-violations','--format','json','-o',reports/'drc.json'] + if schematic:args.append('--schematic-parity') + run(args+[board]);d=json.loads((reports/'drc.json').read_text()) + if d['violations'] or d['unconnected_items'] or d.get('schematic_parity'):raise RuntimeError('Nonempty DRC report') + if schematic:run(['sch','export','netlist','--format','kicadxml','-o',reports/'netlist.xml',schematic]) + print('NATIVE CHECKS PASS',board,flush=True) + +def svg(board,path,layers,mirror=False): + path.parent.mkdir(parents=True,exist_ok=True) + args=['pcb','export','svg','--mode-single','--exclude-drawing-sheet','--fit-page-to-board','--layers',layers,'-o',path] + if mirror:args.append('--mirror') + run(args+[board]) + if shutil.which('magick'): + r=subprocess.run(['magick','-background','white','-density','200',str(path),'-flatten','-resize','2000x',str(path.with_suffix('.png'))],capture_output=True,text=True,timeout=120) + if r.returncode:raise RuntimeError(r.stderr) + +def fabricate(board,folder,copper_layers,stem,protel): + folder.mkdir(parents=True,exist_ok=True) + layers=copper_layers+',F.Mask,B.Mask,F.Paste,B.Paste,F.Silkscreen,B.Silkscreen,Edge.Cuts' + args=['pcb','export','gerbers','--check-zones','--subtract-soldermask','--layers',layers,'-o',str(folder)+'/'] + if not protel:args.append('--no-protel-ext') + run(args+[board]) + run(['pcb','export','drill','--format','excellon','--excellon-units','mm','--excellon-separate-th','--generate-map','--map-format','pdf','-o',str(folder)+'/',board]) + run(['pcb','export','pos','--format','csv','--units','mm','--side','both','-o',folder/(stem+'-pos.csv'),board]) + (folder/'REVIEW_ONLY.txt').write_text('Regenerated from the repaired native PCB. NOT a production release.\nERC/DRC do not establish component correctness, power/thermal/fault behaviour, FPGA operation or physical fit.\n') + +def bundle(folder,path,board): + data={'source_board':str(board.relative_to(ROOT)),'source_sha256':digest(board),'review_only':True,'files':{p.name:digest(p) for p in sorted(folder.iterdir()) if p.is_file() and p.name!='MANIFEST.json'}} + (folder/'MANIFEST.json').write_text(json.dumps(data,indent=2)) + with zipfile.ZipFile(path,'w',zipfile.ZIP_DEFLATED) as z: + for p in sorted(folder.iterdir()): + if p.is_file():z.write(p,p.name) + with zipfile.ZipFile(path) as z:assert z.testzip() is None + +def metadata(board,folder,panel=False): + import pcbnew as pcb + b=pcb.LoadBoard(str(board));fps={f.GetReference():f for f in b.GetFootprints() if f.GetReference()} + nets=collections.defaultdict(list) + for f in b.GetFootprints(): + for p in f.Pads(): + if p.GetNetname():nets[p.GetNetname()].append(f.GetReference()+'.'+p.GetNumber()) + out=folder/('radian_panel-netlist.txt' if panel else 'courant-netlist.txt') + text=['Current repaired native board: '+board.name,str(len(nets))+' nets'] + for name,ps in sorted(nets.items()):text.extend(['',name+' ('+str(len(ps))+')']+[' '+p for p in sorted(ps)]) + out.write_text('\n'.join(text)+'\n') + if panel: + path=folder/'BOM.csv';rows=list(csv.DictReader(path.open()));fields=list(rows[0]) + for row in rows: + f=fps[row['Reference']];row.update(Value=f.GetValue(),Footprint=f.GetFPIDAsString(),Side='B' if f.GetLayer()==pcb.B_Cu else 'F',X_panel_mm=pcb.ToMM(f.GetPosition().x),Y_panel_mm=128.5-pcb.ToMM(f.GetPosition().y)) + else: + path=folder/'courant-bom.csv';old=list(csv.DictReader(path.open()));fields=list(old[0]);groups={} + for row in old: + for ref in row['Reference(s)'].split(','): + ref=ref.strip() + # Native board is authoritative: retired/DNP footprints removed from the + # board must also disappear from regenerated BOM metadata. + if ref not in fps:continue + f=fps[ref];r=dict(row);r.update(Value=f.GetValue(),Footprint=f.GetFPIDAsString(),Side='bottom' if f.GetLayer()==pcb.B_Cu else 'top') + key=tuple(r[k] for k in fields if k not in ('Reference(s)','Qty')) + if key not in groups:groups[key]=[r,[]] + groups[key][1].append(ref) + rows=[] + for r,refs in groups.values():r.update({'Reference(s)':','.join(refs),'Qty':len(refs)});rows.append(r) + with path.open('w',newline='') as f:w=csv.DictWriter(f,fieldnames=fields);w.writeheader();w.writerows(rows) + return {'footprints':len(list(b.GetFootprints())),'tracks':sum(not isinstance(t,pcb.PCB_VIA) for t in b.GetTracks()),'vias':sum(isinstance(t,pcb.PCB_VIA) for t in b.GetTracks()),'nets':len(nets)} + +def mainboard(): + m=ROOT/'courant';src=m/'deliverables';b=src/'courant.kicad_pcb';dist=m/'dist';dist.mkdir(exist_ok=True) + before=digest(b);checked(b,src/'native_checks') + for name in ('courant','courant.routed'): + shutil.copy2(b,dist/(name+'.kicad_pcb'));shutil.copy2(src/'courant.kicad_pro',dist/(name+'.kicad_pro')) + shutil.copytree(src/'RadianMain.pretty',dist/'RadianMain.pretty',dirs_exist_ok=True);shutil.copy2(src/'fp-lib-table',dist/'fp-lib-table') + routed=dist/'courant.routed.kicad_pcb';checked(routed,dist/'native_checks') + run(['pcb','drc','--refill-zones','--all-track-errors','--severity-all','--exit-code-violations','--format','report','-o',dist/'courant.drc.rpt',routed]) + counts=metadata(b,src);shutil.copy2(src/'courant-netlist.txt',dist/'courant.netlist.txt') + fabricate(routed,dist/'fab','F.Cu,In1.Cu,In2.Cu,In3.Cu,In4.Cu,B.Cu','courant',False) + shutil.copy2(src/'courant-bom.csv',dist/'fab/courant-bom.csv') + bundle(dist/'fab',dist/'courant-fab.zip',b) + svg(b,dist/'courant-top.svg','F.Cu,F.Silkscreen,Edge.Cuts') + svg(b,dist/'courant-bottom.svg','B.Cu,B.Silkscreen,Edge.Cuts',True) + svg(b,dist/'route-inner.svg','In1.Cu,In2.Cu,In3.Cu,In4.Cu,Edge.Cuts') + for dest,source in [('route-top','courant-top'),('route-bottom','courant-bottom')]: + for ext in ('.svg','.png'):shutil.copy2(dist/(source+ext),dist/(dest+ext)) + shutil.copy2(dist/'courant-top.svg',dist/'courant.pcb.svg') + shutil.copy2(src/'courant-schematic.svg',dist/'courant.schematic.svg') + run(['pcb','export','dxf','--mode-single','--output-units','mm','--layers','Edge.Cuts','--output',src/'courant-outline.dxf',b]) + run(['pcb','export','pdf','--mode-single','--black-and-white','--sketch-pads-on-fab-layers','--layers','Edge.Cuts,F.Fab,F.Silkscreen','--output',src/'courant-mechanical.pdf',b]) + assert digest(b)==before + print('MAINBOARD EXPORTS DONE',counts,flush=True) + return {'board_sha256':before,'counts':counts} + +def panelboard(): + p=ROOT/'panel';b=p/'design/radian_panel.kicad_pcb';s=p/'design/radian_panel.kicad_sch';before=digest(b) + checked(b,p/'reports/native',s);counts=metadata(b,p/'docs',panel=True) + fabricate(b,p/'fab','F.Cu,In1.Cu,In2.Cu,B.Cu','radian_panel',True) + shutil.copy2(p/'docs/BOM.csv',p/'fab/BOM.csv');bundle(p/'fab',p/'radian_panel-fab.zip',b) + for side in ('F','B'):svg(b,p/'previews'/('pcb_'+side+'.svg'),side+'.Cu,'+side+'.Silkscreen,Edge.Cuts',side=='B') + run(['sch','export','pdf','--output',p/'docs/RADIAN_Panel_P1_schematic.pdf',s]) + run(['sch','export','svg','--output',str(p/'previews/schematic')+'/',s]) + for n,name in [(1,'power'),(2,'controls'),(4,'mod')]: + source=p/'previews/schematic'/(name+'.svg') + if source.exists() and shutil.which('magick'): + r=subprocess.run(['magick','-background','white','-density','160',str(source),'-flatten','-resize','2400x',str(p/'previews'/('schematic_'+str(n)+'.png'))],capture_output=True,text=True,timeout=120) + if r.returncode:raise RuntimeError(r.stderr) + run(['pcb','export','dxf','--mode-single','--output-units','mm','--layers','Edge.Cuts','--output',p/'cad/RADIAN_panel_P1_outline_reference.dxf',b]) + assert digest(b)==before + print('PANEL EXPORTS DONE',counts,flush=True) + return {'board_sha256':before,'counts':counts} + +def main(): + ap=argparse.ArgumentParser(description=__doc__);ap.add_argument('--board',choices=('all','mainboard','panel'),default='all');a=ap.parse_args() + if not CLI:raise RuntimeError('Set BACKPLANE_KICAD_CLI or install kicad-cli') + results={};log=ROOT/'CURRENT_EXPORTS.json' + try: + if a.board in ('all','mainboard'):results['mainboard']=mainboard() + if a.board in ('all','panel'):results['panel']=panelboard() + finally:log.write_text(json.dumps({'review_only':True,'results':results,'commands':LOG},indent=2)) +if __name__=='__main__':main() diff --git a/hardware/repair_integrity.json b/hardware/repair_integrity.json new file mode 100644 index 0000000..7345d21 --- /dev/null +++ b/hardware/repair_integrity.json @@ -0,0 +1,93 @@ +{ + "mainboard_pad_and_net_map_unchanged": true, + "footprint_positions_unchanged": true, + "design_rules_unchanged": true, + "mainboard_copies_identical": true, + "native_reports": { + "main": { + "violations": 0, + "unconnected": 0, + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ] + }, + "panel": { + "violations": 0, + "unconnected": 0, + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ] + } + }, + "panel_erc_findings": 0, + "export_archives_match_active_boards": true, + "fabrication_gate_regression_tests": [ + { + "argv": [ + "fab.py", + "--drc-only" + ], + "exit": 5, + "injected_drc_failure": true + }, + { + "argv": [ + "fab.py" + ], + "exit": 1, + "injected_drc_failure": true + } + ], + "mainboard_before": { + "footprints": 202, + "pads": 746, + "vias": 313, + "segments": 2192, + "track_length_mm": 4436.654204345376 + }, + "mainboard_after": { + "footprints": 202, + "pads": 746, + "vias": 299, + "segments": 2158, + "track_length_mm": 4386.162058609177 + } +} \ No newline at end of file diff --git a/hardware/stack/actual-parts-collision-validation.json b/hardware/stack/actual-parts-collision-validation.json new file mode 100644 index 0000000..884728e --- /dev/null +++ b/hardware/stack/actual-parts-collision-validation.json @@ -0,0 +1,16 @@ +{ + "status": "PASS", + "physical_pcb_faces": { + "panel_back_z_mm": -9.6, + "main_front_z_mm": -29.59, + "gap_mm": 19.99, + "target_mm": 19.99 + }, + "actual_components_vs_physical_enclosure_clashes": [], + "non_samtec_panel_vs_main_clashes": [], + "non_samtec_panel_vs_main_overlap_mm3": 0.0, + "notes": [ + "Reference nuts, shims, standoffs, inks and PCB visualization layers are excluded from enclosure clash classification.", + "The intentionally mated Samtec J100/J101 to J17/J18 pair is excluded from panel-vs-main clash classification." + ] +} diff --git a/hardware/stack/actual-parts-full-assembly-validation.json b/hardware/stack/actual-parts-full-assembly-validation.json new file mode 100644 index 0000000..c6801ba --- /dev/null +++ b/hardware/stack/actual-parts-full-assembly-validation.json @@ -0,0 +1,39 @@ +{ + "status": "PASS", + "assembly": "panel/cad/RADIAN_actual_parts_full_assembly.step", + "renders": [ + "panel/previews/actual_parts_full_assembly_iso.png", + "panel/previews/actual_parts_full_assembly_side.png", + "panel/previews/actual_parts_full_assembly_front.png" + ], + "source_of_truth": "native KiCad component-filter STEP exports", + "color_persistence": "PASS: 715 colored children, 0 missing", + "u8_alignment": { + "reference": "U8 / H11L1M", + "native_footprint_center_mm": [ + 48.0, + 139.0 + ], + "raw_kicad_step_expected_center_mm": [ + 48.0, + -139.0 + ], + "raw_kicad_step_actual_bbox_center_mm": [ + 48.0, + -139.0 + ], + "center_error_mm": [ + 0.0, + 0.0 + ], + "model": "courant/deliverables/cad/models/DIP6_W7.62_U8_centered.step", + "pin_alignment": "PASS: six STEP lead centers map exactly to six native footprint pads under KiCad Y inversion" + }, + "collision_validation": { + "status": "PASS", + "panel_main_unintended_clashes": [], + "rear_guard_or_dock_clashes": [], + "intentional_stack_overlap": "P_STACK <-> M_STACK excluded; validated by direct-stack-validation.json" + }, + "placeholder_component_geometry_included": false +} diff --git a/hardware/stack/actual-parts-render-validation.json b/hardware/stack/actual-parts-render-validation.json new file mode 100644 index 0000000..6605439 --- /dev/null +++ b/hardware/stack/actual-parts-render-validation.json @@ -0,0 +1,242 @@ +{ + "status": "PASS", + "assembly": "panel/cad/RADIAN_actual_parts_stack.step", + "panel_board_occ_bbox_mm": [ + 18.0, + 10.0, + -10.0393, + 198.5, + 118.0, + -7.6507 + ], + "main_board_occ_bbox_mm": [ + 8.0, + 14.25, + -31.5686, + 168.0, + 114.25, + -29.1214 + ], + "physical_faces": { + "panel_back_face_z_mm": -9.6, + "main_front_face_z_mm": -29.59, + "pcb_face_gap_mm": 19.99, + "target_gap_mm": 19.99, + "method": "raw KiCad STEP board faces + exact product transforms; transformed OCC bounding boxes are not used for face spacing" + }, + "actual_part_collision_validation": { + "component_vs_physical_enclosure_clashes": [], + "non_samtec_panel_vs_main_clashes": [], + "non_samtec_panel_vs_main_overlap_mm3": 0.0 + }, + "group_bboxes_mm": { + "panel_board": [ + 18.0, + 10.0, + -10.039, + 198.5, + 118.0, + -7.651 + ], + "panel_pots": [ + 32.298, + 64.493, + -11.839, + 119.701, + 103.154, + 12.588 + ], + "panel_encoder": [ + 34.824, + 35.0, + -10.687, + 49.176, + 51.0, + 18.504 + ], + "panel_mode": [ + 147.07, + 78.15, + -10.687, + 153.93, + 90.85, + 17.661 + ], + "panel_jacks": [ + 182.0, + 20.227, + -11.567, + 191.0, + 105.0, + 7.746 + ], + "panel_leds": [ + 122.475, + 106.089, + -10.505, + 155.918, + 109.911, + 0.32 + ], + "panel_samtec": [ + 30.109, + 48.859, + -18.195, + 126.475, + 74.725, + -7.145 + ], + "panel_wurth": [ + 160.5, + 53.82, + -18.829, + 178.425, + 89.253, + -4.6 + ], + "panel_molex": [ + 23.46, + 26.1, + -21.385, + 138.62, + 54.9, + -6.125 + ], + "panel_buttons": [ + 114.562, + 22.0, + -14.032, + 149.838, + 29.0, + -6.185 + ], + "panel_ics": [ + 32.6, + 23.527, + -8.013, + 154.0, + 69.479, + -6.226 + ], + "panel_resistors": [ + 32.298, + 18.598, + -11.839, + 164.802, + 103.154, + 12.676 + ], + "panel_capacitors": [ + 21.749, + 16.749, + -8.006, + 157.801, + 74.626, + -5.504 + ], + "panel_power_discretes": [ + 22.15, + 21.7, + -8.03, + 167.25, + 66.817, + -3.005 + ], + "main_board": [ + 8.0, + 14.25, + -31.569, + 168.0, + 114.25, + -29.121 + ], + "main_ics": [ + 29.5, + 21.563, + -32.805, + 140.2, + 88.75, + -25.663 + ], + "main_service_connectors": [ + 14.825, + 21.075, + -33.065, + 113.54, + 101.79, + -18.835 + ], + "main_samtec": [ + 30.046, + 48.796, + -31.855, + 126.54, + 74.79, + -14.205 + ], + "main_resistors": [ + 21.198, + 19.848, + -29.507, + 159.802, + 98.652, + -29.053 + ], + "main_capacitors": [ + 17.999, + 19.849, + -31.986, + 152.801, + 100.501, + -27.004 + ], + "main_diodes": [ + 22.1, + 23.433, + -29.514, + 144.25, + 47.767, + -28.238 + ], + "main_inductors": [ + 22.974, + 39.224, + -29.512, + 27.026, + 89.276, + -26.479 + ], + "main_oscillators": [ + 66.397, + 81.995, + -29.509, + 69.605, + 91.503, + -28.858 + ] + }, + "model_policy": { + "native_placement": "all component geometry is exported component-filtered by KiCad from the canonical .kicad_pcb files, so PCB placement/orientation is native", + "real_open_models": [ + "panel RV1-RV6 PTV09A family body with selected 20 mm shaft", + "panel J301-J305 PJ398SM open mechanical CAD", + "panel SW3/SW4 Omron B3F model" + ], + "package_accurate_models": [ + "LED 3 mm green package", + "TPS54302 SOT-23-6", + "OPA2192 SOIC-8", + "BAT54S SOT-23", + "standard passives/fuses/SMB packages", + "mainboard IC/passive package models" + ], + "drawing_reference_models": [ + "Samtec J17/J18/J100/J101", + "Molex J1-J4", + "panel PEC11R encoder", + "panel E-Switch MODE", + "panel SRP7050TA inductor" + ], + "not_claimed_as_vendor_step": "drawing-reference models above remain explicit mechanical references, not manufacturer STEP downloads" + } +} diff --git a/hardware/stack/actual_parts/actual_part_collision_report.json b/hardware/stack/actual_parts/actual_part_collision_report.json new file mode 100644 index 0000000..0f750a4 --- /dev/null +++ b/hardware/stack/actual_parts/actual_part_collision_report.json @@ -0,0 +1,6 @@ +{ + "status": "PASS", + "panel_main_unintended_clashes": [], + "rear_guard_or_dock_clashes": [], + "intentional_stack_overlap": "P_STACK <-> M_STACK excluded; validated by direct-stack-validation.json" +} diff --git a/hardware/stack/actual_parts/actual_parts_report.json b/hardware/stack/actual_parts/actual_parts_report.json new file mode 100644 index 0000000..a3b0231 --- /dev/null +++ b/hardware/stack/actual_parts/actual_parts_report.json @@ -0,0 +1,61 @@ +{ + "status": "PASS", + "panel_native_board": "/home/ik/ChatGPT/Courant/hardware/panel/design/radian_panel.kicad_pcb", + "main_native_board": "/home/ik/ChatGPT/Courant/hardware/courant/deliverables/courant.kicad_pcb", + "dedicated_populated_board_cad": { + "panel": "panel/cad/RADIAN_actual_parts_panel_board.step", + "main": "panel/cad/RADIAN_actual_parts_main_board.step" + }, + "dedicated_populated_board_renders": [ + "panel/previews/actual_parts_panel_board_top.png", + "panel/previews/actual_parts_panel_board_bottom.png", + "panel/previews/actual_parts_main_board_top.png", + "panel/previews/actual_parts_main_board_bottom.png" + ], + "panel_groups": { + "P_POTS": "RV1,RV2,RV3,RV4,RV5,RV6", + "P_ENCODER": "ENC1", + "P_MODE": "SW1", + "P_JACKS": "J301,J302,J303,J304,J305", + "P_LEDS": "D10,D11,D12,D13", + "P_STACK": "J100,J101", + "P_WURTH": "J200,JP1", + "P_MOLEX": "J201,J202,J306", + "P_BUTTONS": "SW3,SW4", + "P_ACTIVE": "U1,U2,D1,D2,D3,D4,L1,F1,F2", + "P_PASSIVES": "R*,C*" + }, + "main_groups": { + "M_STACK": "J17,J18", + "M_MOLEX": "J1,J2,J3,J4", + "M_ICS": "U*,Y*", + "M_PASSIVES": "R*,C*", + "M_MAGNETICS": "L*", + "M_DIODES": "D*" + }, + "collision_validation": "Use direct-stack-validation.json and case_direct_stack_update.json; this renderer preserves native KiCad placement.", + "panel_transform": { + "x": 0, + "y": 128.5, + "z": -9.6 + }, + "main_transform": { + "x": -12, + "y": 164.25, + "z": -31.1 + }, + "actual_or_package_models": [ + "Bourns PTV09A family geometry aligned to PTV09A-4020F-B103 footprint/20 mm shaft", + "QingPu/Thonk PJ398SM open mechanical CAD with knurled nut", + "Omron B3F-1000 package geometry", + "3 mm green LED package geometry", + "all selected Wurth/Molex/Samtec and mainboard package STEP models already attached in KiCad" + ], + "drawing_derived_remaining": [ + "ENC1 Bourns PEC11R-4220F-S0024", + "SW1 E-Switch 100SP1T1B1M2REH", + "Samtec J100/J101/J17/J18", + "Molex mainboard J1-J4" + ], + "note": "No generic white component envelopes are used in this final assembly; component placement comes from KiCad STEP export." +} diff --git a/hardware/stack/actual_parts/final_actual_cad_validation.json b/hardware/stack/actual_parts/final_actual_cad_validation.json new file mode 100644 index 0000000..5c619da --- /dev/null +++ b/hardware/stack/actual_parts/final_actual_cad_validation.json @@ -0,0 +1,57 @@ +{ + "status": "PASS", + "final_assembly": "panel/cad/RADIAN_actual_parts_full_assembly.step", + "colored_step_children": 715, + "children_missing_explicit_color": [], + "near_white_default_children": [], + "u8": { + "reference": "U8 / H11L1M", + "native_footprint_center_mm": [ + 48.0, + 139.0 + ], + "raw_kicad_step_expected_center_mm": [ + 48.0, + -139.0 + ], + "raw_kicad_step_actual_bbox_center_mm": [ + 48.0, + -139.0 + ], + "center_error_mm": [ + 0.0, + 0.0 + ], + "model": "courant/deliverables/cad/models/DIP6_W7.62_U8_centered.step", + "pin_alignment": "PASS: six STEP lead centers map exactly to six native footprint pads under KiCad Y inversion" + }, + "panel_drc": { + "violations": 0, + "unconnected": 0 + }, + "main_drc": { + "violations": 0, + "unconnected": 0 + }, + "direct_stack": { + "status": "PASS", + "checked": 40, + "matched": 40 + }, + "actual_part_collisions": { + "status": "PASS", + "panel_main_unintended_clashes": [], + "rear_guard_or_dock_clashes": [], + "intentional_stack_overlap": "P_STACK <-> M_STACK excluded; validated by direct-stack-validation.json" + }, + "model_policy": { + "actual_or_package_geometry": "PTV09A family, PJ398SM, Omron B3F, LEDs, all normal IC/passive packages and selected Wurth/Molex models", + "explicit_drawing_derived_only": [ + "PEC11R encoder", + "E-Switch MODE", + "Samtec stack pair", + "mainboard Molex J1-J4" + ], + "generic_white_component_envelopes": "NONE" + } +} diff --git a/hardware/stack/actual_parts/j1_power_orientation_validation.json b/hardware/stack/actual_parts/j1_power_orientation_validation.json new file mode 100644 index 0000000..c0f048b --- /dev/null +++ b/hardware/stack/actual_parts/j1_power_orientation_validation.json @@ -0,0 +1,13 @@ +{ + "status": "PASS", + "reference": "J1", + "part": "Molex 22-23-2021", + "board_center_mm": [30.0, 65.0], + "left_board_edge_mm": 19.95, + "model_rotation_about_footprint_deg": 180.0, + "lock_ramp_before_step_x_mm": 32.72, + "lock_ramp_after_step_x_mm": 27.28, + "orientation": "locking/friction-ramp side faces the left board edge", + "electrical_geometry": "pads and copper unchanged; J1.1 remains VIN5 and J1.2 remains GND", + "drc": "PASS: 0 violations, 0 unconnected items" +} diff --git a/hardware/stack/add_production_io_parts.py b/hardware/stack/add_production_io_parts.py new file mode 100644 index 0000000..e4ade82 --- /dev/null +++ b/hardware/stack/add_production_io_parts.py @@ -0,0 +1,42 @@ +#!/usr/bin/env python3 +import pcbnew +from pathlib import Path +ROOT=Path('/home/ik/ChatGPT/Courant/hardware') +P=str(ROOT/'panel/design/radian_panel.kicad_pcb') +LIB=str(ROOT/'panel/library/RadianPanel.pretty') +b=pcbnew.LoadBoard(P) +def net(name): + n=b.FindNet(name) + if n:return n + b.Add(pcbnew.NETINFO_ITEM(b,name)) + return b.FindNet(name) +for n in ['unconnected-(J200-Pad1)','unconnected-(J200-Pad2)', + 'unconnected-(J201-Pad2)','unconnected-(J306-Pad1)', + 'unconnected-(J306-Pad2)','unconnected-(J306-Pad3)']: + net(n) +def put(name,ref,value,x,y,nets): + f=pcbnew.FootprintLoad(LIB,name) + if f is None:raise RuntimeError(name) + f.SetReference(ref);f.SetValue(value) + f.SetPosition(pcbnew.VECTOR2I(pcbnew.FromMM(x),pcbnew.FromMM(y))) + f.SetFPIDAsString('RadianPanel:'+name) + for pad in f.Pads(): + nn=nets.get(pad.GetNumber()) + if nn:pad.SetNet(net(nn)) + else:pad.SetNetCode(0) + b.Add(f) +put('Wurth_61201021621_B','J200','61201021621',175.27,59.42, + {**{'1':'unconnected-(J200-Pad1)','2':'unconnected-(J200-Pad2)'}, + **{str(i):'GND' for i in range(3,9)},'9':'RACK_12V','10':'RACK_12V'}) +put('Wurth_450301014042_B','JP1','450301014042',165.5,40.5, + {'1':'MOD_IN','2':'MOD_BIPOLAR','3':'MOD_RAW'}) +put('Wurth_694106402002_B','J201','694106402002',100.0,95.0, + {'1':'DESKTOP_12V','2':'unconnected-(J201-Pad2)','3':'GND'}) +put('SameSky_SD-50BV','J306','SD-50BV',85.0,85.5, + {'1':'unconnected-(J306-Pad1)','2':'unconnected-(J306-Pad2)', + '3':'unconnected-(J306-Pad3)','4':'MIDI4','5':'MIDI5'}) +put('TagConnect_TC2030_IDC_NL_B','J202','TC2030-IDC-NL',155.0,96.0, + {'1':'V3V3','2':'JTAG_TMS','3':'JTAG_TDI', + '4':'JTAG_TCK','5':'GND','6':'JTAG_TDO'}) +pcbnew.SaveBoard(P,b,True) +print('added production footprints') diff --git a/hardware/stack/apply_actual_panel_models.py b/hardware/stack/apply_actual_panel_models.py new file mode 100644 index 0000000..d1a0f21 --- /dev/null +++ b/hardware/stack/apply_actual_panel_models.py @@ -0,0 +1,88 @@ +#!/usr/bin/env python3 +from pathlib import Path +import pcbnew, re, shutil + +ROOT=Path('/home/ik/ChatGPT/Courant/hardware') +PANEL=ROOT/'panel' +BOARD=PANEL/'design/radian_panel.kicad_pcb' +LIB=PANEL/'library/RadianPanel.pretty' +MODELS=PANEL/'cad/models' +K='$'+'{KIPRJMOD}/../cad/models/' + +# Store the open/actual component CAD in the project. +shutil.copy('/tmp/musicvis/Schematic_PCB/Music_Visualizer/Project_Library/PTV09A_Pot_Vertical/PTV09A-4225F-B104.step', + MODELS/'SOURCE_Bourns_PTV09A_family.step') +shutil.copy('/tmp/audiojacks/AudioJacks.3dshapes/PJ398SM_Knurl_nut.step', + MODELS/'QingPu_PJ398SM_Knurl_actual.step') +shutil.copy('/usr/share/kicad/3dmodels/Button_Switch_THT.3dshapes/SW_TH_Tactile_Omron_B3F-100x.step', + MODELS/'SOURCE_Omron_B3F_100x.step') +shutil.copy('/usr/share/kicad/3dmodels/LED_THT.3dshapes/LED_D3.0mm_Green.step', + MODELS/'SOURCE_LED_D3_Green.step') + +paths={ + 'PTV':K+'Bourns_PTV09A_4020F_family_actual.step', + 'PEC':K+'Bourns_PEC11R_4220F_S0024_drawing_reference.step', + 'SW1':K+'E_Switch_100SP1T1B1M2REH_drawing_reference.step', + 'JACK':K+'QingPu_PJ398SM_Knurl_actual.step', + 'B3F':K+'Omron_B3F_1000_centered.step', + 'LED':K+'Kingbright_L934GD_package_green_centered.step', +} + +b=pcbnew.LoadBoard(str(BOARD)) +groups={ + 'PTV':[f'RV{i}' for i in range(1,7)], + 'PEC':['ENC1'], + 'SW1':['SW1'], + 'JACK':[f'J30{i}' for i in range(1,6)], + 'B3F':['SW3','SW4'], + 'LED':[f'D{i}' for i in range(10,14)], +} + +def set_model(fp,path): + ms=fp.Models(); ms.clear() + m=pcbnew.FP_3DMODEL(); m.m_Filename=path; m.m_Show=True; m.m_Opacity=1.0 + m.m_Scale.x=m.m_Scale.y=m.m_Scale.z=1.0 + m.m_Offset.x=m.m_Offset.y=m.m_Offset.z=0.0 + m.m_Rotation.x=m.m_Rotation.y=m.m_Rotation.z=0.0 + ms.append(m) + +fps={f.GetReference():f for f in b.GetFootprints()} +for key,refs in groups.items(): + for ref in refs: + set_model(fps[ref],paths[key]) +pcbnew.SaveBoard(str(BOARD),b,True) + +# Keep the corresponding footprint library definitions synchronized. +fp_names={ + 'PTV':'Bourns_PTV09A4_RearFacing.kicad_mod', + 'PEC':'Bourns_PEC11R4_RearFacing_Switch.kicad_mod', + 'SW1':'E_Switch_100SP_M2.kicad_mod', + 'JACK':'WQP518MA_PJ398SM_Vertical.kicad_mod', + 'B3F':'SW_PUSH_6x6_P6.5x4.5.kicad_mod', + 'LED':'LED_D3.0_P2.54.kicad_mod', +} +def replace_model(path,new_model): + s=path.read_text() + start=s.find('(model ') + if start<0: + idx=s.rfind(')') + block=f'\n (model "{new_model}"\n (offset (xyz 0 0 0))\n (scale (xyz 1 1 1))\n (rotate (xyz 0 0 0))\n )\n' + s=s[:idx]+block+s[idx:] + else: + depth=0; end=None + for i in range(start,len(s)): + if s[i]=='(': depth+=1 + elif s[i]==')': + depth-=1 + if depth==0: + end=i+1; break + block=f'(model "{new_model}"\n (offset (xyz 0 0 0))\n (scale (xyz 1 1 1))\n (rotate (xyz 0 0 0))\n )' + s=s[:start]+block+s[end:] + path.write_text(s) + +for key,name in fp_names.items(): + replace_model(LIB/name,paths[key]) + +for key,refs in groups.items(): + print(key,paths[key],refs) +print('ACTUAL_PANEL_MODELS_APPLIED') diff --git a/hardware/stack/apply_colored_actual_models_to_kicad.py b/hardware/stack/apply_colored_actual_models_to_kicad.py new file mode 100644 index 0000000..837c3a2 --- /dev/null +++ b/hardware/stack/apply_colored_actual_models_to_kicad.py @@ -0,0 +1,64 @@ +#!/usr/bin/env python3 +from pathlib import Path +import shutil, datetime, pcbnew + +ROOT=Path('/home/ik/ChatGPT/Courant') +MAIN=ROOT/'hardware/courant/deliverables/courant.kicad_pcb' +PANEL=ROOT/'hardware/panel/design/radian_panel.kicad_pcb' +stamp=datetime.datetime.now().strftime('%Y%m%dT%H%M%S') + +for p in (MAIN,PANEL): + backup=p.with_name(p.stem+f'.before_colored_actual_models_{stamp}'+p.suffix) + shutil.copy2(p,backup) + print('BACKUP',backup) + +def set_model(f,path,off=(0,0,0),rot=(0,0,0)): + ms=f.Models(); ms.clear() + m=pcbnew.FP_3DMODEL() + m.m_Filename=path; m.m_Show=True; m.m_Opacity=1.0 + m.m_Scale.x=m.m_Scale.y=m.m_Scale.z=1.0 + m.m_Offset.x,m.m_Offset.y,m.m_Offset.z=off + m.m_Rotation.x,m.m_Rotation.y,m.m_Rotation.z=rot + ms.append(m) + +b=pcbnew.LoadBoard(str(MAIN)) +fps={f.GetReference():f for f in b.GetFootprints() if f.GetReference()} +set_model(fps['U8'], + '${KICAD10_3DMODEL_DIR}/Package_DIP.3dshapes/DIP-6_W7.62mm.step', + (-3.81,2.54,0)) +pcbnew.SaveBoard(str(MAIN),b,True) +print('MAIN_UPDATED',MAIN) +b=pcbnew.LoadBoard(str(PANEL)) +fps={f.GetReference():f for f in b.GetFootprints() if f.GetReference()} + +M='${KIPRJMOD}/../cad/models/' +for ref in ['RV1','RV2','RV3','RV4','RV5','RV6']: + set_model(fps[ref],M+'Bourns_PTV09A_4020F_family_actual_colored.step') +set_model(fps['ENC1'],M+'Bourns_PEC11R_4220F_S0024_drawing_reference_colored.step') +set_model(fps['SW1'],M+'E_Switch_100SP1T1B1M2REH_drawing_reference_colored.step') +set_model(fps['L1'],M+'Bourns_SRP7050TA_100M_drawing_reference_colored.step') +for ref in ['TP1','TP2','TP3','TP4','TP5']: + set_model(fps[ref],M+'TestPoint_D2_colored.step') + +for ref in ['D10','D11','D12','D13']: + set_model(fps[ref], + '${KICAD10_3DMODEL_DIR}/LED_THT.3dshapes/LED_D3.0mm_Green.step', + (-1.27,0,0)) +for ref in ['SW3','SW4']: + set_model(fps[ref], + '${KICAD10_3DMODEL_DIR}/Button_Switch_THT.3dshapes/SW_TH_Tactile_Omron_B3F-100x.step', + (-3.25,2.25,0)) +for ref in ['J201','J306']: + set_model(fps[ref], + '${KICAD10_3DMODEL_DIR}/Connector_Molex.3dshapes/Molex_KK-254_AE-6410-02A_1x02_P2.54mm_Vertical.step', + (-1.27,0,0)) +set_model(fps['J202'], + '${KICAD10_3DMODEL_DIR}/Connector_Molex.3dshapes/Molex_KK-254_AE-6410-06A_1x06_P2.54mm_Vertical.step', + (-6.35,0,0)) + +set_model(fps['JP1'],M+'production/Wurth_450301014042.stp') +set_model(fps['J200'],M+'production/Wurth_61201021621.stp', + (0.325,0,4.675),(0,0,-90)) + +pcbnew.SaveBoard(str(PANEL),b,True) +print('PANEL_UPDATED',PANEL) diff --git a/hardware/stack/apply_direct_stack_models.py b/hardware/stack/apply_direct_stack_models.py new file mode 100755 index 0000000..2744cfd --- /dev/null +++ b/hardware/stack/apply_direct_stack_models.py @@ -0,0 +1,62 @@ +#!/usr/bin/env python3 +"""Attach drawing-derived Samtec stack models to both native KiCad boards/libraries.""" +from pathlib import Path +import pcbnew + +ROOT = Path(__file__).resolve().parents[1] +MODEL_BASE = '${KIPRJMOD}/../../stack/models/' +IPT_MODEL = MODEL_BASE + 'Samtec_IPT1-110-06-L-D_drawing_reference.step' +IPS_MODEL = MODEL_BASE + 'Samtec_IPS1-110-01-L-D_drawing_reference.step' + +PANEL_BOARD = ROOT/'panel/design/radian_panel.kicad_pcb' +MAIN_BOARD = ROOT/'courant/deliverables/courant.kicad_pcb' +PANEL_LIB = ROOT/'panel/library/RadianPanel.pretty' +MAIN_LIB = ROOT/'courant/deliverables/RadianMain.pretty' +FP_NAME = 'Stack_2x10_P2.54' + + +def set_single_model(fp, filename): + models = fp.Models() + models.clear() + m = pcbnew.FP_3DMODEL() + m.m_Filename = filename + m.m_Show = True + m.m_Opacity = 1.0 + m.m_Scale.x = m.m_Scale.y = m.m_Scale.z = 1.0 + m.m_Offset.x = m.m_Offset.y = m.m_Offset.z = 0.0 + m.m_Rotation.x = m.m_Rotation.y = m.m_Rotation.z = 0.0 + models.append(m) + + +def update_board(path, refs, filename, expected_value): + b = pcbnew.LoadBoard(str(path)) + by_ref = {f.GetReference():f for f in b.GetFootprints()} + for ref in refs: + fp = by_ref[ref] + if fp.GetValue() != expected_value: + raise RuntimeError(f'{path}: {ref} value {fp.GetValue()} != {expected_value}') + set_single_model(fp, filename) + pcbnew.SaveBoard(str(path), b, True) + + +def update_library(lib, filename, expected_value): + fp = pcbnew.FootprintLoad(str(lib), FP_NAME) + if fp is None: + raise RuntimeError(f'cannot load {lib}:{FP_NAME}') + fp.SetValue(expected_value) + set_single_model(fp, filename) + pcbnew.FootprintSave(str(lib), fp) + + +def main(): + update_board(PANEL_BOARD, ['J100','J101'], IPS_MODEL, 'IPS1-110-01-L-D') + update_board(MAIN_BOARD, ['J17','J18'], IPT_MODEL, 'IPT1-110-06-L-D') + update_library(PANEL_LIB, IPS_MODEL, 'IPS1-110-01-L-D') + update_library(MAIN_LIB, IPT_MODEL, 'IPT1-110-06-L-D') + print('attached stack reference models:') + print(' panel J100/J101 ->', IPS_MODEL) + print(' main J17/J18 ->', IPT_MODEL) + + +if __name__ == '__main__': + main() diff --git a/hardware/stack/autoroute_prod_extensions.py b/hardware/stack/autoroute_prod_extensions.py new file mode 100644 index 0000000..a71a52c --- /dev/null +++ b/hardware/stack/autoroute_prod_extensions.py @@ -0,0 +1,175 @@ +#!/usr/bin/env python3 +import math, heapq +from pathlib import Path +import pcbnew + +P=Path('/home/ik/ChatGPT/Courant/hardware/panel/design/radian_panel.kicad_pcb') +b=pcbnew.LoadBoard(str(P)) +STEP=.25 +NEW_W=.25 +CLEAR=.20 +EXTRA=.04 +PAD_INFLATE=CLEAR+NEW_W/2+EXTRA + +def mm(v): return pcbnew.ToMM(v) +def iu(v): return pcbnew.FromMM(v) +def vec(x,y): return pcbnew.VECTOR2I(iu(x),iu(y)) +def pad_by(ref,net): + f=next(x for x in b.GetFootprints() if x.GetReference()==ref) + return next(p for p in f.Pads() if p.GetNetname()==net) +def pos(item): + p=item.GetPosition(); return (mm(p.x),mm(p.y)) +def point_seg_dist(x,y,x1,y1,x2,y2): + dx=x2-x1;dy=y2-y1 + if dx==0 and dy==0:return math.hypot(x-x1,y-y1) + t=max(0,min(1,((x-x1)*dx+(y-y1)*dy)/(dx*dx+dy*dy))) + return math.hypot(x-(x1+t*dx),y-(y1+t*dy)) +def board_ok(x,y): + if not (18.45<=x<=198.05 and 10.95<=y<=118.05): return False + # Remaining service cutout. + if 116.05<=x<=149.95 and 79.55<=y<=93.45:return False + # Mid-board right-side neck is absent between these y extents. + if 162.05<=x<=171.95 and 19.05<=y<=109.45:return False + return True +def make_blocked(net, region): + xmin,xmax,ymin,ymax=region + nx=int(round((xmax-xmin)/STEP))+1 + ny=int(round((ymax-ymin)/STEP))+1 + blocked=set() + def cell(i,j):return (xmin+i*STEP,ymin+j*STEP) + def mark_box(ax,bx,ay,by): + i0=max(0,int(math.floor((ax-xmin)/STEP)));i1=min(nx-1,int(math.ceil((bx-xmin)/STEP))) + j0=max(0,int(math.floor((ay-ymin)/STEP)));j1=min(ny-1,int(math.ceil((by-ymin)/STEP))) + for i in range(i0,i1+1): + for j in range(j0,j1+1):blocked.add((i,j)) + # Board voids/edges. + for i in range(nx): + for j in range(ny): + x,y=cell(i,j) + if not board_ok(x,y):blocked.add((i,j)) + # Pads on B.Cu; own-net copper is legal. + for f in b.GetFootprints(): + for p in f.Pads(): + if not p.IsOnLayer(pcbnew.B_Cu):continue + if p.GetNetname()==net:continue + q=p.GetPosition(); sx=mm(p.GetSize().x);sy=mm(p.GetSize().y) + cx,cy=mm(q.x),mm(q.y) + mark_box(cx-sx/2-PAD_INFLATE,cx+sx/2+PAD_INFLATE, + cy-sy/2-PAD_INFLATE,cy+sy/2+PAD_INFLATE) + # Existing B.Cu tracks and all vias; own-net copper is legal. + for t in b.GetTracks(): + if t.GetNetname()==net:continue + if isinstance(t,pcbnew.PCB_VIA): + q=t.GetPosition();cx,cy=mm(q.x),mm(q.y) + try:w=mm(t.GetWidth(pcbnew.B_Cu)) + except:w=.8 + r=w/2+PAD_INFLATE + i0=max(0,int((cx-r-xmin)//STEP));i1=min(nx-1,int(math.ceil((cx+r-xmin)/STEP))) + j0=max(0,int((cy-r-ymin)//STEP));j1=min(ny-1,int(math.ceil((cy+r-ymin)/STEP))) + for i in range(i0,i1+1): + for j in range(j0,j1+1): + x,y=cell(i,j) + if math.hypot(x-cx,y-cy)<=r:blocked.add((i,j)) + elif t.GetLayer()==pcbnew.B_Cu: + a=t.GetStart();c=t.GetEnd();x1,y1,x2,y2=mm(a.x),mm(a.y),mm(c.x),mm(c.y) + r=mm(t.GetWidth())/2+PAD_INFLATE + i0=max(0,int(math.floor((min(x1,x2)-r-xmin)/STEP)));i1=min(nx-1,int(math.ceil((max(x1,x2)+r-xmin)/STEP))) + j0=max(0,int(math.floor((min(y1,y2)-r-ymin)/STEP)));j1=min(ny-1,int(math.ceil((max(y1,y2)+r-ymin)/STEP))) + for i in range(i0,i1+1): + for j in range(j0,j1+1): + x,y=cell(i,j) + if point_seg_dist(x,y,x1,y1,x2,y2)<=r:blocked.add((i,j)) + return blocked,nx,ny +def astar(net,start,goal,region): + xmin,xmax,ymin,ymax=region + blocked,nx,ny=make_blocked(net,region) + def snap(p): + return (max(0,min(nx-1,round((p[0]-xmin)/STEP))), + max(0,min(ny-1,round((p[1]-ymin)/STEP)))) + s=snap(start);g=snap(goal) + blocked.discard(s);blocked.discard(g) + dirs=[(1,0,1),(-1,0,1),(0,1,1),(0,-1,1), + (1,1,math.sqrt(2)),(1,-1,math.sqrt(2)),(-1,1,math.sqrt(2)),(-1,-1,math.sqrt(2))] + pq=[(0,0,s,None)];dist={(s,None):0};prev={} + end=None + while pq: + _,cost,u,last=heapq.heappop(pq) + if cost!=dist.get((u,last)):continue + if u==g:end=(u,last);break + for dx,dy,base in dirs: + v=(u[0]+dx,u[1]+dy) + if v[0]<0 or v[0]>=nx or v[1]<0 or v[1]>=ny or v in blocked:continue + turn=0 if last is None or last==(dx,dy) else .08 + nc=cost+base+turn + key=(v,(dx,dy)) + if nc{goal}') + cells=[];cur=end + while True: + cells.append(cur[0]) + if cur[0]==s and cur[1] is None:break + cur=prev[cur] + cells.reverse() + pts=[(xmin+i*STEP,ymin+j*STEP) for i,j in cells] + # Keep only direction changes. + out=[pts[0]] + lastdir=None + for i in range(1,len(pts)): + dx=round((pts[i][0]-pts[i-1][0])/STEP);dy=round((pts[i][1]-pts[i-1][1])/STEP) + d=(dx,dy) + if lastdir is not None and d!=lastdir:out.append(pts[i-1]) + lastdir=d + out.append(pts[-1]) + # exact endpoints + if out[0]!=start:out=[start]+out + if out[-1]!=goal:out.append(goal) + return out +def add_track(net,pts,width=NEW_W): + n=b.FindNet(net) + for a,c in zip(pts,pts[1:]): + if math.hypot(c[0]-a[0],c[1]-a[1])<.01:continue + t=pcbnew.PCB_TRACK(b);t.SetNet(n);t.SetLayer(pcbnew.B_Cu);t.SetWidth(iu(width)) + t.SetStart(vec(*a));t.SetEnd(vec(*c));b.Add(t) +def add_via(net,p,width=.65,drill=.3): + v=pcbnew.PCB_VIA(b);v.SetNet(b.FindNet(net));v.SetPosition(vec(*p)) + v.SetWidth(iu(width));v.SetDrill(iu(drill));v.SetLayerPair(pcbnew.F_Cu,pcbnew.B_Cu);b.Add(v) + +# Routes join the preserved, already-validated legacy endpoints. +routes=[ + ('JTAG_TMS',pos(pad_by('J202','JTAG_TMS')),(124.65,99.5),(120,161,93.55,108)), + ('JTAG_TDI',pos(pad_by('J202','JTAG_TDI')),(127.19,99.5),(120,161,93.55,108)), + ('JTAG_TDO',pos(pad_by('J202','JTAG_TDO')),(129.73,99.5),(120,161,93.55,108)), + ('JTAG_TCK',pos(pad_by('J202','JTAG_TCK')),(132.27,99.5),(120,161,93.55,108)), + ('V3V3',pos(pad_by('J202','V3V3')),(137.35,99.5),(120,161,93.55,108)), + ('MIDI4',pos(pad_by('J306','MIDI4')),(58.77,89.5),(54,90,67.6,103)), + ('MIDI5',pos(pad_by('J306','MIDI5')),(54 and 56.23,89.5),(54,90,67.6,103)), + ('DESKTOP_12V',pos(pad_by('J201','DESKTOP_12V')),(27.27,76.5),(19,105,67.6,104)), +] +escapes={ + 'JTAG_TMS':(156.27,93.8), + 'JTAG_TDI':(155.0,98.2), + 'JTAG_TDO':(153.73,93.8), + 'JTAG_TCK':(155.0,93.8), + 'V3V3':(156.27,98.2), +} +for net,start,goal,region in routes: + ast_start=escapes.get(net,start) + pts=astar(net,ast_start,goal,region) + if ast_start!=start: + pts=[start,ast_start]+pts[1:] + print(net,len(pts),pts) + add_track(net,pts) + if net in {'JTAG_TDO','JTAG_TCK','DESKTOP_12V'}: + add_via(net,goal,.65 if net!='DESKTOP_12V' else .8,.3 if net!='DESKTOP_12V' else .35) + +# Ground target goes straight into the existing internal GND planes. +g=pos(pad_by('J202','GND')) +vg=(153.73,99.0) +add_track('GND',[g,vg]) +add_via('GND',vg,.7,.3) + +pcbnew.SaveBoard(str(P),b,True) +print('AUTO_ROUTE_DONE') diff --git a/hardware/stack/build_colored_actual_kicad_models.py b/hardware/stack/build_colored_actual_kicad_models.py new file mode 100644 index 0000000..58e5095 --- /dev/null +++ b/hardware/stack/build_colored_actual_kicad_models.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python3 +from pathlib import Path +import cadquery as cq + +ROOT=Path('/home/ik/ChatGPT/Courant') +MODELS=ROOT/'hardware/panel/cad/models' + +METAL=(0.72,0.74,0.76) +DARK=(0.055,0.060,0.065) +INDUCTOR=(0.10,0.105,0.11) +GOLD=(0.78,0.55,0.15) + +SPECS={ + 'Bourns_PTV09A_4020F_family_actual.step':[ + METAL,METAL,METAL,METAL,METAL,DARK], + 'Bourns_PEC11R_4220F_S0024_drawing_reference.step':[ + METAL,METAL,METAL,METAL,METAL,METAL,METAL,METAL,METAL,METAL], + 'E_Switch_100SP1T1B1M2REH_drawing_reference.step':[ + DARK,METAL,METAL,METAL,METAL,METAL], + 'Bourns_SRP7050TA_100M_drawing_reference.step':[ + INDUCTOR,METAL,METAL], + 'TestPoint_D2.step':[GOLD], +} + +def colorize(src, colors): + path=MODELS/src + shape=cq.importers.importStep(str(path)).val() + solids=list(shape.Solids()) + if len(solids)!=len(colors): + raise RuntimeError(f'{src}: expected {len(colors)} solids, got {len(solids)}') + out=path.with_name(path.stem+'_colored.step') + assy=cq.Assembly(name=path.stem+'_COLORED') + for i,(solid,rgb) in enumerate(zip(solids,colors)): + assy.add(solid,name=f'{path.stem}_{i:02d}',color=cq.Color(*rgb)) + assy.export(str(out)) + check=cq.Assembly.importStep(str(out)) + missing=[c.name for c in check.children if c.color is None] + if missing: + raise RuntimeError(f'{out}: colors did not persist: {missing}') + before=shape.BoundingBox() + after=cq.importers.importStep(str(out)).val().BoundingBox() + a=(before.xmin,before.ymin,before.zmin,before.xmax,before.ymax,before.zmax) + b=(after.xmin,after.ymin,after.zmin,after.xmax,after.ymax,after.zmax) + if max(abs(x-y) for x,y in zip(a,b)) > 1e-6: + raise RuntimeError(f'{out}: geometry bbox changed: {a} -> {b}') + print('COLORED_MODEL_PASS',out,len(solids)) + +for src,colors in SPECS.items(): + colorize(src,colors) diff --git a/hardware/stack/build_exact_footprints_from_native_baselines.py b/hardware/stack/build_exact_footprints_from_native_baselines.py new file mode 100644 index 0000000..4a0a1e5 --- /dev/null +++ b/hardware/stack/build_exact_footprints_from_native_baselines.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +from pathlib import Path +import re +L=Path('/home/ik/ChatGPT/Courant/hardware/panel/library/RadianPanel.pretty') + +def make(src,dst,newname,value,mpn,model,pad_size,drill,renum=None): + s=(L/(src+'.kicad_mod')).read_text() + s=s.replace(f'(footprint "{src}"',f'(footprint "{newname}"',1) + # First Value property only. + s=re.sub(r'\(property "Value" "[^"]*"',f'(property "Value" "{value}"',s,count=1) + s=re.sub(r'\(property "MPN" "[^"]*"',f'(property "MPN" "{mpn}"',s,count=1) + # Native generator footprints use circular/rect pads. Keep the proven pad + # centers and graphics; only use the selected component's hole/land sizes. + s=re.sub(r'\(size 1\.8 1\.8\) \(drill 1\)',f'(size {pad_size} {pad_size}) (drill {drill})',s) + if renum: + # Replace pad numbers by their relative X coordinate, avoiding swap collisions. + for old,new in renum.items(): + pat=rf'\(pad "{old}" ([^\n]*?)\(at ([^\n]*?)\)' + lines=[] + for line in s.splitlines(): + if line.lstrip().startswith('(pad "') or '(pad "' in line: + for old,new in renum.items(): + if f'(pad "{old}"' in line: + line=line.replace(f'(pad "{old}"',f'(pad "X{new}"',1);break + lines.append(line) + s='\n'.join(lines)+'\n' + for new in set(renum.values()): s=s.replace(f'(pad "X{new}"',f'(pad "{new}"') + model_block=f'\n(model "{model}" (offset (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)))\n' + i=s.rfind(')') + s=s[:i]+model_block+s[i:] + (L/(dst+'.kicad_mod')).write_text(s) + +make('IDC_2x05_P2.54_Shrouded','Wurth_61201021621_Exact_B','Wurth_61201021621_Exact_B', + '61201021621','61201021621','${KIPRJMOD}/../cad/models/Wurth_61201021621_native.step','1.65','1.1') +make('Header_1x02_P2.54','Molex_22-27-2021_J201_B','Molex_22-27-2021_J201_B', + '22-27-2021','22-27-2021','${KIPRJMOD}/../cad/models/Molex_22-27-2021_centered.step','1.6','1.1') +make('Header_1x02_P2.54','Molex_22-27-2021_J306_B','Molex_22-27-2021_J306_B', + '22-27-2021','22-27-2021','${KIPRJMOD}/../cad/models/Molex_22-27-2021_centered.step','1.6','1.1') +make('Header_1x06_P2.54','Molex_22-27-2061_J202_B','Molex_22-27-2061_J202_B', + '22-27-2061','22-27-2061','${KIPRJMOD}/../cad/models/Molex_22-27-2061_centered.step','1.6','1.1') +make('Header_1x03_P2.54','Wurth_450301014042_Exact_B','Wurth_450301014042_Exact_B', + '450301014042','450301014042','${KIPRJMOD}/../cad/models/Wurth_450301014042_native.step','1.3','.8', + {'1':'3','2':'1','3':'2'}) +print('exact library footprints rebuilt from native baseline families') diff --git a/hardware/stack/build_mainboard_exact_part_library.py b/hardware/stack/build_mainboard_exact_part_library.py new file mode 100644 index 0000000..67df458 --- /dev/null +++ b/hardware/stack/build_mainboard_exact_part_library.py @@ -0,0 +1,64 @@ +#!/usr/bin/env python3 +from pathlib import Path +import re +ROOT=Path('/home/ik/ChatGPT/Courant/hardware') +LIB=ROOT/'courant/deliverables/RadianMain.pretty' + +def strip_models(s): + out=[];i=0 + while i1e-4: clashes.append({'panel':pn,'main':mn,'mm3':round(v,6)}) +# Main non-stack components must also clear the panel PCB itself. +for mn,ms in M.items(): + if mn in {'stack','board'}: continue + v=ov(ms,P['board']) + if v>1e-4: clashes.append({'panel':'board','main':mn,'mm3':round(v,6)}) +# Panel non-stack components must clear the main PCB itself. +for pn,ps in P.items(): + if pn in {'stack','board'}: continue + v=ov(ps,M['board']) + if v>1e-4: clashes.append({'panel':pn,'main':'board','mm3':round(v,6)}) + +# Enclosure collision only against rear/dock solids; faceplate intersections +# with shafts/jack bushings are intentional and handled by existing case checks. +shell=cq.Assembly.importStep(str(CAD/'RADIAN_P1_case_shell_updated.step')) +case={} +for c in shell.children: + if c.name in {'rear_guard','desktop_dock'}: + case[c.name]=c.obj.moved(c.loc) +case_clashes=[] +for side,groups in [('panel',P),('main',M)]: + for gn,gs in groups.items(): + if gn in {'board'}: continue + for cn,cs in case.items(): + v=ov(gs,cs) + if v>1e-4: case_clashes.append({'side':side,'group':gn,'case':cn,'mm3':round(v,6)}) + +report={ + 'status':'PASS' if not clashes and not case_clashes else 'FAIL', + 'panel_main_unintended_clashes':clashes, + 'rear_guard_or_dock_clashes':case_clashes, + 'intentional_stack_overlap':'P_STACK <-> M_STACK excluded; validated by direct-stack-validation.json', +} +out=D/'actual_part_collision_report.json' +out.write_text(json.dumps(report,indent=2)+'\n') +print(json.dumps(report,indent=2)) +if report['status']!='PASS': raise SystemExit(2) diff --git a/hardware/stack/direct-stack-validation.json b/hardware/stack/direct-stack-validation.json new file mode 100644 index 0000000..bfa30f1 --- /dev/null +++ b/hardware/stack/direct-stack-validation.json @@ -0,0 +1,972 @@ +{ + "status": "PASS", + "sources": { + "stack_contract": "stack/panel-stack.json", + "panel_board": "panel/design/radian_panel.kicad_pcb", + "main_board": "courant/deliverables/courant.kicad_pcb", + "manufacturer_drawings": [ + "Samtec IPT1-1XX-XX-XX-D-XX Rev AA", + "Samtec IPS1-1XX-XX-XX-D-XX Rev S", + "Samtec IPX1 MATED DOCUMENT Rev C", + "Samtec IPT1 and IPS1 recommended through-hole PCB layouts" + ] + }, + "pairs": [ + { + "id": "A", + "main_ref": "J17", + "panel_ref": "J100", + "main_value": "IPT1-110-06-L-D", + "panel_value": "IPS1-110-01-L-D", + "main_side": "F", + "panel_side": "B", + "main_models": [ + "${KIPRJMOD}/../../stack/models/Samtec_IPT1-110-06-L-D_drawing_reference.step" + ], + "panel_models": [ + "${KIPRJMOD}/../../stack/models/Samtec_IPS1-110-01-L-D_drawing_reference.step" + ], + "pins": [ + { + "pin": 1, + "net": "GND", + "main_product_xy_mm": [ + 122.73, + 73.18 + ], + "panel_product_xy_mm": [ + 122.73, + 73.18 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 2, + "net": "VIN5", + "main_product_xy_mm": [ + 125.27, + 73.18 + ], + "panel_product_xy_mm": [ + 125.27, + 73.18 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 3, + "net": "VIN5", + "main_product_xy_mm": [ + 122.73, + 70.64 + ], + "panel_product_xy_mm": [ + 122.73, + 70.64 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 4, + "net": "VREF25", + "main_product_xy_mm": [ + 125.27, + 70.64 + ], + "panel_product_xy_mm": [ + 125.27, + 70.64 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 5, + "net": "GND", + "main_product_xy_mm": [ + 122.73, + 68.1 + ], + "panel_product_xy_mm": [ + 122.73, + 68.1 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 6, + "net": "POT_PITCH_RAW", + "main_product_xy_mm": [ + 125.27, + 68.1 + ], + "panel_product_xy_mm": [ + 125.27, + 68.1 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 7, + "net": "POT_DECAY_RAW", + "main_product_xy_mm": [ + 122.73, + 65.56 + ], + "panel_product_xy_mm": [ + 122.73, + 65.56 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 8, + "net": "POT_TIMBRE_RAW", + "main_product_xy_mm": [ + 125.27, + 65.56 + ], + "panel_product_xy_mm": [ + 125.27, + 65.56 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 9, + "net": "POT_DRIVE_RAW", + "main_product_xy_mm": [ + 122.73, + 63.02 + ], + "panel_product_xy_mm": [ + 122.73, + 63.02 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 10, + "net": "POT_DELAY_RAW", + "main_product_xy_mm": [ + 125.27, + 63.02 + ], + "panel_product_xy_mm": [ + 125.27, + 63.02 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 11, + "net": "POT_REVERB_RAW", + "main_product_xy_mm": [ + 122.73, + 60.48 + ], + "panel_product_xy_mm": [ + 122.73, + 60.48 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 12, + "net": "GND", + "main_product_xy_mm": [ + 125.27, + 60.48 + ], + "panel_product_xy_mm": [ + 125.27, + 60.48 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 13, + "net": "PITCH_IN", + "main_product_xy_mm": [ + 122.73, + 57.94 + ], + "panel_product_xy_mm": [ + 122.73, + 57.94 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 14, + "net": "MOD_IN", + "main_product_xy_mm": [ + 125.27, + 57.94 + ], + "panel_product_xy_mm": [ + 125.27, + 57.94 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 15, + "net": "GATE_IN", + "main_product_xy_mm": [ + 122.73, + 55.4 + ], + "panel_product_xy_mm": [ + 122.73, + 55.4 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 16, + "net": "GND", + "main_product_xy_mm": [ + 125.27, + 55.4 + ], + "panel_product_xy_mm": [ + 125.27, + 55.4 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 17, + "net": "LINE_L", + "main_product_xy_mm": [ + 122.73, + 52.86 + ], + "panel_product_xy_mm": [ + 122.73, + 52.86 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 18, + "net": "GND", + "main_product_xy_mm": [ + 125.27, + 52.86 + ], + "panel_product_xy_mm": [ + 125.27, + 52.86 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 19, + "net": "LINE_R", + "main_product_xy_mm": [ + 122.73, + 50.32 + ], + "panel_product_xy_mm": [ + 122.73, + 50.32 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 20, + "net": "GND", + "main_product_xy_mm": [ + 125.27, + 50.32 + ], + "panel_product_xy_mm": [ + 125.27, + 50.32 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + } + ], + "main_center_product_mm": [ + 124.0, + 61.75 + ], + "panel_center_product_mm": [ + 124.0, + 61.75 + ], + "contract_center_product_mm": [ + 124.0, + 61.75 + ], + "matched_pins": 20 + }, + { + "id": "B", + "main_ref": "J18", + "panel_ref": "J101", + "main_value": "IPT1-110-06-L-D", + "panel_value": "IPS1-110-01-L-D", + "main_side": "F", + "panel_side": "B", + "main_models": [ + "${KIPRJMOD}/../../stack/models/Samtec_IPT1-110-06-L-D_drawing_reference.step" + ], + "panel_models": [ + "${KIPRJMOD}/../../stack/models/Samtec_IPS1-110-01-L-D_drawing_reference.step" + ], + "pins": [ + { + "pin": 1, + "net": "GND", + "main_product_xy_mm": [ + 31.57, + 70.98 + ], + "panel_product_xy_mm": [ + 31.57, + 70.98 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 2, + "net": "V3V3", + "main_product_xy_mm": [ + 31.57, + 73.52 + ], + "panel_product_xy_mm": [ + 31.57, + 73.52 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 3, + "net": "GND", + "main_product_xy_mm": [ + 34.11, + 70.98 + ], + "panel_product_xy_mm": [ + 34.11, + 70.98 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 4, + "net": "ENC_A_RAW", + "main_product_xy_mm": [ + 34.11, + 73.52 + ], + "panel_product_xy_mm": [ + 34.11, + 73.52 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 5, + "net": "ENC_B_RAW", + "main_product_xy_mm": [ + 36.65, + 70.98 + ], + "panel_product_xy_mm": [ + 36.65, + 70.98 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 6, + "net": "ENC_SW_RAW", + "main_product_xy_mm": [ + 36.65, + 73.52 + ], + "panel_product_xy_mm": [ + 36.65, + 73.52 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 7, + "net": "cv_select", + "main_product_xy_mm": [ + 39.19, + 70.98 + ], + "panel_product_xy_mm": [ + 39.19, + 70.98 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 8, + "net": "LED0_A", + "main_product_xy_mm": [ + 39.19, + 73.52 + ], + "panel_product_xy_mm": [ + 39.19, + 73.52 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 9, + "net": "LED1_A", + "main_product_xy_mm": [ + 41.73, + 70.98 + ], + "panel_product_xy_mm": [ + 41.73, + 70.98 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 10, + "net": "LED2_A", + "main_product_xy_mm": [ + 41.73, + 73.52 + ], + "panel_product_xy_mm": [ + 41.73, + 73.52 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 11, + "net": "LED3_A", + "main_product_xy_mm": [ + 44.27, + 70.98 + ], + "panel_product_xy_mm": [ + 44.27, + 70.98 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 12, + "net": "GND", + "main_product_xy_mm": [ + 44.27, + 73.52 + ], + "panel_product_xy_mm": [ + 44.27, + 73.52 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 13, + "net": "MIDI4", + "main_product_xy_mm": [ + 46.81, + 70.98 + ], + "panel_product_xy_mm": [ + 46.81, + 70.98 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 14, + "net": "MIDI5", + "main_product_xy_mm": [ + 46.81, + 73.52 + ], + "panel_product_xy_mm": [ + 46.81, + 73.52 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 15, + "net": "PROGRAM_B", + "main_product_xy_mm": [ + 49.35, + 70.98 + ], + "panel_product_xy_mm": [ + 49.35, + 70.98 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 16, + "net": "reset_n", + "main_product_xy_mm": [ + 49.35, + 73.52 + ], + "panel_product_xy_mm": [ + 49.35, + 73.52 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 17, + "net": "JTAG_TCK", + "main_product_xy_mm": [ + 51.89, + 70.98 + ], + "panel_product_xy_mm": [ + 51.89, + 70.98 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 18, + "net": "JTAG_TDO", + "main_product_xy_mm": [ + 51.89, + 73.52 + ], + "panel_product_xy_mm": [ + 51.89, + 73.52 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 19, + "net": "JTAG_TDI", + "main_product_xy_mm": [ + 54.43, + 70.98 + ], + "panel_product_xy_mm": [ + 54.43, + 70.98 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + }, + { + "pin": 20, + "net": "JTAG_TMS", + "main_product_xy_mm": [ + 54.43, + 73.52 + ], + "panel_product_xy_mm": [ + 54.43, + 73.52 + ], + "xy_error_mm": 0.0, + "main_drill_mm": [ + 1.02, + 1.02 + ], + "panel_drill_mm": [ + 1.04, + 1.04 + ], + "net_match": true + } + ], + "main_center_product_mm": [ + 43.0, + 72.25 + ], + "panel_center_product_mm": [ + 43.0, + 72.25 + ], + "contract_center_product_mm": [ + 43.0, + 72.25 + ], + "matched_pins": 20 + } + ], + "mechanical": { + "fully_mated_gap_mm": 19.99, + "max_gap_mm": 20.45, + "fully_mated_wipe_mm": 0.84, + "min_wipe_at_max_gap_mm": 0.38, + "main_insulation_height_mm": 15.3, + "panel_height_mm": 8.51, + "nominal_geometric_insertion_mm": 3.82, + "geometric_insertion_at_max_gap_mm": 3.36, + "panel_tail_protrusion_past_opposite_face_mm": 0.94, + "main_tail_protrusion_past_opposite_face_mm": 0.75, + "panel_tail_to_faceplate_rear_clearance_mm": 7.06 + }, + "errors": [], + "total_contacts_checked": 40, + "total_contacts_matched": 40 +} diff --git a/hardware/stack/finalize_mainboard_exact_part_library.py b/hardware/stack/finalize_mainboard_exact_part_library.py new file mode 100644 index 0000000..fe939d9 --- /dev/null +++ b/hardware/stack/finalize_mainboard_exact_part_library.py @@ -0,0 +1,105 @@ +#!/usr/bin/env python3 +from pathlib import Path +import re,pcbnew + +ROOT=Path('/home/ik/ChatGPT/Courant/hardware') +DEL=ROOT/'courant/deliverables' +LIB=DEL/'RadianMain.pretty' +BOARD=DEL/'courant.kicad_pcb' +BACK=ROOT/'_backups/mainboard_exact_parts_20260918T042958Z/courant.kicad_pcb' +K='$'+'{KIPRJMOD}' + +def strip_models(s): + out=[];i=0 + while i{cut}') + kill=[]; cur=cut + while cur!=old_end: + kill.append(pedge[cur]);cur=prev[cur] + seen=set(); unique=[] + for t in kill: + u=str(t.m_Uuid) + if u not in seen: + seen.add(u); unique.append(t) + for t in unique:b.Remove(t) + print(net,'removed',len(unique),'tail segments') + +trim_path('JTAG_TMS',pcbnew.B_Cu,(124.65,99.5),(115.5,93.0)) +trim_path('JTAG_TDI',pcbnew.B_Cu,(127.19,99.5),(111.0,102.5)) +trim_path('JTAG_TCK',pcbnew.F_Cu,(132.27,99.5),(111.5,103.0)) +trim_path('JTAG_TDO',pcbnew.F_Cu,(129.73,99.5),(111.0,102.5)) +pcbnew.SaveBoard(P,b,True) +print('J202 relocated and JTAG tails trimmed') diff --git a/hardware/stack/remove_panel_dangles_once.py b/hardware/stack/remove_panel_dangles_once.py new file mode 100644 index 0000000..d303f39 --- /dev/null +++ b/hardware/stack/remove_panel_dangles_once.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +import json,re,sys,pcbnew +from pathlib import Path +ROOT=Path('/home/ik/ChatGPT/Courant/hardware') +BOARD=ROOT/'panel/design/radian_panel.kicad_pcb' +REPORT=ROOT/'panel/reports/native/production-parts-prune.json' +TARGET={'DESKTOP_12V','MIDI4','MIDI5','JTAG_TCK','JTAG_TDO','JTAG_TDI','JTAG_TMS','V3V3'} +d=json.loads(REPORT.read_text()) +items=[] +for v in d.get('violations',[]): + if v.get('type') not in {'track_dangling','via_dangling'}: continue + for item in v.get('items',[]): + desc=item.get('description','') + m=re.search(r'(?:Track|Via) \[([^\]]+)\]',desc) + net=m.group(1) if m else '' + items.append((item.get('uuid'),net,desc)) +foreign=[x for x in items if x[1] not in TARGET] +if foreign: + print('FOREIGN',foreign);sys.exit(2) +if not items: + print('NO_DANGLES');sys.exit(0) +b=pcbnew.LoadBoard(str(BOARD)); by={t.m_Uuid.AsString():t for t in b.GetTracks()} +missing=[];removed=[] +for uid,net,desc in items: + t=by.get(uid) + if t is None:missing.append(uid);continue + removed.append((uid,net));b.Remove(t) +if missing: + print('MISSING',missing);sys.exit(3) +pcbnew.SaveBoard(str(BOARD),b,True) +print('REMOVED',len(removed),removed) diff --git a/hardware/stack/render_actual_part_cad.py b/hardware/stack/render_actual_part_cad.py new file mode 100644 index 0000000..65affa0 --- /dev/null +++ b/hardware/stack/render_actual_part_cad.py @@ -0,0 +1,177 @@ +#!/usr/bin/env python3 +from pathlib import Path +import subprocess, sys, json +import cadquery as cq + +ROOT=Path('/home/ik/ChatGPT/Courant/hardware') +OUT=ROOT/'stack/actual_parts' +OUT.mkdir(parents=True,exist_ok=True) +PANEL=ROOT/'panel/design/radian_panel.kicad_pcb' +MAIN=ROOT/'courant/deliverables/courant.kicad_pcb' +CAD=ROOT/'panel/cad' +PRE=ROOT/'panel/previews' +sys.path.insert(0,str(ROOT/'panel/source')) +import build_cad as model + +PANEL_Z=-9.6 +MAIN_Z=-31.10 +def run(cmd): + subprocess.run(cmd,check=True) +def exp(board,name,refs=None,board_only=False): + out=OUT/(name+'.step') + cmd=['kicad-cli','pcb','export','step','-f','-o',str(out)] + if board_only: + # Mechanical board solid only. Component geometry comes from the native + # KiCad component-filter exports below; skipping copper keeps the final + # assembly light enough for interactive CAD/rendering. + cmd += ['--board-only'] + else: + cmd += ['--no-board-body','--component-filter',refs] + cmd += [str(board)] + run(cmd) + return out +def load(path): + return cq.importers.importStep(str(path)).val() +def ptx(s): return s.translate((0,128.5,PANEL_Z)) +def mtx(s): return s.translate((-12,164.25,MAIN_Z)) +def hx(c,default='#30362f'): + if c is None:return default + rgb=c.toTuple()[:3] + return '#'+''.join(f'{max(0,min(255,round(v*255))):02x}' for v in rgb) + +# KiCad-placed native exports. +panel_board=ptx(load(exp(PANEL,'panel_board',board_only=True))) +main_board=mtx(load(exp(MAIN,'main_board',board_only=True))) +panel_groups={ + 'P_POTS':('RV1,RV2,RV3,RV4,RV5,RV6','#252724'), + 'P_ENCODER':('ENC1','#242624'), + 'P_MODE':('SW1','#242624'), + 'P_JACKS':('J301,J302,J303,J304,J305','#202220'), + 'P_LEDS':('D10,D11,D12,D13','#55a84d'), + 'P_STACK':('J100,J101','#252724'), + 'P_WURTH':('J200,JP1','#252724'), + 'P_MOLEX':('J201,J202,J306','#ded6b7'), + 'P_BUTTONS':('SW3,SW4','#252724'), + 'P_ACTIVE':('U1,U2,D1,D2,D3,D4,L1,F1,F2','#252724'), + 'P_PASSIVES':('R*,C*','#9b8d6c'), +} +main_groups={ + 'M_STACK':('J17,J18','#252724'), + 'M_MOLEX':('J1,J2,J3,J4','#ded6b7'), + 'M_ICS':('U*,Y*','#252724'), + 'M_PASSIVES':('R*,C*','#9b8d6c'), + 'M_MAGNETICS':('L*','#353935'), + 'M_DIODES':('D*','#303330'), +} +items={} +# Existing enclosure shell, but remove all old native-PCB reference geometry. +shell=cq.Assembly.importStep(str(CAD/'RADIAN_P1_case_shell_updated.step')) +for c in shell.children: + if c.name.startswith('P1_NATIVE_'): continue + n=c.name + fallback='#2a2f2a' + if any(k in n.lower() for k in ['nut','screw','spacer','standoff','shim']): + fallback='#a4a59d' + elif 'knob' in n.lower(): + fallback='#252724' + elif any(k in n.lower() for k in ['marker','engraving','ink']): + fallback='#dddccd' + items['CASE_'+n]=(c.obj.moved(c.loc),hx(c.color,fallback)) + +items['PANEL_BOARD']=(panel_board,'#285d48') +items['MAIN_BOARD']=(main_board,'#285d48') + +for name,(refs,col) in panel_groups.items(): + s=ptx(load(exp(PANEL,name.lower(),refs=refs))) + items[name]=(s,col) +for name,(refs,col) in main_groups.items(): + s=mtx(load(exp(MAIN,name.lower(),refs=refs))) + items[name]=(s,col) + +def export_colored_solids(items,path,name): + # STEP color on a CadQuery compound does not survive a round trip; colors on + # child solids do. Export every physical solid as a named colored child. + assy=cq.Assembly(name=name) + nsolid=0 + for nm,(shape,hexcol) in items.items(): + rgb=tuple(int(hexcol.lstrip('#')[i:i+2],16)/255 for i in (0,2,4)) + col=cq.Color(*rgb) + solids=list(shape.Solids()) + if not solids: + assy.add(shape,name=nm,color=col) + nsolid+=1 + continue + for i,s in enumerate(solids): + assy.add(s,name=f'{nm}_{i:04d}',color=col) + nsolid+=1 + assy.export(str(path)) + # Round-trip audit: no viewer-default-white children are allowed. + check=cq.Assembly.importStep(str(path)) + missing=[c.name for c in check.children if c.color is None] + if missing: + raise RuntimeError(f'color persistence failed for {len(missing)} children: {missing[:20]}') + print('COLORED_STEP_PASS',path,nsolid,'solids') + return nsolid + +# Electrical geometry and direct-stack/case collision validation remain the +# canonical validators; component placement comes straight from native KiCad. +# Full product CAD and previews. +export_colored_solids(items,CAD/'RADIAN_actual_parts_full_assembly.step','RADIAN_ACTUAL_PARTS_FULL') +export_colored_solids(items,CAD/'RADIAN_P1_desktop_fit_study.step','RADIAN_ACTUAL_PARTS_FULL') +export_colored_solids(items,CAD/'RADIAN_P1_case_updated.step','RADIAN_ACTUAL_PARTS_FULL') +model.render(items,PRE/'actual_parts_full_iso.png',target=(101,64,-18),camera=(300,-220,130),scale=145) +model.render(items,PRE/'actual_parts_full_side.png',target=(101,64,-18),camera=(101,-285,-18),scale=125,up=(0,0,1)) + +# Dedicated populated-board CAD. These deliberately exclude the case and the +# opposite PCB so every fitted part can be inspected directly instead of being +# hidden by the product assembly. They use the exact same KiCad-native model +# placements as the full assembly above; only the view/export grouping differs. +panel_items={n:v for n,v in items.items() if n=='PANEL_BOARD' or n.startswith('P_')} +main_items={n:v for n,v in items.items() if n=='MAIN_BOARD' or n.startswith('M_')} +export_colored_solids(panel_items,CAD/'RADIAN_actual_parts_panel_board.step','RADIAN_ACTUAL_PARTS_PANEL_BOARD') +export_colored_solids(main_items,CAD/'RADIAN_actual_parts_main_board.step','RADIAN_ACTUAL_PARTS_MAIN_BOARD') +model.render(panel_items,PRE/'actual_parts_panel_board_top.png',target=(108,64,-1),camera=(280,-185,150),scale=92) +model.render(panel_items,PRE/'actual_parts_panel_board_bottom.png',target=(108,64,-10),camera=(275,-175,-125),scale=92,up=(0,0,1)) +model.render(main_items,PRE/'actual_parts_main_board_top.png',target=(88,64,-27),camera=(250,-170,105),scale=88) +model.render(main_items,PRE/'actual_parts_main_board_bottom.png',target=(88,64,-31),camera=(245,-165,-130),scale=88,up=(0,0,1)) + +# Board-stack-only proof uses the same actual KiCad component geometry. +stack_items={n:v for n,v in items.items() if n in {'PANEL_BOARD','MAIN_BOARD'} or n.startswith('P_') or n.startswith('M_')} +export_colored_solids(stack_items,CAD/'RADIAN_direct_stack_mated.step','RADIAN_DIRECT_STACK_ACTUAL_PARTS') +model.render(stack_items,PRE/'direct_stack_mated_iso.png',target=(101,64,-20),camera=(300,-210,120),scale=135) +model.render(stack_items,PRE/'direct_stack_mated_side.png',target=(101,64,-20),camera=(101,-260,-20),scale=120,up=(0,0,1)) +close={n:v for n,v in stack_items.items() if n in {'PANEL_BOARD','MAIN_BOARD','P_STACK','M_STACK'}} +model.render(close,PRE/'direct_stack_connectors_closeup.png',target=(84,67,-20),camera=(250,-180,35),scale=95) + +report={ + 'status':'PASS', + 'panel_native_board':str(PANEL), + 'main_native_board':str(MAIN), + 'dedicated_populated_board_cad':{ + 'panel':'panel/cad/RADIAN_actual_parts_panel_board.step', + 'main':'panel/cad/RADIAN_actual_parts_main_board.step', + }, + 'dedicated_populated_board_renders':[ + 'panel/previews/actual_parts_panel_board_top.png', + 'panel/previews/actual_parts_panel_board_bottom.png', + 'panel/previews/actual_parts_main_board_top.png', + 'panel/previews/actual_parts_main_board_bottom.png', + ], + 'panel_groups':{k:v[0] for k,v in panel_groups.items()}, + 'main_groups':{k:v[0] for k,v in main_groups.items()}, + 'collision_validation':'Use direct-stack-validation.json and case_direct_stack_update.json; this renderer preserves native KiCad placement.', + 'panel_transform':{'x':0,'y':128.5,'z':PANEL_Z}, + 'main_transform':{'x':-12,'y':164.25,'z':MAIN_Z}, + 'actual_or_package_models':[ + 'Bourns PTV09A family geometry aligned to PTV09A-4020F-B103 footprint/20 mm shaft', + 'QingPu/Thonk PJ398SM open mechanical CAD with knurled nut', + 'Omron B3F-1000 package geometry', + '3 mm green LED package geometry', + 'all selected Wurth/Molex/Samtec and mainboard package STEP models already attached in KiCad', + ], + 'drawing_derived_remaining':['ENC1 Bourns PEC11R-4220F-S0024','SW1 E-Switch 100SP1T1B1M2REH','Samtec J100/J101/J17/J18','Molex mainboard J1-J4'], + 'note':'No generic white component envelopes are used in this final assembly; component placement comes from KiCad STEP export.' +} +(OUT/'actual_parts_report.json').write_text(json.dumps(report,indent=2)+'\n') +print('ACTUAL_PART_CAD_PASS') +print(json.dumps(report,indent=2)) diff --git a/hardware/stack/render_actual_parts_full_assembly.py b/hardware/stack/render_actual_parts_full_assembly.py new file mode 100644 index 0000000..c8593e5 --- /dev/null +++ b/hardware/stack/render_actual_parts_full_assembly.py @@ -0,0 +1,12 @@ +#!/usr/bin/env python3 +"""Compatibility entry point for the final actual-part assembly views. + +The old implementation rebuilt the full assembly from stale *-raw.step groups, +which could reintroduce old U8 geometry and default-white compound colors. +The canonical CAD is now built by render_actual_part_cad.py and this entry point +renders that color-persistent STEP directly. +""" +from pathlib import Path +import runpy +HERE=Path(__file__).resolve().parent +runpy.run_path(str(HERE/'render_final_actual_assembly_views.py'),run_name='__main__') diff --git a/hardware/stack/render_actual_parts_stack.py b/hardware/stack/render_actual_parts_stack.py new file mode 100644 index 0000000..94c239b --- /dev/null +++ b/hardware/stack/render_actual_parts_stack.py @@ -0,0 +1,148 @@ +#!/usr/bin/env python3 +from pathlib import Path +import json +import cadquery as cq +from OCP.Bnd import Bnd_Box +from OCP.BRepBndLib import BRepBndLib + +ROOT=Path('/home/ik/ChatGPT/Courant/hardware') +D=ROOT/'stack/actual_parts' +OUT_CAD=ROOT/'panel/cad' +OUT_PRE=ROOT/'panel/previews' + +# Raw KiCad STEP uses x=native-x, y=-native-y, board B-face z=0. +# Product transforms are derived from the native board contracts. +PANEL_T=(0.0,128.5,-9.6) # panel B PCB face = -9.60 mm +MAIN_T=(-12.0,164.25,-31.10) # main F PCB face = -29.59 mm (raw top=1.51) +TARGET_GAP=19.99 + +groups=[ + ('panel_board','panel-board-raw.step',PANEL_T,'#285C45'), + ('panel_pots','panel-pots-raw.step',PANEL_T,'#313531'), + ('panel_encoder','panel-encoder-raw.step',PANEL_T,'#444744'), + ('panel_mode','panel-mode-raw.step',PANEL_T,'#323432'), + ('panel_jacks','panel-jacks-only-raw.step',PANEL_T,'#202321'), + ('panel_leds','panel-leds-only-raw.step',PANEL_T,'#49A65B'), + ('panel_samtec','panel-samtec-raw.step',PANEL_T,'#181A19'), + ('panel_wurth','panel-wurth-raw.step',PANEL_T,'#252826'), + ('panel_molex','panel-molex-raw.step',PANEL_T,'#E6E1CF'), + ('panel_buttons','panel-buttons-raw.step',PANEL_T,'#252525'), + ('panel_ics','panel-ics-raw.step',PANEL_T,'#222422'), + ('panel_resistors','panel-resistors-raw.step',PANEL_T,'#B6A47E'), + ('panel_capacitors','panel-capacitors-raw.step',PANEL_T,'#A9825B'), + ('panel_power_discretes','panel-power-discretes-raw.step',PANEL_T,'#4A4741'), + + ('main_board','main-board-raw.step',MAIN_T,'#20573F'), + ('main_ics','main-ics-only-raw.step',MAIN_T,'#222422'), + ('main_service_connectors','main-service-connectors-raw.step',MAIN_T,'#E6E1CF'), + ('main_samtec','main-samtec-raw.step',MAIN_T,'#181A19'), + ('main_resistors','main-resistors-raw.step',MAIN_T,'#B6A47E'), + ('main_capacitors','main-capacitors-raw.step',MAIN_T,'#A9825B'), + ('main_diodes','main-diodes-raw.step',MAIN_T,'#252525'), + ('main_inductors','main-inductors-raw.step',MAIN_T,'#474A47'), + ('main_oscillators','main-oscillators-raw.step',MAIN_T,'#BFC4C5'), +] + +def bbox(shape): + b=shape.BoundingBox() + return [b.xmin,b.ymin,b.zmin,b.xmax,b.ymax,b.zmax] + +def load(): + out={} + for name,fn,t,col in groups: + p=D/fn + if not p.exists(): raise RuntimeError(f'missing {p}') + s=cq.importers.importStep(str(p)).val().translate(t) + out[name]=(s,col) + return out + +def export(items,path): + assy=cq.Assembly(name='RADIAN_ACTUAL_PARTS_STACK') + for name,(shape,c) in items.items(): + rgb=tuple(int(c.lstrip('#')[i:i+2],16)/255 for i in (0,2,4)) + assy.add(shape,name=name,color=cq.Color(*rgb)) + assy.export(str(path)) + +def render(items,path,camera,target=(105,64,-13),scale=100,up=(0,0,1)): + import vtk + rr=vtk.vtkRenderer();rr.SetBackground(.92,.92,.90);rr.SetUseFXAA(True) + win=vtk.vtkRenderWindow();win.SetOffScreenRendering(1);win.SetSize(1800,1250);win.SetMultiSamples(0);win.AddRenderer(rr) + for name,(s,c) in items.items(): + mapper=vtk.vtkPolyDataMapper();mapper.SetInputData(s.toVtkPolyData(.04,.15,True));mapper.ScalarVisibilityOff() + a=vtk.vtkActor();a.SetMapper(mapper) + rgb=tuple(int(c.lstrip('#')[i:i+2],16)/255 for i in (0,2,4)) + p=a.GetProperty();p.SetColor(*rgb);p.SetAmbient(.22);p.SetDiffuse(.72);p.SetSpecular(.28);p.SetSpecularPower(35) + rr.AddActor(a) + rr.AutomaticLightCreationOff() + for xyz,power in [((-120,240,330),.95),((350,-210,210),.70),((80,40,-220),.35)]: + l=vtk.vtkLight();l.SetLightTypeToSceneLight();l.SetPosition(*xyz);l.SetFocalPoint(*target);l.SetIntensity(power);rr.AddLight(l) + cam=rr.GetActiveCamera();cam.SetPosition(*camera);cam.SetFocalPoint(*target);cam.SetViewUp(*up);cam.ParallelProjectionOn();cam.SetParallelScale(scale) + rr.ResetCameraClippingRange();win.Render() + im=vtk.vtkWindowToImageFilter();im.SetInput(win);im.SetInputBufferTypeToRGB();im.ReadFrontBufferOff();im.Update() + w=vtk.vtkPNGWriter();w.SetFileName(str(path));w.SetInputConnection(im.GetOutputPort());w.Write();win.Finalize() + +items=load() +export(items,OUT_CAD/'RADIAN_actual_parts_stack.step') +render(items,OUT_PRE/'actual_parts_stack_iso.png',(300,-205,205),scale=104) +render(items,OUT_PRE/'actual_parts_stack_side.png',(310,64,-12),scale=92,up=(0,0,1)) +render(items,OUT_PRE/'actual_parts_panel_closeup.png',(260,-125,155),target=(108,65,-2),scale=78) + +pb=bbox(items['panel_board'][0]); mb=bbox(items['main_board'][0]) + +# OCC expands transformed STEP bounding boxes by representation tolerances. +# The physical PCB-face gap must therefore use the *raw* KiCad board faces and +# the exact product transforms rather than transformed OCC bounding boxes. +raw_pb=cq.importers.importStep(str(D/'panel-board-raw.step')).val().BoundingBox() +raw_mb=cq.importers.importStep(str(D/'main-board-raw.step')).val().BoundingBox() +panel_back_face=PANEL_T[2]+raw_pb.zmin +main_front_face=MAIN_T[2]+raw_mb.zmax +gap=panel_back_face-main_front_face + +# Detailed boolean collision validation is kept in a separate, lightweight +# validator so the renderer does not duplicate a high-memory OCC workload. +collision_path=ROOT/'stack/actual-parts-collision-validation.json' +if not collision_path.exists(): + raise RuntimeError('run validate_actual_parts_collisions.py before rendering') +collision=json.loads(collision_path.read_text()) +enclosure_clashes=collision['actual_components_vs_physical_enclosure_clashes'] +panel_main_clashes=collision['non_samtec_panel_vs_main_clashes'] +panel_main_overlap=collision['non_samtec_panel_vs_main_overlap_mm3'] + +status='PASS' if ( + collision['status']=='PASS' and + abs(gap-TARGET_GAP)<0.001 and + not enclosure_clashes and + not panel_main_clashes +) else 'FAIL' + +report={ + 'status':status, + 'assembly':'panel/cad/RADIAN_actual_parts_stack.step', + 'panel_board_occ_bbox_mm':[round(x,4) for x in pb], + 'main_board_occ_bbox_mm':[round(x,4) for x in mb], + 'physical_faces':{ + 'panel_back_face_z_mm':round(panel_back_face,4), + 'main_front_face_z_mm':round(main_front_face,4), + 'pcb_face_gap_mm':round(gap,4), + 'target_gap_mm':TARGET_GAP, + 'method':'raw KiCad STEP board faces + exact product transforms; transformed OCC bounding boxes are not used for face spacing' + }, + 'actual_part_collision_validation':{ + 'component_vs_physical_enclosure_clashes':enclosure_clashes, + 'non_samtec_panel_vs_main_clashes':panel_main_clashes, + 'non_samtec_panel_vs_main_overlap_mm3':round(panel_main_overlap,7) + }, + 'group_bboxes_mm':{n:[round(x,3) for x in bbox(s)] for n,(s,_) in items.items()}, + 'model_policy':{ + 'native_placement':'all component geometry is exported component-filtered by KiCad from the canonical .kicad_pcb files, so PCB placement/orientation is native', + 'real_open_models':['panel RV1-RV6 PTV09A family body with selected 20 mm shaft','panel J301-J305 PJ398SM open mechanical CAD','panel SW3/SW4 Omron B3F model'], + 'package_accurate_models':['LED 3 mm green package','TPS54302 SOT-23-6','OPA2192 SOIC-8','BAT54S SOT-23','standard passives/fuses/SMB packages','mainboard IC/passive package models'], + 'drawing_reference_models':['Samtec J17/J18/J100/J101','Molex J1-J4','panel PEC11R encoder','panel E-Switch MODE','panel SRP7050TA inductor'], + 'not_claimed_as_vendor_step':'drawing-reference models above remain explicit mechanical references, not manufacturer STEP downloads' + } +} +(ROOT/'stack/actual-parts-render-validation.json').write_text(json.dumps(report,indent=2)+'\n') +print(json.dumps(report,indent=2)) +if status!='PASS': + raise SystemExit('ACTUAL_PARTS_STACK_VALIDATION_FAILED') +print('ACTUAL_PARTS_STACK_RENDER_PASS') diff --git a/hardware/stack/render_direct_stack.py b/hardware/stack/render_direct_stack.py new file mode 100755 index 0000000..7bef24e --- /dev/null +++ b/hardware/stack/render_direct_stack.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +from pathlib import Path +import sys, re +import cadquery as cq + +ROOT=Path('/home/ik/ChatGPT/Courant/hardware') +sys.path.insert(0,str(ROOT/'panel/source')) +import build_cad as model + +src=ROOT/'panel/cad/RADIAN_P1_desktop_fit_study.step' +a=cq.Assembly.importStep(str(src)) + +def color_hex(c, default='#30362F'): + if c is None:return default + rgb=c.toTuple()[:3] + return '#'+''.join(f'{max(0,min(255,round(v*255))):02x}' for v in rgb) + +# Keep the two real board assemblies, the exact Samtec mating pair, and all +# current panel electrical/mechanical parts including their generic lead/pin +# envelopes. Strip the faceplate/case so the inter-board gap is visible. +items={} +for c in a.children: + n=c.name + keep = ( + n in {'P1_BOARD','MAINBOARD_REPAIRED','J17_IPT1_REFERENCE','J18_IPT1_REFERENCE'} + or re.match(r'^(?:J100|J101|RV[1-6]|ENC1|SW1|D1[0-3]|J30[1-6]|J20[0-2]|F[12]|D[1-4]|U[12]|L1|C(?:[1-7]|20|21)|R(?:[1-5]|20|21|22|23|24)|JP1|SW[34])_(?:body|pins|shaft|bushing)$',n) + ) + if keep: + shape=c.obj.moved(c.loc) + col=color_hex(c.color) + # Make the mating connectors easier to distinguish in the proof views. + if n in {'J100_body','J101_body'}: col='#356fa8' + elif n in {'J17_IPT1_REFERENCE','J18_IPT1_REFERENCE'}: col='#b08a32' + items[n]=(shape,col) + +outdir=ROOT/'panel/previews' +outdir.mkdir(exist_ok=True) +model.export_assy(items,ROOT/'panel/cad/RADIAN_direct_stack_mated.step','RADIAN_DIRECT_STACK_MATED') +model.render(items,outdir/'direct_stack_mated_iso.png',target=(101,64,-20),camera=(300,-210,120),scale=135) +model.render(items,outdir/'direct_stack_mated_side.png',target=(101,64,-20),camera=(101,-260,-20),scale=120,up=(0,0,1)) + +# Connector-only close-up so all four mating connector bodies are unobscured. +close={} +for n in ['P1_BOARD','MAINBOARD_REPAIRED','J100_body','J101_body','J100_pins','J101_pins','J17_IPT1_REFERENCE','J18_IPT1_REFERENCE']: + if n in items: close[n]=items[n] +model.render(close,outdir/'direct_stack_connectors_closeup.png',target=(84,67,-20),camera=(250,-180,35),scale=95) +print('STACK_RENDER_PASS',len(items),'items') +print(outdir/'direct_stack_mated_iso.png') +print(outdir/'direct_stack_mated_side.png') +print(outdir/'direct_stack_connectors_closeup.png') diff --git a/hardware/stack/render_direct_stack_fit.py b/hardware/stack/render_direct_stack_fit.py new file mode 100755 index 0000000..37e0ae4 --- /dev/null +++ b/hardware/stack/render_direct_stack_fit.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +from pathlib import Path +import json, sys +import cadquery as cq + +ROOT=Path(__file__).resolve().parents[1] +STACK=json.loads((ROOT/'stack/panel-stack.json').read_text()) +sys.path.insert(0,str(ROOT/'panel/source')) +import build_cad as panelcad + +MODELS=ROOT/'stack/models' +IPT=cq.importers.importStep(str(MODELS/'Samtec_IPT1-110-06-L-D_drawing_reference.step')).val() +IPS=cq.importers.importStep(str(MODELS/'Samtec_IPS1-110-01-L-D_drawing_reference.step')).val() +GAP=STACK['mating']['fully_mated_gap_mm'] + +# Simplified main PCB slab using the current mainboard product-space bounds. +mainpcb=cq.Workplane('XY').box(160,100,1.6,centered=(False,False,False)).translate((8,14.25,-1.6)).val() +# Actual panel PCB outline from current panel CAD, shifted so its B-side is at z=GAP. +panelpcb=panelcad.board_shape().translate((0,0,GAP+9.6)) + +items={'MAIN_PCB':(mainpcb,'#2E5745'),'PANEL_PCB':(panelpcb,'#265944')} +for con in STACK['connectors']: + x=con['panel_xy_mm']['x']; y=con['panel_xy_mm']['y']; a=con['rotation_deg'] + male=IPT.rotate((0,0,0),(0,0,1),a).translate((x,y,0)) + # Panel connector is B-side: flip about Y then rotate like the footprint. + female=IPS.rotate((0,0,0),(0,1,0),180).rotate((0,0,0),(0,0,1),a).translate((x,y,GAP)) + items[f"{con['main_ref']}_IPT1"]=(male,'#242424') + items[f"{con['panel_ref']}_IPS1"]=(female,'#242424') + +out=ROOT/'stack/direct_stack_fit_both.png' +panelcad.render(items,out,target=(95,67,10),camera=(290,-175,115),scale=105) +panelcad.export_assy(items,ROOT/'stack/direct_stack_fit_both.step','RADIAN_DIRECT_STACK_EXACT_REFERENCE') + +# Pair-A close-up, clipped down to a local board sample for readable mating detail. +con=STACK['connectors'][0]; x=con['panel_xy_mm']['x']; y=con['panel_xy_mm']['y']; a=con['rotation_deg'] +main_sample=cq.Workplane('XY').box(28,38,1.6,centered=(True,True,False)).val().translate((x,y,-1.6)) +panel_sample=cq.Workplane('XY').box(28,38,1.6,centered=(True,True,False)).val().translate((x,y,GAP)) +male=IPT.rotate((0,0,0),(0,0,1),a).translate((x,y,0)) +female=IPS.rotate((0,0,0),(0,1,0),180).rotate((0,0,0),(0,0,1),a).translate((x,y,GAP)) +close={'MAIN_PCB':(main_sample,'#2E5745'),'PANEL_PCB':(panel_sample,'#265944'),'J17_IPT1':(male,'#242424'),'J100_IPS1':(female,'#242424')} +out2=ROOT/'stack/direct_stack_fit_pair_A.png' +panelcad.render(close,out2,target=(x,y,GAP/2),camera=(x+70,y-80,55),scale=32) +panelcad.export_assy(close,ROOT/'stack/direct_stack_fit_pair_A.step','RADIAN_DIRECT_STACK_PAIR_A') +print(out) +print(out2) diff --git a/hardware/stack/render_final_actual_assembly_views.py b/hardware/stack/render_final_actual_assembly_views.py new file mode 100644 index 0000000..d25e8ee --- /dev/null +++ b/hardware/stack/render_final_actual_assembly_views.py @@ -0,0 +1,41 @@ +#!/usr/bin/env python3 +from pathlib import Path +import cadquery as cq +import vtk + +ROOT=Path('/home/ik/ChatGPT/Courant/hardware') +STEP=ROOT/'panel/cad/RADIAN_actual_parts_full_assembly.step' +OUT=ROOT/'panel/previews' +OUT.mkdir(parents=True,exist_ok=True) + +assy=cq.Assembly.importStep(str(STEP)) +children=[] +for c in assy.children: + shape=c.obj.moved(c.loc) + color=c.color.toTuple()[:3] if c.color else (0.2,0.2,0.2) + children.append((c.name,shape,color)) + +def render(path,camera,target=(104,64,-12),scale=108,case_opacity=.18): + rr=vtk.vtkRenderer(); rr.SetBackground(.94,.94,.925); rr.SetUseFXAA(True) + win=vtk.vtkRenderWindow(); win.SetOffScreenRendering(1); win.SetSize(1800,1250); win.SetMultiSamples(0); win.AddRenderer(rr) + for name,shape,rgb in children: + mapper=vtk.vtkPolyDataMapper(); mapper.SetInputData(shape.toVtkPolyData(.04,.15,True)); mapper.ScalarVisibilityOff() + actor=vtk.vtkActor(); actor.SetMapper(mapper) + p=actor.GetProperty(); p.SetColor(*rgb) + p.SetOpacity(case_opacity if name.startswith('CASE_') else 1.0) + p.SetAmbient(.22); p.SetDiffuse(.72); p.SetSpecular(.25); p.SetSpecularPower(35) + rr.AddActor(actor) + rr.AutomaticLightCreationOff() + for xyz,power in [((-120,240,340),.95),((350,-210,220),.72),((80,40,-220),.35)]: + l=vtk.vtkLight(); l.SetLightTypeToSceneLight(); l.SetPosition(*xyz); l.SetFocalPoint(*target); l.SetIntensity(power); rr.AddLight(l) + cam=rr.GetActiveCamera(); cam.SetPosition(*camera); cam.SetFocalPoint(*target); cam.SetViewUp(0,0,1) + cam.ParallelProjectionOn(); cam.SetParallelScale(scale) + rr.ResetCameraClippingRange(); win.SetAlphaBitPlanes(1); win.Render() + im=vtk.vtkWindowToImageFilter(); im.SetInput(win); im.SetInputBufferTypeToRGB(); im.ReadFrontBufferOff(); im.Update() + w=vtk.vtkPNGWriter(); w.SetFileName(str(path)); w.SetInputConnection(im.GetOutputPort()); w.Write(); win.Finalize() + print(path) + +render(OUT/'actual_parts_full_assembly_iso.png',(305,-205,210),scale=110,case_opacity=.18) +render(OUT/'actual_parts_full_assembly_side.png',(315,64,-10),scale=94,case_opacity=.15) +render(OUT/'actual_parts_full_assembly_front.png',(104,-260,65),target=(104,64,-4),scale=82,case_opacity=.22) +print('FINAL_ACTUAL_ASSEMBLY_VIEWS_PASS',len(children),'colored solids') diff --git a/hardware/stack/render_hq_actual_views.py b/hardware/stack/render_hq_actual_views.py new file mode 100644 index 0000000..7b6e0f7 --- /dev/null +++ b/hardware/stack/render_hq_actual_views.py @@ -0,0 +1,81 @@ +#!/usr/bin/env python3 +from pathlib import Path +import cadquery as cq +import vtk + +ROOT=Path('/home/ik/ChatGPT/Courant/hardware') +OUT=ROOT/'panel/previews/hq' +OUT.mkdir(parents=True,exist_ok=True) + +def load_step(path): + assy=cq.Assembly.importStep(str(path)) + out=[] + for c in assy.children: + shape=c.obj.moved(c.loc) + rgb=c.color.toTuple()[:3] if c.color else (0.2,0.2,0.2) + out.append((c.name,shape,rgb)) + return out + +def render(children,path,camera,target,scale,case_opacity=1.0): + rr=vtk.vtkRenderer() + rr.SetBackground(.94,.94,.925) + rr.SetUseFXAA(True) + win=vtk.vtkRenderWindow() + win.SetOffScreenRendering(1) + win.SetSize(3840,2160) + win.SetMultiSamples(0) + win.AddRenderer(rr) + for name,shape,rgb in children: + mapper=vtk.vtkPolyDataMapper() + mapper.SetInputData(shape.toVtkPolyData(.025,.10,True)) + mapper.ScalarVisibilityOff() + actor=vtk.vtkActor() + actor.SetMapper(mapper) + prop=actor.GetProperty() + prop.SetColor(*rgb) + prop.SetOpacity(case_opacity if name.startswith('CASE_') else 1.0) + prop.SetAmbient(.20) + prop.SetDiffuse(.74) + prop.SetSpecular(.28) + prop.SetSpecularPower(42) + rr.AddActor(actor) + rr.AutomaticLightCreationOff() + for xyz,power in [((-160,260,380),1.0),((390,-240,250),.72),((70,30,-260),.32)]: + light=vtk.vtkLight() + light.SetLightTypeToSceneLight() + light.SetPosition(*xyz) + light.SetFocalPoint(*target) + light.SetIntensity(power) + rr.AddLight(light) + cam=rr.GetActiveCamera() + cam.SetPosition(*camera) + cam.SetFocalPoint(*target) + cam.SetViewUp(0,0,1) + cam.ParallelProjectionOn() + cam.SetParallelScale(scale) + rr.ResetCameraClippingRange() + win.Render() + im=vtk.vtkWindowToImageFilter() + im.SetInput(win) + im.SetInputBufferTypeToRGB() + im.ReadFrontBufferOff() + im.Update() + writer=vtk.vtkPNGWriter() + writer.SetFileName(str(path)) + writer.SetInputConnection(im.GetOutputPort()) + writer.Write() + win.Finalize() + print(path) + +panel=load_step(ROOT/'panel/cad/RADIAN_actual_parts_panel_board.step') +main=load_step(ROOT/'panel/cad/RADIAN_actual_parts_main_board.step') +full=load_step(ROOT/'panel/cad/RADIAN_actual_parts_full_assembly.step') + +render(main,OUT/'01_mainboard_top_4k.png',(250,-170,105),(88,64,-27),88) +render(main,OUT/'02_mainboard_bottom_4k.png',(245,-165,-130),(88,64,-31),88) +render(panel,OUT/'03_panel_top_4k.png',(280,-185,150),(108,64,-1),92) +render(panel,OUT/'04_panel_bottom_4k.png',(275,-175,-125),(108,64,-10),92) +render(full,OUT/'05_full_assembly_iso_4k.png',(305,-205,210),(104,64,-12),110,.18) +render(full,OUT/'06_full_assembly_front_4k.png',(104,-260,65),(104,64,-4),82,.22) +render(full,OUT/'07_full_assembly_side_4k.png',(315,64,-10),(104,64,-12),94,.15) +print('HQ_4K_RENDERS_PASS') diff --git a/hardware/stack/render_presentation_board_views.py b/hardware/stack/render_presentation_board_views.py new file mode 100644 index 0000000..f9ede37 --- /dev/null +++ b/hardware/stack/render_presentation_board_views.py @@ -0,0 +1,77 @@ +#!/usr/bin/env python3 +from pathlib import Path +import cadquery as cq +import vtk +from PIL import Image + +ROOT=Path('/home/ik/ChatGPT/Courant') +CAD=ROOT/'hardware/panel/cad' +OUT=ROOT/'RADIAN_PCBs_and_case' +TMP=ROOT/'hardware/panel/previews/presentation_tmp' +TMP.mkdir(parents=True,exist_ok=True) + +TOP=(203/255,203/255,228/255) +BOTTOM=(103/255,103/255,128/255) + +def load_step(path): + assy=cq.Assembly.importStep(str(path)) + out=[] + for c in assy.children: + out.append((c.name,c.obj.moved(c.loc),c.color.toTuple()[:3] if c.color else (.2,.2,.2))) + return out + +def render(children,path,camera,target,parallel_scale): + rr=vtk.vtkRenderer() + rr.GradientBackgroundOn() + rr.SetBackground(*BOTTOM) + rr.SetBackground2(*TOP) + rr.SetUseFXAA(True) + win=vtk.vtkRenderWindow() + win.SetOffScreenRendering(1) + win.SetSize(3536,2464) + win.SetMultiSamples(0) + win.AddRenderer(rr) + for name,shape,rgb in children: + mapper=vtk.vtkPolyDataMapper() + mapper.SetInputData(shape.toVtkPolyData(.018,.08,True)) + mapper.ScalarVisibilityOff() + actor=vtk.vtkActor() + actor.SetMapper(mapper) + prop=actor.GetProperty() + prop.SetColor(*rgb) + prop.SetAmbient(.18) + prop.SetDiffuse(.72) + if any(k in name for k in ('MOLEX','OSC','WURTH','STACK')): + prop.SetSpecular(.42); prop.SetSpecularPower(52) + elif 'BOARD' in name: + prop.SetSpecular(.12); prop.SetSpecularPower(18) + else: + prop.SetSpecular(.25); prop.SetSpecularPower(34) + rr.AddActor(actor) + rr.AutomaticLightCreationOff() + for xyz,power in [((-160,250,340),1.0),((320,-220,210),.75),((70,50,-180),.30)]: + light=vtk.vtkLight() + light.SetLightTypeToSceneLight() + light.SetPosition(*xyz); light.SetFocalPoint(*target); light.SetIntensity(power) + rr.AddLight(light) + cam=rr.GetActiveCamera() + cam.SetPosition(*camera); cam.SetFocalPoint(*target); cam.SetViewUp(0,0,1) + cam.ParallelProjectionOn(); cam.SetParallelScale(parallel_scale) + rr.ResetCameraClippingRange(); win.Render() + cap=vtk.vtkWindowToImageFilter() + cap.SetInput(win); cap.SetInputBufferTypeToRGB(); cap.ReadFrontBufferOff(); cap.Update() + writer=vtk.vtkPNGWriter() + writer.SetFileName(str(path)); writer.SetInputConnection(cap.GetOutputPort()); writer.Write() + win.Finalize() + + im=Image.open(path).convert('RGB') + im=im.resize((1768,1232),Image.Resampling.LANCZOS) + im.save(path,optimize=True) + +main=load_step(CAD/'RADIAN_actual_parts_main_board.step') +panel=load_step(CAD/'RADIAN_actual_parts_panel_board.step') +render(main,OUT/'01_mainboard_KiCad_actual_parts_U8_aligned.png', + (250,-170,105),(88,64,-27),88) +render(panel,OUT/'02_panel_KiCad_actual_parts.png', + (280,-185,150),(108,64,-1),92) +print('PRESENTATION_BOARD_RENDERS_PASS') diff --git a/hardware/stack/route_j202_local.py b/hardware/stack/route_j202_local.py new file mode 100644 index 0000000..520d0b1 --- /dev/null +++ b/hardware/stack/route_j202_local.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +import pcbnew +P='/home/ik/ChatGPT/Courant/hardware/panel/design/radian_panel.kicad_pcb' +b=pcbnew.LoadBoard(P) +def mm(x): return pcbnew.FromMM(x) +def pt(x,y): return pcbnew.VECTOR2I(mm(x),mm(y)) +def tr(net,layer,pts,w=.25): + n=b.FindNet(net) + for a,c in zip(pts,pts[1:]): + t=pcbnew.PCB_TRACK(b);t.SetNet(n);t.SetLayer(layer);t.SetWidth(mm(w)) + t.SetStart(pt(*a));t.SetEnd(pt(*c));b.Add(t) +def via(net,x,y,w=.65,d=.30): + v=pcbnew.PCB_VIA(b);v.SetNet(b.FindNet(net));v.SetPosition(pt(x,y)) + v.SetWidth(mm(w));v.SetDrill(mm(d));v.SetLayerPair(pcbnew.F_Cu,pcbnew.B_Cu);b.Add(v) + +tr('JTAG_TMS',pcbnew.B_Cu,[(106.27,97.365),(108.0,96.0),(111.0,94.0),(115.5,93.0)]) +tr('JTAG_TDI',pcbnew.B_Cu,[(105.0,98.635),(105.0,100.5),(108.0,102.0),(111.0,102.5)]) + +tr('GND',pcbnew.B_Cu,[(103.73,98.635),(103.5,100.0),(100.0,101.5),(96.0,101.5)]) +via('GND',96.0,101.5,.70,.30) + +# V3V3 goes around the left end of the parallel PROGRAM_B/JTAG lanes: +# rise to F.Cu on the right, cross below those lanes at y=106, then +# return to the existing B.Cu V3V3 trunk at x=59.5,y=105. +tr('V3V3',pcbnew.B_Cu,[(106.27,98.635),(110.0,99.0),(113.5,99.0)]) +via('V3V3',113.5,99.0) +tr('V3V3',pcbnew.F_Cu,[(113.5,99.0),(113.5,106.0),(58.5,106.0)]) +via('V3V3',58.5,106.0) +tr('V3V3',pcbnew.B_Cu,[(58.5,106.0),(59.5,105.0)]) + +tr('JTAG_TCK',pcbnew.B_Cu,[(105.0,97.365),(105.0,94.0)]) +via('JTAG_TCK',105.0,94.0) +tr('JTAG_TCK',pcbnew.F_Cu,[(105.0,94.0),(109.0,94.0),(113.0,98.0),(113.0,101.0),(111.5,103.0)]) + +tr('JTAG_TDO',pcbnew.B_Cu,[(103.73,97.365),(103.73,94.5),(100.0,94.5)]) +via('JTAG_TDO',100.0,94.5) +tr('JTAG_TDO',pcbnew.F_Cu,[(100.0,94.5),(92.0,94.5),(92.0,102.5),(111.0,102.5)]) + +pcbnew.SaveBoard(P,b,True) +print('J202 local routes added v4') diff --git a/hardware/stack/trim_one_jtag.py b/hardware/stack/trim_one_jtag.py new file mode 100644 index 0000000..d49fe15 --- /dev/null +++ b/hardware/stack/trim_one_jtag.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +import sys, pcbnew +from collections import defaultdict, deque +P='/home/ik/ChatGPT/Courant/hardware/panel/design/radian_panel.kicad_pcb' +net=sys.argv[1]; layer=pcbnew.B_Cu if sys.argv[2]=='B' else pcbnew.F_Cu +old=(float(sys.argv[3]),float(sys.argv[4])); cut=(float(sys.argv[5]),float(sys.argv[6])) +b=pcbnew.LoadBoard(P) +def key(p):return (round(pcbnew.ToMM(p.x),3),round(pcbnew.ToMM(p.y),3)) +tracks=[t for t in b.GetTracks() if not isinstance(t,pcbnew.PCB_VIA) and t.GetNetname()==net and t.GetLayer()==layer] +adj=defaultdict(list) +for t in tracks: + a=key(t.GetStart());c=key(t.GetEnd());adj[a].append((c,t));adj[c].append((a,t)) +q=deque([old]);prev={old:None};pedge={} +while q: + u=q.popleft() + if u==cut:break + for v,t in adj[u]: + if v not in prev:prev[v]=u;pedge[v]=t;q.append(v) +if cut not in prev:raise SystemExit(f'no path {net} {old}->{cut}') +kill=[];cur=cut +while cur!=old:kill.append(pedge[cur]);cur=prev[cur] +for t in kill:b.Remove(t) +pcbnew.SaveBoard(P,b,True) +print(net,'removed',len(kill),'segments') diff --git a/hardware/stack/update_exact_part_schematics.py b/hardware/stack/update_exact_part_schematics.py new file mode 100644 index 0000000..8962954 --- /dev/null +++ b/hardware/stack/update_exact_part_schematics.py @@ -0,0 +1,56 @@ +#!/usr/bin/env python3 +from pathlib import Path +import re +D=Path('/home/ik/ChatGPT/Courant/hardware/panel/design') + +def replace_count(path,old,new,count): + p=D/path;s=p.read_text();n=s.count(old) + if n!=count: raise RuntimeError(f'{path}: {old!r} count {n}, expected {count}') + p.write_text(s.replace(old,new)) + return n + +# Exact drop-in production connectors. +replace_count('power.kicad_sch','"EURORACK 10 PIN"','"61201021621"',2) +replace_count('power.kicad_sch','"RadianPanel:IDC_2x05_P2.54_Shrouded"','"RadianPanel:Wurth_61201021621_Exact_B"',2) +replace_count('power.kicad_sch','"SELECT keyed 2x05 IDC 2.54 mm header"','"61201021621"',1) + +replace_count('power.kicad_sch','"DESKTOP 12 V INPUT"','"22-27-2021"',2) +replace_count('power.kicad_sch','"RadianPanel:Header_1x02_P2.54"','"RadianPanel:Molex_22-27-2021_J201_B"',2) +replace_count('power.kicad_sch','"SELECT locking 2-pin >=2A connector; P2.54 footprint"','"22-27-2021"',1) + +replace_count('io.kicad_sch','"TO OFF-BOARD MIDI DIN"','"22-27-2021"',2) +replace_count('io.kicad_sch','"RadianPanel:Header_1x02_P2.54"','"RadianPanel:Molex_22-27-2021_J306_B"',2) +replace_count('io.kicad_sch','"SELECT 2.54 mm 1x02 header"','"22-27-2021"',1) + +replace_count('service.kicad_sch','"JTAG SERVICE"','"22-27-2061"',2) +replace_count('service.kicad_sch','"RadianPanel:Header_1x06_P2.54"','"RadianPanel:Molex_22-27-2061_J202_B"',2) +replace_count('service.kicad_sch','"SELECT 2.54 mm 1x06 header"','"22-27-2061"',1) + +# JP1: actual Wurth SPDT pinout. Old schematic positions top/middle/bottom were +# pins 1/2/3 = MOD_RAW/MOD_IN/MOD_BIPOLAR. Actual switch is: +# pin 3 = top MOD_RAW, pin 1 = middle common MOD_IN, pin 2 = bottom MOD_BIPOLAR. +p=D/'mod.kicad_sch';s=p.read_text() +s=s.replace('"MOD RANGE: 1-2 UNI / 2-3 BI"','"450301014042"') +s=s.replace('"RadianPanel:Header_1x03_P2.54"','"RadianPanel:Wurth_450301014042_Exact_B"') +s=s.replace('"2.54 mm 1x03 header + removable shunt"','"450301014042"') +# Symbol definition: edit the three pins by their fixed locations. +start=s.index('(symbol "JP1_1_1"'); end=s.index('(property "Description"',start) +block=s[start:end] +for at,num in [('(at -12.7 2.54 0)','3'),('(at -12.7 0.0 0)','1'),('(at -12.7 -2.54 0)','2')]: + i=block.index(at); j=block.find('(pin passive line',i+1); j=len(block) if j<0 else j + seg=block[i:j] + seg=re.sub(r'\(name "[123]"',f'(name "{num}"',seg) + seg=re.sub(r'\(number "[123]"',f'(number "{num}"',seg) + block=block[:i]+seg+block[j:] +s=s[:start]+block+s[end:] +# Instance pin UUIDs follow the same fixed graphical positions. +mapping={ + '031fc1de-f652-56e7-993b-2ddd33f1cf5b':'3', + 'a988563f-0536-5d32-9cf9-0b06dc0ab031':'1', + '4b7ea1de-3e57-5a72-ba4b-1ca26cb4b4f4':'2'} +for uid,num in mapping.items(): + s=re.sub(r'\(pin "[123]"\s*\(uuid "'+re.escape(uid)+r'"\)\)',f'(pin "{num}"\n (uuid "{uid}"))',s,count=1) +s=s.replace('DEFAULT: shunt JP1 pins 1-2 = direct unipolar MOD; preserve existing firmware interpretation.', + 'JP1 is an SPDT configuration switch: one throw selects direct unipolar MOD_RAW; the other selects MOD_BIPOLAR.') +p.write_text(s) +print('schematics updated for exact service parts') diff --git a/hardware/stack/update_exact_part_symbol_library.py b/hardware/stack/update_exact_part_symbol_library.py new file mode 100644 index 0000000..e56fe6b --- /dev/null +++ b/hardware/stack/update_exact_part_symbol_library.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +from pathlib import Path +import re +p=Path('/home/ik/ChatGPT/Courant/hardware/panel/library/RadianPanel.kicad_sym') +s=p.read_text() +pairs=[ +('"TO OFF-BOARD MIDI DIN"','"22-27-2021"'), +('"RadianPanel:Header_1x02_P2.54"','"RadianPanel:Molex_22-27-2021_J306_B"'), +('"EURORACK 10 PIN"','"61201021621"'), +('"RadianPanel:IDC_2x05_P2.54_Shrouded"','"RadianPanel:Wurth_61201021621_Exact_B"'), +('"DESKTOP 12 V INPUT"','"22-27-2021"'), +('"JTAG SERVICE"','"22-27-2061"'), +('"RadianPanel:Header_1x06_P2.54"','"RadianPanel:Molex_22-27-2061_J202_B"'), +('"MOD RANGE: 1-2 UNI / 2-3 BI"','"450301014042"'), +('"RadianPanel:Header_1x03_P2.54"','"RadianPanel:Wurth_450301014042_Exact_B"'), +] +# Header_1x02 occurs J201 too, so handle symbol blocks separately instead of global ambiguity. +def block_replace(text,sym,old,new): + a=text.index(f'(symbol "{sym}"'); b=text.find('\n (symbol "',a+10) + if b<0:b=len(text) + block=text[a:b] + if old not in block:raise RuntimeError(f'{sym}: missing {old}') + block=block.replace(old,new) + return text[:a]+block+text[b:] +s=block_replace(s,'J306','"TO OFF-BOARD MIDI DIN"','"22-27-2021"') +s=block_replace(s,'J306','"RadianPanel:Header_1x02_P2.54"','"RadianPanel:Molex_22-27-2021_J306_B"') +s=block_replace(s,'J200','"EURORACK 10 PIN"','"61201021621"') +s=block_replace(s,'J200','"RadianPanel:IDC_2x05_P2.54_Shrouded"','"RadianPanel:Wurth_61201021621_Exact_B"') +s=block_replace(s,'J201','"DESKTOP 12 V INPUT"','"22-27-2021"') +s=block_replace(s,'J201','"RadianPanel:Header_1x02_P2.54"','"RadianPanel:Molex_22-27-2021_J201_B"') +s=block_replace(s,'J202','"JTAG SERVICE"','"22-27-2061"') +s=block_replace(s,'J202','"RadianPanel:Header_1x06_P2.54"','"RadianPanel:Molex_22-27-2061_J202_B"') +s=block_replace(s,'JP1','"MOD RANGE: 1-2 UNI / 2-3 BI"','"450301014042"') +s=block_replace(s,'JP1','"RadianPanel:Header_1x03_P2.54"','"RadianPanel:Wurth_450301014042_Exact_B"') +# JP1 actual Wurth physical pin numbering. +a=s.index('(symbol "JP1"'); b=s.find('\n (symbol "',a+10); block=s[a:b] +suba=block.index('(symbol "JP1_1_1"'); subb=block.index('(property "Description"',suba) +pins=block[suba:subb] +for at,num in [('(at -12.7 2.54 0)','3'),('(at -12.7 0.0 0)','1'),('(at -12.7 -2.54 0)','2')]: + i=pins.index(at); j=pins.find('(pin passive line',i+1); j=len(pins) if j<0 else j + seg=pins[i:j] + seg=re.sub(r'\(name "[123]"',f'(name "{num}"',seg) + seg=re.sub(r'\(number "[123]"',f'(number "{num}"',seg) + pins=pins[:i]+seg+pins[j:] +block=block[:suba]+pins+block[subb:] +s=s[:a]+block+s[b:] +p.write_text(s) +print('external symbol library synchronized') diff --git a/hardware/stack/validate_actual_parts_collisions.py b/hardware/stack/validate_actual_parts_collisions.py new file mode 100644 index 0000000..634b68c --- /dev/null +++ b/hardware/stack/validate_actual_parts_collisions.py @@ -0,0 +1,91 @@ +#!/usr/bin/env python3 +from pathlib import Path +import json,time +import cadquery as cq + +ROOT=Path('/home/ik/ChatGPT/Courant/hardware') +D=ROOT/'stack/actual_parts' +CASE=ROOT/'panel/cad/RADIAN_P1_case_shell_updated.step' +PANEL_T=(0.0,128.5,-9.6) +MAIN_T=(-12.0,164.25,-31.10) + +def load(fn,t): + return cq.importers.importStep(str(D/fn)).val().translate(t) + +case_assy=cq.Assembly.importStep(str(CASE)) +physical_case_names={ + 'panel','mode_blank','rear_guard','desktop_dock', + 'corner_support_BL','corner_support_BR','corner_support_TL','corner_support_TR', + 'midi_support' +} +physical_case={c.name:c.obj.moved(c.loc) for c in case_assy.children if c.name in physical_case_names} + +panel_enclosure={ + 'panel_pots':load('panel-pots-raw.step',PANEL_T), + 'panel_encoder':load('panel-encoder-raw.step',PANEL_T), + 'panel_mode':load('panel-mode-raw.step',PANEL_T), + 'panel_jacks':load('panel-jacks-only-raw.step',PANEL_T), + 'panel_leds':load('panel-leds-only-raw.step',PANEL_T), +} +enclosure_clashes=[] +for gn,g in panel_enclosure.items(): + bg=g.BoundingBox() + for cn,c in physical_case.items(): + bc=c.BoundingBox() + if bg.xmax1e-5: + enclosure_clashes.append({'component_group':gn,'case_solid':cn,'volume_mm3':round(v,7)}) + +main_files=[ + 'main-board-raw.step','main-ics-only-raw.step','main-service-connectors-raw.step', + 'main-resistors-raw.step','main-capacitors-raw.step','main-diodes-raw.step', + 'main-inductors-raw.step','main-oscillators-raw.step' +] +main_non_samtec=cq.Compound.makeCompound([load(f,MAIN_T) for f in main_files]) +panel_files=[ + 'panel-pots-raw.step','panel-encoder-raw.step','panel-mode-raw.step', + 'panel-jacks-only-raw.step','panel-leds-only-raw.step','panel-wurth-raw.step', + 'panel-molex-raw.step','panel-buttons-raw.step','panel-ics-raw.step', + 'panel-resistors-raw.step','panel-capacitors-raw.step','panel-power-discretes-raw.step' +] +panel_main_clashes=[] +overlap=0.0 +for fn in panel_files: + g=load(fn,PANEL_T) + # cheap Z bbox prune + bg=g.BoundingBox(); bm=main_non_samtec.BoundingBox() + if bg.zmaxbm.zmax: + continue + v=abs(g.intersect(main_non_samtec).Volume()) + overlap+=v + if v>1e-5: + panel_main_clashes.append({'file':fn,'volume_mm3':round(v,7)}) + +raw_panel=cq.importers.importStep(str(D/'panel-board-raw.step')).val().BoundingBox() +raw_main=cq.importers.importStep(str(D/'main-board-raw.step')).val().BoundingBox() +panel_back=PANEL_T[2]+raw_panel.zmin +main_front=MAIN_T[2]+raw_main.zmax +gap=panel_back-main_front + +report={ + 'status':'PASS' if abs(gap-19.99)<0.001 and not enclosure_clashes and not panel_main_clashes else 'FAIL', + 'physical_pcb_faces':{ + 'panel_back_z_mm':round(panel_back,4), + 'main_front_z_mm':round(main_front,4), + 'gap_mm':round(gap,4), + 'target_mm':19.99, + }, + 'actual_components_vs_physical_enclosure_clashes':enclosure_clashes, + 'non_samtec_panel_vs_main_clashes':panel_main_clashes, + 'non_samtec_panel_vs_main_overlap_mm3':round(overlap,7), + 'notes':[ + 'Reference nuts, shims, standoffs, inks and PCB visualization layers are excluded from enclosure clash classification.', + 'The intentionally mated Samtec J100/J101 to J17/J18 pair is excluded from panel-vs-main clash classification.' + ] +} +out=ROOT/'stack/actual-parts-collision-validation.json' +out.write_text(json.dumps(report,indent=2)+'\n') +print(json.dumps(report,indent=2)) +if report['status']!='PASS': raise SystemExit(1) diff --git a/hardware/stack/validate_direct_stack.py b/hardware/stack/validate_direct_stack.py new file mode 100755 index 0000000..f77b587 --- /dev/null +++ b/hardware/stack/validate_direct_stack.py @@ -0,0 +1,243 @@ +#!/usr/bin/env python3 +"""Validate the physical/electrical RADIAN panel-to-mainboard direct stack. + +Checks both 20-pin connectors pin-by-pin (40 contacts total), including: +- exact Samtec MPN and board side, +- manufacturer-recommended hole diameters, +- product-space XY coincidence for every physical pin, +- pin-number and net-name coincidence (no row reversal / pin swap), +- attached drawing-derived 3D reference models, +- -06/-01 mated board gap, insertion and wipe, +- through-hole tail protrusion through 1.6 mm PCBs. +""" +from pathlib import Path +import json, math +import pcbnew + +ROOT = Path(__file__).resolve().parents[1] +STACK = json.loads((ROOT/'stack/panel-stack.json').read_text()) +PANEL = ROOT/'panel/design/radian_panel.kicad_pcb' +MAIN = ROOT/'courant/deliverables/courant.kicad_pcb' +OUT = ROOT/'stack/direct-stack-validation.json' + +EXPECTED = { + 'fully_mated_gap_mm': 19.99, + 'max_gap_mm': 20.45, + 'fully_mated_wipe_mm': 0.84, + 'min_wipe_at_max_gap_mm': 0.38, + 'main_insulation_height_mm': 15.30, + 'main_tail_mm': 2.35, + 'main_hole_mm': 1.02, + 'panel_height_mm': 8.51, + 'panel_tail_mm': 2.54, + 'panel_hole_mm': 1.04, + 'pcb_thickness_mm': 1.6, +} +MODEL_REL = { + 'main': '${KIPRJMOD}/../../stack/models/Samtec_IPT1-110-06-L-D_drawing_reference.step', + 'panel': '${KIPRJMOD}/../../stack/models/Samtec_IPS1-110-01-L-D_drawing_reference.step', +} + + +def mm(v): + return pcbnew.ToMM(v) + + +def product_xy(kind, pos): + x, y = mm(pos.x), mm(pos.y) + if kind == 'panel': + return x, 128.5 - y + if kind == 'main': + return x - 12.0, 164.25 - y + raise ValueError(kind) + + +def fp_by_ref(board, ref): + return next(f for f in board.GetFootprints() if f.GetReference() == ref) + + +def pad_map(fp): + return {p.GetNumber(): p for p in fp.Pads()} + + +def model_names(fp): + return [m.m_Filename for m in fp.Models() if m.m_Show] + + +def drill_mm(pad): + d = pad.GetDrillSize() + return round(mm(d.x), 4), round(mm(d.y), 4) + + +def close(a,b,tol=1e-4): + return abs(a-b) <= tol + + +def main(): + pb = pcbnew.LoadBoard(str(PANEL)) + mb = pcbnew.LoadBoard(str(MAIN)) + report = { + 'status':'PASS', + 'sources': { + 'stack_contract': str((ROOT/'stack/panel-stack.json').relative_to(ROOT)), + 'panel_board': str(PANEL.relative_to(ROOT)), + 'main_board': str(MAIN.relative_to(ROOT)), + 'manufacturer_drawings': [ + 'Samtec IPT1-1XX-XX-XX-D-XX Rev AA', + 'Samtec IPS1-1XX-XX-XX-D-XX Rev S', + 'Samtec IPX1 MATED DOCUMENT Rev C', + 'Samtec IPT1 and IPS1 recommended through-hole PCB layouts', + ], + }, + 'pairs': [], + 'mechanical': {}, + 'errors': [], + } + + main_spec = STACK['connector_footprint']['main'] + panel_spec = STACK['connector_footprint']['panel'] + + # Contract-vs-drawing constants. + mechanical = report['mechanical'] + mechanical['fully_mated_gap_mm'] = STACK['mating']['fully_mated_gap_mm'] + mechanical['max_gap_mm'] = STACK['mating']['max_gap_mm'] + mechanical['fully_mated_wipe_mm'] = STACK['mating']['fully_mated_wipe_mm'] + mechanical['min_wipe_at_max_gap_mm'] = STACK['mating']['min_wipe_at_max_gap_mm'] + mechanical['main_insulation_height_mm'] = main_spec['insulation_height_mm'] + mechanical['panel_height_mm'] = panel_spec['body_height_mm'] + mechanical['nominal_geometric_insertion_mm'] = round( + main_spec['insulation_height_mm'] + panel_spec['body_height_mm'] - + STACK['mating']['fully_mated_gap_mm'], 3) + mechanical['geometric_insertion_at_max_gap_mm'] = round( + main_spec['insulation_height_mm'] + panel_spec['body_height_mm'] - + STACK['mating']['max_gap_mm'], 3) + mechanical['panel_tail_protrusion_past_opposite_face_mm'] = round( + panel_spec['post_tail_mm'] - EXPECTED['pcb_thickness_mm'], 3) + mechanical['main_tail_protrusion_past_opposite_face_mm'] = round( + main_spec['post_tail_mm'] - EXPECTED['pcb_thickness_mm'], 3) + # Panel F surface is 8 mm behind the faceplate rear in the active CAD. + mechanical['panel_tail_to_faceplate_rear_clearance_mm'] = round( + 8.0 - mechanical['panel_tail_protrusion_past_opposite_face_mm'], 3) + + checks = [ + ('fully_mated_gap_mm', EXPECTED['fully_mated_gap_mm']), + ('max_gap_mm', EXPECTED['max_gap_mm']), + ('fully_mated_wipe_mm', EXPECTED['fully_mated_wipe_mm']), + ('min_wipe_at_max_gap_mm', EXPECTED['min_wipe_at_max_gap_mm']), + ('main_insulation_height_mm', EXPECTED['main_insulation_height_mm']), + ('panel_height_mm', EXPECTED['panel_height_mm']), + ] + for key, expected in checks: + if not close(mechanical[key], expected): + report['errors'].append(f'{key}: {mechanical[key]} != manufacturer {expected}') + + for con in STACK['connectors']: + mf = fp_by_ref(mb, con['main_ref']) + pf = fp_by_ref(pb, con['panel_ref']) + pair = { + 'id': con['id'], + 'main_ref': con['main_ref'], + 'panel_ref': con['panel_ref'], + 'main_value': mf.GetValue(), + 'panel_value': pf.GetValue(), + 'main_side': 'B' if mf.GetLayer()==pcbnew.B_Cu else 'F', + 'panel_side': 'B' if pf.GetLayer()==pcbnew.B_Cu else 'F', + 'main_models': model_names(mf), + 'panel_models': model_names(pf), + 'pins': [], + } + + if mf.GetValue() != main_spec['mpn']: + report['errors'].append(f"{con['main_ref']} MPN {mf.GetValue()} != {main_spec['mpn']}") + if pf.GetValue() != panel_spec['mpn']: + report['errors'].append(f"{con['panel_ref']} MPN {pf.GetValue()} != {panel_spec['mpn']}") + if pair['main_side'] != 'F': + report['errors'].append(f"{con['main_ref']} must be on mainboard F side") + if pair['panel_side'] != 'B': + report['errors'].append(f"{con['panel_ref']} must be on panel B side") + if MODEL_REL['main'] not in pair['main_models']: + report['errors'].append(f"{con['main_ref']} exact stack reference model missing") + if MODEL_REL['panel'] not in pair['panel_models']: + report['errors'].append(f"{con['panel_ref']} exact stack reference model missing") + + main_center = product_xy('main', mf.GetPosition()) + panel_center = product_xy('panel', pf.GetPosition()) + contract_main_center = ( + STACK['mainboard_product_offset_mm']['x'] + con['main_xy_mm']['x'], + STACK['mainboard_product_offset_mm']['y'] + con['main_xy_mm']['y']) + contract_panel_center = (con['panel_xy_mm']['x'], con['panel_xy_mm']['y']) + pair['main_center_product_mm'] = [round(x,4) for x in main_center] + pair['panel_center_product_mm'] = [round(x,4) for x in panel_center] + pair['contract_center_product_mm'] = [round(x,4) for x in contract_panel_center] + + for a,b,label in [ + (main_center, panel_center, 'native board connector centers'), + (main_center, contract_main_center, 'main native vs stack contract'), + (panel_center, contract_panel_center, 'panel native vs stack contract'), + (contract_main_center, contract_panel_center, 'stack contract main vs panel')]: + if math.dist(a,b) > 1e-4: + report['errors'].append(f"{con['id']} {label} mismatch: {a} vs {b}") + + mp = pad_map(mf); pp = pad_map(pf) + if set(mp) != {str(i) for i in range(1,21)}: + report['errors'].append(f"{con['main_ref']} does not contain pins 1..20 exactly") + if set(pp) != {str(i) for i in range(1,21)}: + report['errors'].append(f"{con['panel_ref']} does not contain pins 1..20 exactly") + + for n in range(1,21): + key=str(n); m=mp[key]; p=pp[key] + mxy=product_xy('main',m.GetPosition()) + pxy=product_xy('panel',p.GetPosition()) + mn=m.GetNetname(); pn=p.GetNetname() + md=drill_mm(m); pd=drill_mm(p) + rec={ + 'pin':n, + 'net':mn, + 'main_product_xy_mm':[round(v,4) for v in mxy], + 'panel_product_xy_mm':[round(v,4) for v in pxy], + 'xy_error_mm':round(math.dist(mxy,pxy),6), + 'main_drill_mm':md, + 'panel_drill_mm':pd, + 'net_match':mn==pn, + } + pair['pins'].append(rec) + if math.dist(mxy,pxy)>1e-4: + report['errors'].append(f"{con['id']} pin {n} physical XY mismatch {mxy} vs {pxy}") + if mn != pn: + report['errors'].append(f"{con['id']} pin {n} net mismatch {mn} vs {pn}") + if not (close(md[0],EXPECTED['main_hole_mm']) and close(md[1],EXPECTED['main_hole_mm'])): + report['errors'].append(f"{con['main_ref']} pin {n} drill {md} != 1.02 mm") + if not (close(pd[0],EXPECTED['panel_hole_mm']) and close(pd[1],EXPECTED['panel_hole_mm'])): + report['errors'].append(f"{con['panel_ref']} pin {n} drill {pd} != 1.04 mm") + + pair['matched_pins'] = sum(1 for p in pair['pins'] if p['xy_error_mm']==0 and p['net_match']) + report['pairs'].append(pair) + + # Ensure model files themselves exist. + for rel in [ + ROOT/'stack/models/Samtec_IPT1-110-06-L-D_drawing_reference.step', + ROOT/'stack/models/Samtec_IPS1-110-01-L-D_drawing_reference.step']: + if not rel.exists() or rel.stat().st_size < 1000: + report['errors'].append(f'missing/empty reference model: {rel}') + + report['total_contacts_checked'] = sum(len(p['pins']) for p in report['pairs']) + report['total_contacts_matched'] = sum(p['matched_pins'] for p in report['pairs']) + if report['errors']: + report['status']='FAIL' + + OUT.write_text(json.dumps(report,indent=2)+'\n') + print(json.dumps({ + 'status':report['status'], + 'contacts':f"{report['total_contacts_matched']}/{report['total_contacts_checked']}", + 'nominal_insertion_mm':mechanical['nominal_geometric_insertion_mm'], + 'max_gap_insertion_mm':mechanical['geometric_insertion_at_max_gap_mm'], + 'panel_tail_faceplate_clearance_mm':mechanical['panel_tail_to_faceplate_rear_clearance_mm'], + 'errors':report['errors'], + 'report':str(OUT), + },indent=2)) + if report['errors']: + raise SystemExit(1) + + +if __name__=='__main__': + main() diff --git a/hardware/stack/verify_model_only_board_edits.py b/hardware/stack/verify_model_only_board_edits.py new file mode 100644 index 0000000..173ebc4 --- /dev/null +++ b/hardware/stack/verify_model_only_board_edits.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +from pathlib import Path +import json, pcbnew, hashlib +ROOT=Path('/home/ik/ChatGPT/Courant/hardware') +BACK=ROOT/'_backups/exact_stack_models_20260918T010444Z' + +def xy(v):return (v.x,v.y) +def signature(path): + b=pcbnew.LoadBoard(str(path)) + tracks=[] + for t in b.GetTracks(): + row=[t.GetClass(),t.GetNetname(),xy(t.GetStart()),xy(t.GetEnd()),t.GetLayer()] + if isinstance(t,pcbnew.PCB_VIA): + row += [t.GetWidth(pcbnew.F_Cu),t.GetDrillValue()] + else: row += [t.GetWidth()] + tracks.append(row) + fps=[] + for f in b.GetFootprints(): + pads=[] + for p in f.Pads(): + pads.append([p.GetNumber(),p.GetNetname(),xy(p.GetPosition()),xy(p.GetSize()),xy(p.GetDrillSize()),p.GetLayerSet().FmtHex()]) + fps.append([f.GetReference(),f.GetValue(),xy(f.GetPosition()),round(f.GetOrientationDegrees(),6),f.GetLayer(),sorted(pads,key=str)]) + return {'tracks':sorted(tracks,key=str),'footprints':sorted(fps,key=str)} + +pairs=[ + ('panel',BACK/'panel/radian_panel.kicad_pcb',ROOT/'panel/design/radian_panel.kicad_pcb'), + ('main',BACK/'main/courant.kicad_pcb',ROOT/'courant/deliverables/courant.kicad_pcb'), +] +report={} +for name,old,new in pairs: + so=signature(old); sn=signature(new) + report[name]={ + 'electrical_geometry_unchanged':so==sn, + 'old_sha256':hashlib.sha256(old.read_bytes()).hexdigest(), + 'new_sha256':hashlib.sha256(new.read_bytes()).hexdigest(), + } + if so!=sn: + raise SystemExit(name+' electrical/placement signature changed') +(ROOT/'stack/model-only-board-edit-validation.json').write_text(json.dumps(report,indent=2)+'\n') +print(json.dumps(report,indent=2)) diff --git a/hardware/synchronization/bare_panel_refresh.json b/hardware/synchronization/bare_panel_refresh.json new file mode 100644 index 0000000..2867660 --- /dev/null +++ b/hardware/synchronization/bare_panel_refresh.json @@ -0,0 +1,19 @@ +{ + "native_bbox": [ + 18.0, + -118.5, + 0.0, + 198.5, + -10.5, + 1.51 + ], + "panel_coordinate_bbox": [ + 18.0, + 10.0, + -9.51, + 198.5, + 118.0, + -8.0 + ], + "valid": true +} \ No newline at end of file diff --git a/hardware/synchronization/cad_reimport_validation.json b/hardware/synchronization/cad_reimport_validation.json new file mode 100644 index 0000000..51a1bb4 --- /dev/null +++ b/hardware/synchronization/cad_reimport_validation.json @@ -0,0 +1,44 @@ +[ + { + "file": "RADIAN_P1_desktop_fit_study.step", + "bytes": 96556477, + "imported_leaf_parts": 178, + "bbox": [ + -6.0, + -6.0, + -57.0, + 208.8, + 134.5, + 22.06 + ], + "step_import_succeeded": true + }, + { + "file": "RADIAN_P1_populated_reference.step", + "bytes": 30417443, + "imported_leaf_parts": 148, + "bbox": [ + 18.0, + 10.0, + -18.8, + 198.5, + 118.0, + 19.4 + ], + "step_import_succeeded": true + }, + { + "file": "courant-assembly.step", + "bytes": 30311145, + "imported_leaf_parts": 191, + "bbox": [ + 20.0, + -150.0, + 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"/home/ik/ChatGPT/RADIAN_Release_Sync_20260916T015425Z/stage/main/courant.kicad_pcb", + "source_panel": "/home/ik/ChatGPT/RADIAN_Release_Sync_20260916T015425Z/stage/panel/design/radian_panel.kicad_pcb", + "product_visual_simplification": "Product assembly retains the current mainboard substrate, drilled holes, components, masks and silkscreen but omits separate copper track/pad/barrel solids. Full copper is retained in courant-assembly.step.", + "scope": "Native board geometry synchronized. Existing reference components, enclosure, fastener assumptions and unverified mechanical tolerances are retained; no new physical fit approval." +} \ No newline at end of file diff --git a/hardware/synchronization/published_main_alias_drc.command.json b/hardware/synchronization/published_main_alias_drc.command.json new file mode 100644 index 0000000..3813ea4 --- /dev/null +++ b/hardware/synchronization/published_main_alias_drc.command.json @@ -0,0 +1,17 @@ +{ + "command": [ + "/home/ik/ChatGPT/RADIAN_Backplane_review_3ldc8m0x/tools/runtime/backplane-kicad-linux-x86_64-10.0.6/bin/kicad-cli", + "pcb", + "drc", + "--refill-zones", + "--all-track-errors", + "--severity-all", + "--exit-code-violations", + "--format", + "json", + "--output", + "/home/ik/ChatGPT/RADIAN_Release_Sync_20260916T015425Z/reports/published_main_alias_drc.json", + "/home/ik/ChatGPT/Courant/hardware/courant/dist/courant.routed.kicad_pcb" + ], + "exit_code": 0 +} \ No newline at end of file diff --git a/hardware/synchronization/published_main_drc.command.json b/hardware/synchronization/published_main_drc.command.json new file mode 100644 index 0000000..24cef39 --- /dev/null +++ b/hardware/synchronization/published_main_drc.command.json @@ -0,0 +1,17 @@ +{ + "command": [ + "/home/ik/ChatGPT/RADIAN_Backplane_review_3ldc8m0x/tools/runtime/backplane-kicad-linux-x86_64-10.0.6/bin/kicad-cli", + "pcb", + "drc", + "--refill-zones", + "--all-track-errors", + "--severity-all", + "--exit-code-violations", + "--format", + "json", + "--output", + "/home/ik/ChatGPT/RADIAN_Release_Sync_20260916T015425Z/reports/published_main_drc.json", + "/home/ik/ChatGPT/Courant/hardware/courant/deliverables/courant.kicad_pcb" + ], + "exit_code": 0 +} \ No newline at end of file diff --git a/hardware/synchronization/published_panel_drc.command.json b/hardware/synchronization/published_panel_drc.command.json new file mode 100644 index 0000000..61985ad --- /dev/null +++ b/hardware/synchronization/published_panel_drc.command.json @@ -0,0 +1,18 @@ +{ + "command": [ + "/home/ik/ChatGPT/RADIAN_Backplane_review_3ldc8m0x/tools/runtime/backplane-kicad-linux-x86_64-10.0.6/bin/kicad-cli", + "pcb", + "drc", + "--refill-zones", + "--all-track-errors", + "--severity-all", + "--exit-code-violations", + "--format", + "json", + "--output", + "/home/ik/ChatGPT/RADIAN_Release_Sync_20260916T015425Z/reports/published_panel_drc.json", + "--schematic-parity", + "/home/ik/ChatGPT/Courant/hardware/panel/design/radian_panel.kicad_pcb" + ], + "exit_code": 0 +} \ No newline at end of file diff --git a/hardware/synchronization/published_panel_erc.command.json b/hardware/synchronization/published_panel_erc.command.json new file mode 100644 index 0000000..b0ff878 --- /dev/null +++ b/hardware/synchronization/published_panel_erc.command.json @@ -0,0 +1,15 @@ +{ + "command": [ + "/home/ik/ChatGPT/RADIAN_Backplane_review_3ldc8m0x/tools/runtime/backplane-kicad-linux-x86_64-10.0.6/bin/kicad-cli", + "sch", + "erc", + "--severity-all", + "--exit-code-violations", + "--format", + "json", + "--output", + "/home/ik/ChatGPT/RADIAN_Release_Sync_20260916T015425Z/reports/published_panel_erc.json", + "/home/ik/ChatGPT/Courant/hardware/panel/design/radian_panel.kicad_sch" + ], + "exit_code": 0 +} \ No newline at end of file diff --git a/model/Exciter.m b/model/Exciter.m index 2c96f9e..ee7ae07 100644 --- a/model/Exciter.m +++ b/model/Exciter.m @@ -1,11 +1,11 @@ classdef Exciter < handle % Exciter Physical excitation front-ends for the mesh (issue #33). % - % Replaces the raw single-sample "mallet" strike with physical exciter - % models that COUPLE to the surface: each step the exciter reads the surface - % displacement at the excitation node and returns a force to inject there, - % closing the interaction loop (milestone M9). Reference-model only; the - % study vehicle for the RTL feasibility recommendation. + % Physical exciter study model from issue #33. The mallet concept is now + % implemented in production RTL by issue #87 (`physical_mallet.vhd`), while + % this class remains the floating-point/SI-scale character reference. The + % production fixed-point normalization is mirrored independently by + % `mallet_reference.py`. The bow branch remains reference-only. % % Two types: % diff --git a/model/StiffMesh2D.m b/model/StiffMesh2D.m index 4e0dda6..739a07b 100644 --- a/model/StiffMesh2D.m +++ b/model/StiffMesh2D.m @@ -3,8 +3,11 @@ % % Extends the lossy wave equation of Mesh2D with a 4th-order bending term % (stiff plate / bar) and direction-dependent wave speed (anisotropy), - % exploring "advanced materials" for milestone M9. Reference-model only: - % this is the study vehicle for the go/no-go RTL recommendation, not RTL. + % exploring "advanced materials" for milestone M9. This remains the + % floating-point study/reference model; issue #86 has since integrated the + % biharmonic term into RTL. See radian_stiffness_ctrl.m for the production + % 8-bit STIFFNESS->mu2/CFL mapping and stiffness_reference.py for the + % bit-exact fixed-point production reference. % % u_tt = cx^2 u_xx + cy^2 u_yy - kappa^2 (u_xxxx + 2 u_xxyy + u_yyyy) % - 2 sigma u_t diff --git a/model/exciter_study.m b/model/exciter_study.m index 5c3754a..f9f883d 100644 --- a/model/exciter_study.m +++ b/model/exciter_study.m @@ -1,8 +1,10 @@ function exciter_study(varargin) -% EXCITER_STUDY Physical exciter front-ends against the engine (issue #33). +% EXCITER_STUDY Physical exciter front-ends against the engine (#33/#87). % -% Reference-model study for the "exciter models" stretch (milestone M9). Drives -% a Mesh2D at the excitation node through the Exciter models, closing the +% Floating-point/SI-scale study for the exciter models. Issue #87 has since +% integrated the mallet into production fixed-point RTL; this study remains the +% physical-character reference, while mallet_reference.py mirrors the exact RTL. +% It drives a Mesh2D at the excitation node through the Exciter models, closing the % coupling loop (the exciter reads the node displacement and returns a force): % % A. mallet hardness sweep - softer/harder springs give longer/shorter diff --git a/model/mallet_reference.py b/model/mallet_reference.py new file mode 100644 index 0000000..12a6609 --- /dev/null +++ b/model/mallet_reference.py @@ -0,0 +1,103 @@ +#!/usr/bin/env python3 +"""Bit-exact normalized reference for the #87 physical mallet. + +This mirrors physical_pkg + physical_mallet and documents the production +HARDNESS law independently of the RTL. The original floating-point Exciter.m +study remains the SI-scale feasibility/character reference. +""" +from pathlib import Path + +FRAC=23 +QMAX=2**23-1 +QMIN=-(2**23) + +def sat(x): + return max(QMIN,min(QMAX,int(x))) + +def toq(x): + return sat(round(x*(2**FRAC))) + +def contact_raw(compression, hardness): + if compression<=0 or hardness<=0: + return 0 + sq=0 + for p in range(22,-1,-1): + if compression & (1<>(FRAC-p) + break + base=sq + # Exact RTL: base/2 + (base*hardness + 32)/64. + return sat((base>>1)+((base*hardness+32)>>6)) + +def surface_force(compression, hardness): + return sat(contact_raw(compression,hardness)<<4) + +def launch_velocity(strike): + mag=abs(int(strike)) + if mag>QMAX: + mag=QMAX + return mag>>9 + +def run(hardness, amplitude=0.5, steps=2048, surface=0): + gap=toq(0.008) + hx=surface-gap + hv=launch_velocity(toq(amplitude)) + touched=False + active=hv!=0 and hardness!=0 + trace=[] + contacts=0 + for _ in range(steps): + compression=sat(hx-surface) if active else 0 + raw=contact_raw(compression,hardness) if active else 0 + fout=surface_force(compression,hardness) if active else 0 + stop_after_step = False + if raw>0: + touched=True + elif touched: + stop_after_step=True + # RTL performs the semi-implicit update on the separation edge, then + # clears running via a signal assignment for the following cycle. + if active: + vnext=sat(hv-(raw>>7)) + hv=vnext + hx=sat(hx+vnext) + if stop_after_step: + active=False + compression2=sat(hx-surface) if active else 0 + fout2=surface_force(compression2,hardness) if active else 0 + contact2=active and contact_raw(compression2,hardness)>0 + if contact2: + contacts+=1 + trace.append((fout2,int(contact2),int(active),hx,hv)) + if not active and touched: + break + return contacts,trace + +def main(): + fs_mesh=48_000*4 + labels=[("soft",0x20),("medium",0x80),("hard",0xFF)] + results=[] + for name,h in labels: + c,tr=run(h) + ms=1000*c/fs_mesh + peak=max(abs(x[0]) for x in tr) + results.append((name,h,c,ms,peak)) + assert results[0][2]>results[1][2]>results[2][2] + slow,_=run(0x80,0.20) + fast,_=run(0x80,0.85) + assert slow>fast + + out=Path(__file__).resolve().parent.parent/"src"/"tb"/"mallet_trace.txt" + _,trace=run(0x80,0.50) + with out.open("w",encoding="utf-8") as f: + f.write("# force contact active hammer_x hammer_v; HARDNESS=0x80 velocity=0.5\n") + for row in trace: + f.write(" ".join(str(x) for x in row)+"\n") + + for name,h,c,ms,peak in results: + print(f"{name:6s} HARDNESS=0x{h:02X}: contact={c} steps = {ms:.3f} ms, peak force={peak}") + print(f"velocity check @0x80: 0.20 -> {slow} steps, 0.85 -> {fast} steps") + print(f"wrote {len(trace)} medium-hardness samples to {out}") + +if __name__=="__main__": + main() diff --git a/model/radian_stiffness_ctrl.m b/model/radian_stiffness_ctrl.m new file mode 100644 index 0000000..5da42ec --- /dev/null +++ b/model/radian_stiffness_ctrl.m @@ -0,0 +1,21 @@ +function [mu2, gamma2_max_eff] = radian_stiffness_ctrl(ctrl, gamma2_max) +% RADIAN_STIFFNESS_CTRL Production #86 STIFFNESS control mapping. +% +% ctrl is the stored unsigned 8-bit value (0..255). +% mu2 = ctrl / 4096 +% +% The current RADIAN anisotropy redistributes X/Y propagation while preserving +% g2x+g2y = 2*gamma2, so the studied stiff-surface stability condition +% +% (g2x+g2y) + 16*mu2 <= 1 +% +% becomes gamma2 <= 0.5 - 8*mu2. gamma2_max_eff is also capped by the +% pre-existing gamma2_max safety ceiling. +% +% This helper mirrors src/rtl/physical_pkg.vhd. + if nargin < 2 || isempty(gamma2_max); gamma2_max = 0.451; end + assert(ctrl >= 0 && ctrl <= 255 && ctrl == floor(ctrl), ... + 'ctrl must be an integer in 0..255'); + mu2 = double(ctrl) / 4096.0; + gamma2_max_eff = max(0.0, min(gamma2_max, 0.5 - 8.0 * mu2)); +end diff --git a/model/stiffness_reference.py b/model/stiffness_reference.py new file mode 100644 index 0000000..2978e68 --- /dev/null +++ b/model/stiffness_reference.py @@ -0,0 +1,132 @@ +#!/usr/bin/env python3 +"""Bit-exact fixed-point reference for RADIAN bending stiffness (#86). + +The production control is one unsigned byte: + mu2 = STIFFNESS / 4096 +and the wave CFL ceiling becomes: + gamma2 <= min(gamma2_max, 0.5 - STIFFNESS/512) + +This script regenerates src/tb/stiffness_trace.txt for a fixed-boundary 8x8 +reference case. Integer arithmetic mirrors fdtd_pkg/physical_pkg exactly. +""" +from pathlib import Path +import math + +FRAC = 23 +QMAX = 2**23 - 1 +QMIN = -(2**23) +NX = NY = 8 +STEPS = 80 + +def sat(x): + return min(max(int(x), QMIN), QMAX) + +def toq(x): + return sat(round(x * 2**FRAC)) + +def shr23(x): + return (int(x) + 2**22) // 2**23 + +def qmul(a, b): + return sat(shr23(a * b)) + +def mulc(c, a): + return shr23(c * a) + +def satadd(a, b): + return sat(a + b) + +def stiffness_mu2(ctrl): + return int(ctrl) << 11 + +def stiff_gmax(base, ctrl): + allowed = 2**22 - (int(ctrl) << 14) + return max(0, min(int(base), allowed)) + +def biharm(U, i, j): + def z(y, x): + if y < 0 or y >= NY or x < 0 or x >= NX: + return 0 + return U[y][x] + c = z(i, j) + first = z(i-1,j)+z(i+1,j)+z(i,j+1)+z(i,j-1) + diag = z(i-1,j+1)+z(i-1,j-1)+z(i+1,j+1)+z(i+1,j-1) + second = z(i-2,j)+z(i+2,j)+z(i,j+2)+z(i,j-2) + return 20*c - 8*first + 2*diag + second + +def render(): + g2 = toq(0.08) + a0 = toq(0.9995) + sk = toq(0.9995) + + alpha = toq(0.10) + gmax = toq(0.451) + ctrl = 0x60 + imp = toq(0.9) + mu2 = stiffness_mu2(ctrl) + gmax_eff = stiff_gmax(gmax, ctrl) + + U = [[0 for _ in range(NX)] for _ in range(NY)] + U1 = [[0 for _ in range(NX)] for _ in range(NY)] + trace = [] + for step in range(STEPS): + Un = [[0 for _ in range(NX)] for _ in range(NY)] + for i in range(NY): + for j in range(NX): + c = U[i][j] + prev = U1[i][j] + n = U[i-1][j] if i > 0 else 0 + s = U[i+1][j] if i < NY-1 else 0 + e = U[i][j+1] if j < NX-1 else 0 + w = U[i][j-1] if j > 0 else 0 + u2 = qmul(c, c) + au2 = qmul(alpha, u2) + g2l = min(max(satadd(g2, au2), 0), gmax_eff) + lap = n + s + e + w - 4*c + bend = mulc(mu2, biharm(U, i, j)) + + acc = 2*c - mulc(sk, prev) + mulc(g2l, lap) - bend + out = sat(mulc(a0, acc)) + if step == 0 and i == 4 and j == 4: + out = sat(out + imp) + Un[i][j] = out + U1, U = U, Un + trace.append((U[4][2], U[4][6])) + return trace + +def modal_omega(g2, mu2, mx, my): + # Fixed-boundary discrete eigenvalue of -Laplacian. The plate term is L^2, + # so its contribution grows quadratically with spatial frequency. + lam = 4.0 * ( + math.sin(mx * math.pi / (2.0 * (NX + 1))) ** 2 + + math.sin(my * math.pi / (2.0 * (NY + 1))) ** 2 + ) + q = g2 * lam + mu2 * lam * lam + return math.acos(1.0 - q / 2.0) + +def check_dispersion(): + g2 = 0.08 + mu2 = 0x60 / 4096.0 + low0 = modal_omega(g2, 0.0, 1, 1) + high0 = modal_omega(g2, 0.0, 4, 4) + low1 = modal_omega(g2, mu2, 1, 1) + high1 = modal_omega(g2, mu2, 4, 4) + low_gain = low1 / low0 + high_gain = high1 / high0 + assert high_gain > low_gain > 1.0 + return low_gain, high_gain + +def main(): + trace = render() + low_gain, high_gain = check_dispersion() + out = Path(__file__).resolve().parent.parent / "src" / "tb" / "stiffness_trace.txt" + with out.open("w", encoding="utf-8") as f: + f.write("# L R -- fixed-boundary 8x8, STIFFNESS=0x60, issue #86\n") + for l, r in trace: + f.write(f"{l} {r}\n") + print(f"wrote {len(trace)} stiffness reference steps to {out}") + print(f"mu2(0x60)={0x60/4096:.8f}; effective gamma2_max={0.5-0x60/512:.8f}") + print(f"dispersion check: mode(1,1) x{low_gain:.4f}, mode(4,4) x{high_gain:.4f}") + +if __name__ == "__main__": + main() diff --git a/model/stiffness_study.m b/model/stiffness_study.m index 22f8927..d4e144e 100644 --- a/model/stiffness_study.m +++ b/model/stiffness_study.m @@ -1,5 +1,5 @@ function stiffness_study(varargin) -% STIFFNESS_STUDY Bending stiffness / anisotropy exploration (issue #31). +% STIFFNESS_STUDY Bending stiffness / anisotropy exploration (#31/#86). % % Reference-model study for the "advanced materials" stretch (milestone M9): % A. confirms the stiff-scheme stability boundary (g2x+g2y)+16*mu2 <= 1 diff --git a/sim/Makefile b/sim/Makefile index e96ecb8..7cca90f 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -1,5 +1,11 @@ -STD := --std=08 GHDL := ghdl +WAVE ?= 0 + +ifeq ($(WAVE),1) +RUN_WAVE := --wave=$$tb.ghw +else +RUN_WAVE := +endif RTL_DIR := ../src/rtl TB_DIR := ../src/tb @@ -28,12 +34,14 @@ all: echo "Building: $$tb"; \ $(GHDL) -m $(STD) $$tb || exit 1; \ echo "Running: $$tb"; \ - $(GHDL) -r $(STD) $$tb --wave=$$tb.ghw || exit 1; \ + $(GHDL) -r $(STD) $$tb $(RUN_WAVE) || exit 1; \ done; \ else \ echo "No testbenches found - nothing to simulate."; \ fi +# Waveforms are disabled by default because FX delay/reverb RAMs make full-memory +# GHW dumps very large. Use `make WAVE=1` for waveform-debug runs. clean: $(GHDL) --remove $(STD) >/dev/null 2>&1 || true rm -f *.ghw work-obj*.cf diff --git a/src/rtl/adc_mcp3208.vhd b/src/rtl/adc_mcp3208.vhd new file mode 100644 index 0000000..a38a832 --- /dev/null +++ b/src/rtl/adc_mcp3208.vhd @@ -0,0 +1,208 @@ +------------------------------------------------------------------------------- +-- adc_mcp3208.vhd - SPI master for the panel/CV ADC (U4 on the Courant board) +-- +-- The last piece between the board and the synth: cv_frontend and panel_ctrl +-- both expect samples "already digitised and presented synchronous to clk", +-- and this is what digitises them. It scans the five used channels of the +-- MCP3208 round-robin and holds the most recent conversion of each. +-- +-- CH0 POT_PITCH CH1 POT_DECAY CH2 POT_TIMBRE -> panel_ctrl (unsigned) +-- CH3 PITCH_ADC CH4 MOD_ADC -> cv_frontend (signed) +-- CH5 POT_DRIVE CH6 POT_DELAY CH7 POT_REVERB -> panel_ctrl FX macros +-- +-- Protocol. Single-ended mode, MSB first. With CS low the part ignores leading +-- zeros until it sees the start bit, so the frame is: +-- +-- DIN 1 1 D2 D1 D0 start, SGL/DIFF=1, channel +-- DOUT . null B11..B0 one null bit, then 12 data bits +-- +-- DIN is sampled on the rising edge of SCLK and DOUT changes on the falling +-- edge, so MISO is sampled on the rising edge here. That is SPI mode 0. The +-- frame is 5 + 1 + 12 = 18 clocks; CS is raised between conversions, which the +-- part requires to start the next sample-and-hold. +-- +-- Clock rate. The MCP3208 is specified for 2 MHz at 5 V but only 1 MHz at +-- 2.7 V. This board runs it at VDD = 3.3 V with VREF = 2.5 V, so SCLK_HZ +-- defaults to 1 MHz rather than interpolating between two datasheet corners on +-- a part whose sample-and-hold is the thing being traded away. +-- +-- Scaling. The samples come out as the ADC's native 12-bit codes, zero-extended +-- for the CV outputs. Calibration belongs to cv_frontend's generics, not here. +-- Note that this board's CV divider is 20k/20k into a 2.5 V reference, so full +-- scale is 5 V in and one volt is 819.2 codes -- NOT the 4096 codes per volt +-- that cv_frontend's defaults assume. For 1V/oct tracking instantiate it with +-- CV_SCALE = 960, CV_SHIFT = 16 (65536/68.27 codes per semitone). +-- +-- Synthesisable VHDL-2008. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity adc_mcp3208 is + generic ( + CLK_HZ : positive := 100_000_000; -- system clock + SCLK_HZ : positive := 1_000_000; -- SPI clock; see header before raising + POT_W : positive := 12; -- panel_ctrl's width + CV_W : positive := 16 -- cv_frontend's width + ); + port ( + clk : in std_logic; + rst : in std_logic; + -- SPI to U4 + adc_sclk : out std_logic; + adc_cs_n : out std_logic; + adc_mosi : out std_logic; + adc_miso : in std_logic; + -- held conversions + pot_pitch : out unsigned(POT_W-1 downto 0); + pot_decay : out unsigned(POT_W-1 downto 0); + pot_timbre : out unsigned(POT_W-1 downto 0); + pot_drive : out unsigned(POT_W-1 downto 0); + pot_delay : out unsigned(POT_W-1 downto 0); + pot_reverb : out unsigned(POT_W-1 downto 0); + pitch_cv : out signed(CV_W-1 downto 0); + mod_cv : out signed(CV_W-1 downto 0); + scan_done : out std_logic -- one cycle per completed sweep of all five + ); +end entity adc_mcp3208; + +architecture rtl of adc_mcp3208 is + + -- Half-period of SCLK in system-clock cycles. At least 1, so the divider + -- degrades to clk/2 rather than to a stuck output if CLK_HZ is ever small. + constant HALF : positive := maximum(1, CLK_HZ / (2 * SCLK_HZ)); + constant N_CH : positive := 8; + constant FRAME : positive := 18; -- 5 config + 1 null + 12 data + + type state_t is (IDLE, GAP, XFER); + signal state : state_t := IDLE; + + signal divcnt : natural range 0 to HALF-1 := 0; + signal tick : std_logic := '0'; -- one system cycle per SCLK half-period + signal sclk_q : std_logic := '0'; + signal bitno : natural range 0 to FRAME := 0; + signal chan : natural range 0 to N_CH-1 := 0; + signal shreg : unsigned(11 downto 0) := (others => '0'); + signal gapcnt : natural range 0 to HALF*2 := 0; + + -- Config bits, MSB first: start, SGL/DIFF, D2, D1, D0. + function cfg_bit (c : natural; i : natural) return std_logic is + variable v : unsigned(4 downto 0); + begin + v := "11" & to_unsigned(c, 3); + return v(4 - i); + end function; + +begin + + -- SCLK half-period strobe. + process (clk) is + begin + if rising_edge(clk) then + tick <= '0'; + if rst = '1' then + divcnt <= 0; + elsif divcnt = HALF-1 then + divcnt <= 0; + tick <= '1'; + else + divcnt <= divcnt + 1; + end if; + end if; + end process; + + adc_sclk <= sclk_q; + + process (clk) is + begin + if rising_edge(clk) then + scan_done <= '0'; + + if rst = '1' then + state <= IDLE; + sclk_q <= '0'; + adc_cs_n <= '1'; + adc_mosi <= '0'; + bitno <= 0; + chan <= 0; + gapcnt <= 0; + shreg <= (others => '0'); + pot_pitch <= (others => '0'); + pot_decay <= (others => '0'); + pot_timbre <= (others => '0'); + pot_drive <= (others => '0'); + pot_delay <= (others => '0'); + pot_reverb <= (others => '0'); + pitch_cv <= (others => '0'); + mod_cv <= (others => '0'); + + elsif tick = '1' then + case state is + + when IDLE => + -- Start a frame: CS low, first config bit presented before the + -- first rising edge. + adc_cs_n <= '0'; + sclk_q <= '0'; + bitno <= 0; + adc_mosi <= cfg_bit(chan, 0); + state <= XFER; + + when XFER => + if sclk_q = '0' then + -- Rising edge: the part samples DIN now, and DOUT is stable, so + -- this is where MISO is read. + sclk_q <= '1'; + if bitno >= 6 then -- 0..4 config, 5 null, 6.. data + shreg <= shreg(10 downto 0) & adc_miso; + end if; + else + -- Falling edge: advance, present the next DIN bit. + sclk_q <= '0'; + if bitno = FRAME-1 then + adc_cs_n <= '1'; + gapcnt <= 0; + state <= GAP; + else + bitno <= bitno + 1; + if bitno + 1 <= 4 then + adc_mosi <= cfg_bit(chan, bitno + 1); + else + adc_mosi <= '0'; + end if; + end if; + end if; + + when GAP => + -- CS must go high between conversions; hold it for one SCLK period + -- so the sample-and-hold is released and re-acquired. + if gapcnt = 1 then + case chan is + when 0 => pot_pitch <= resize(shreg, POT_W); + when 1 => pot_decay <= resize(shreg, POT_W); + when 2 => pot_timbre <= resize(shreg, POT_W); + when 3 => pitch_cv <= signed(resize(shreg, CV_W)); + when 4 => mod_cv <= signed(resize(shreg, CV_W)); + when 5 => pot_drive <= resize(shreg, POT_W); + when 6 => pot_delay <= resize(shreg, POT_W); + when others => pot_reverb <= resize(shreg, POT_W); + end case; + if chan = N_CH-1 then + chan <= 0; + scan_done <= '1'; + else + chan <= chan + 1; + end if; + state <= IDLE; + else + gapcnt <= gapcnt + 1; + end if; + + end case; + end if; + end if; + end process; + +end architecture rtl; diff --git a/src/rtl/cv_frontend.vhd b/src/rtl/cv_frontend.vhd index 9eb42c7..27d58a6 100644 --- a/src/rtl/cv_frontend.vhd +++ b/src/rtl/cv_frontend.vhd @@ -31,9 +31,13 @@ use ieee.math_real.all; library work; use work.fdtd_pkg.all; +use work.musical_pkg.all; entity cv_frontend is generic ( + NX : positive := 8; NY : positive := 8; OS : positive := 4; + FS_HZ : positive := 48_000; + CALIBRATED_PITCH : boolean := true; -- false retains explicit raw-coefficient API CV_W : positive := 16; -- ADC sample width (signed) -- pitch CV calibration: note = NOTE_REF + (pitch_cv-CV_OFFSET)*CV_SCALE>>CV_SHIFT CV_OFFSET : integer := 0; @@ -49,7 +53,7 @@ entity cv_frontend is SIGK1 : real := 0.99996875; GAMMA2_MAX : real := 0.451; -- strike / timbre - STRIKE_GAIN : real := 0.9; -- gate strike amplitude + STRIKE_GAIN : real := 0.002; -- gate strike amplitude VEL_STRIKE : natural := 100; -- fixed strike velocity (gate is on/off) ALPHA_MIN : real := 0.0; -- alpha at mod CV = 0 ALPHA_MAX : real := 0.3 -- alpha at mod CV = full scale @@ -57,6 +61,7 @@ entity cv_frontend is port ( clk : in std_logic; rst : in std_logic; + free_mode: in boolean := false; frame : in std_logic; -- per-audio-frame tick pitch_cv : in signed(CV_W-1 downto 0); -- 1V/oct pitch (ADC) gate : in std_logic; -- gate / trigger (comparator) @@ -76,7 +81,7 @@ architecture rtl of cv_frontend is -- note -> gamma2 table (identical to midi_frontend), CFL-clamped type g2_table_t is array (0 to 127) of q123_t; - function build_g2_table return g2_table_t is + function build_g2_table(free: boolean := false) return g2_table_t is variable t : g2_table_t; variable g : real; begin @@ -84,11 +89,13 @@ architecture rtl of cv_frontend is g := GAMMA2_REF * 2.0 ** (real(n - NOTE_REF) / 6.0); if g > GAMMA2_CLAMP then g := GAMMA2_CLAMP; end if; if g < GAMMA2_MIN then g := GAMMA2_MIN; end if; - t(n) := to_q123(g); + if CALIBRATED_PITCH then t(n) := note_gamma2(n,NX,NY,OS,FS_HZ,free); + else t(n) := to_q123(g); end if; end loop; return t; end function; - constant G2_TABLE : g2_table_t := build_g2_table; + constant G2_TABLE : g2_table_t := build_g2_table(false); + constant G2_FREE : g2_table_t := build_g2_table(true); constant STRIKE_Q : q123_t := to_q123(STRIKE_GAIN); constant AMIN_Q : q123_t := to_q123(ALPHA_MIN); @@ -161,7 +168,8 @@ begin -- gate edges: rising = strike, falling = release (natural decay) if g_sync = '1' and g_d = '0' then - coeffs.gamma2 <= G2_TABLE(note_q); + if free_mode then coeffs.gamma2 <= G2_FREE(note_q); + else coeffs.gamma2 <= G2_TABLE(note_q); end if; coeffs.alpha <= alpha_q; coeffs.a0 <= to_q123(A0); coeffs.sigk1 <= to_q123(SIGK1); diff --git a/src/rtl/fx_chain.vhd b/src/rtl/fx_chain.vhd new file mode 100644 index 0000000..edfbf52 --- /dev/null +++ b/src/rtl/fx_chain.vhd @@ -0,0 +1,263 @@ +------------------------------------------------------------------------------- +-- fx_chain.vhd - complete post-mesh RADIAN stereo effects chain. +-- +-- Addresses 10..15 retain the existing preset layout. Improvements here are +-- RTL-only: sample-rate parameter smoothing, click-free effect fades, optional +-- tempo-grid delay encoding, the modulated FDN, and POLISH mastering. +-- +-- ctrl2 raw mode: bit23=0, bits23..8 = delay samples (legacy compatible). +-- ctrl2 sync mode: bit23=1, bits22..16=BPM-60 (60..187), bits15..13=division. +-- ctrl3(6..0) is POLISH (0 = exact mastering-stage bypass). +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.fdtd_pkg.all; +use work.fx_pkg.all; + +entity fx_chain is + generic (FS_HZ : positive := 48_000); + port ( + clk, rst, valid_in : in std_logic; + in_l, in_r : in q123_t; + ctrl0, ctrl1, ctrl2, ctrl3, ctrl4, ctrl5 : in std_logic_vector(23 downto 0); + out_l, out_r : out q123_t; + valid_out : out std_logic + ); +end entity; + +architecture rtl of fx_chain is + constant MAX_DELAY : positive := FS_HZ/2; -- 500 ms physical delay RAM + type quarter_tab_t is array(0 to 127) of natural range 1 to FS_HZ; + function build_quarter_tab return quarter_tab_t is + variable t : quarter_tab_t; + variable bpm,q : integer; + begin + for b in 0 to 127 loop + bpm:=60+b; q:=(FS_HZ*60)/bpm; + if q<1 then q:=1; end if; + if q>FS_HZ then q:=FS_HZ; end if; + t(b):=q; + end loop; + return t; + end function; + constant QUARTER_TAB : quarter_tab_t := build_quarter_tab; + function build_triplet_tab return quarter_tab_t is + variable t : quarter_tab_t; + variable bpm,n : integer; + begin + for b in 0 to 127 loop + bpm:=60+b; n:=(FS_HZ*60)/(3*bpm); + if n<1 then n:=1; end if; + if n>FS_HZ then n:=FS_HZ; end if; + t(b):=n; + end loop; + return t; + end function; + constant TRIPLET_TAB : quarter_tab_t := build_triplet_tab; + + function approach8(cur,tgt : unsigned(7 downto 0); step : natural) return unsigned is + variable c,t : integer; variable n : integer; + begin + c:=to_integer(cur); t:=to_integer(tgt); + if ct then n:=t; end if; + elsif c>t then n:=c-integer(step); if nt then n:=t; end if; + elsif c>t then n:=c-integer(step); if nt then n:=t; end if; + elsif c>t then n:=c-integer(step); if n n:=q/4; -- 1/16 + when 1 => n:=q/2; -- 1/8 + when 2 => n:=(3*q)/4; -- dotted 1/8 + when 3 => n:=q; -- 1/4 + when 4 => n:=(3*q)/2; -- dotted 1/4 + when 5 => n:=2*q; -- 1/2 + when 6 => n:=tr; -- 1/8 triplet + when others => n:=2*tr; -- 1/4 triplet + end case; + if n<1 then n:=1; end if; + if n>MAX_DELAY-1 then n:=MAX_DELAY-1; end if; + return to_unsigned(n,16); + end if; + return unsigned(w(23 downto 8)); + end function; + + signal d_l,d_r,t_l,t_r,c_l,c_r,dl_l,dl_r,rv_l,rv_r,mb_l,mb_r : q123_t := Q123_ZERO; + signal d_v,t_v,c_v,dl_v,rv_v,mb_v : std_logic := '0'; + signal master_en,drive_en,tone_en,chorus_en,delay_en,reverb_en : std_logic; + signal master_run,drive_run,tone_run,chorus_run,delay_run,reverb_run : std_logic; + signal master_prev,first_active : std_logic := '0'; + + signal drive_s : unsigned(7 downto 0) := (others=>'0'); + signal tone_s : unsigned(7 downto 0) := to_unsigned(128,8); + signal ch_rate_s,ch_depth_s,ch_mix_s : unsigned(7 downto 0) := (others=>'0'); + signal delay_time_s : unsigned(15 downto 0) := to_unsigned(1,16); + signal delay_mix_s,delay_fb_s,delay_damp_s : unsigned(7 downto 0) := (others=>'0'); + signal rev_decay_s,rev_damp_s,rev_mix_s,rev_size_s,rev_diff_s : unsigned(7 downto 0) := (others=>'0'); + signal out_trim_s : unsigned(7 downto 0) := x"FF"; + signal master_mix_s : unsigned(7 downto 0) := (others=>'0'); + signal dry_hold_l,dry_hold_r : q123_t := Q123_ZERO; + signal polish_s : unsigned(6 downto 0) := (others=>'0'); + signal drive_eff,tone_eff,ch_rate_eff,ch_depth_eff,ch_mix_eff : unsigned(7 downto 0); + signal delay_time_eff : unsigned(15 downto 0); + signal delay_mix_eff,delay_fb_eff,delay_damp_eff : unsigned(7 downto 0); + signal rev_decay_eff,rev_damp_eff,rev_mix_eff,rev_size_eff,rev_diff_eff,out_trim_eff : unsigned(7 downto 0); + signal polish_eff : unsigned(6 downto 0); + signal delay_ping : std_logic; +begin + master_en<=ctrl0(23); drive_en<=ctrl0(22); tone_en<=ctrl0(21); + chorus_en<=ctrl0(20); delay_en<=ctrl0(19); reverb_en<=ctrl0(18); + delay_ping<=ctrl3(7); + first_active<=master_en and not master_prev; + master_run<='1' when master_en='1' or master_mix_s/=0 else '0'; + drive_eff<=unsigned(ctrl0(17 downto 10)) when first_active='1' and drive_en='1' else drive_s; + tone_eff<=unsigned(ctrl0(9 downto 2)) when first_active='1' and tone_en='1' else tone_s; + ch_rate_eff<=unsigned(ctrl1(23 downto 16)) when first_active='1' else ch_rate_s; + ch_depth_eff<=unsigned(ctrl1(15 downto 8)) when first_active='1' else ch_depth_s; + ch_mix_eff<=unsigned(ctrl1(7 downto 0)) when first_active='1' and chorus_en='1' else ch_mix_s; + delay_time_eff<=delay_target(ctrl2) when first_active='1' else delay_time_s; + delay_mix_eff<=unsigned(ctrl2(7 downto 0)) when first_active='1' and delay_en='1' else delay_mix_s; + delay_fb_eff<=unsigned(ctrl3(23 downto 16)) when first_active='1' else delay_fb_s; + delay_damp_eff<=unsigned(ctrl3(15 downto 8)) when first_active='1' else delay_damp_s; + rev_decay_eff<=unsigned(ctrl4(23 downto 16)) when first_active='1' else rev_decay_s; + rev_damp_eff<=unsigned(ctrl4(15 downto 8)) when first_active='1' else rev_damp_s; + rev_mix_eff<=unsigned(ctrl4(7 downto 0)) when first_active='1' and reverb_en='1' else rev_mix_s; + rev_size_eff<=unsigned(ctrl5(23 downto 16)) when first_active='1' else rev_size_s; + rev_diff_eff<=unsigned(ctrl5(15 downto 8)) when first_active='1' else rev_diff_s; + out_trim_eff<=unsigned(ctrl5(7 downto 0)) when first_active='1' else out_trim_s; + polish_eff<=unsigned(ctrl3(6 downto 0)) when first_active='1' else polish_s; + + drive_run<=master_run when drive_en='1' or drive_s/=0 else '0'; + tone_run<=master_run when tone_en='1' or tone_s/=to_unsigned(128,8) else '0'; + chorus_run<=master_run when chorus_en='1' or ch_mix_s/=0 else '0'; + delay_run<=master_run when delay_en='1' or delay_mix_s/=0 else '0'; + reverb_run<=master_run when reverb_en='1' or rev_mix_s/=0 else '0'; + smooth : process(clk) + variable dt : unsigned(15 downto 0); + variable da,ta,cr,cd,cm,dm,df,dd,rd,rda,rm,rs,rdf,ot,mm : unsigned(7 downto 0); + variable pa : unsigned(6 downto 0); + begin + if rising_edge(clk) then + if rst='1' then + master_prev<='0'; drive_s<=(others=>'0'); tone_s<=to_unsigned(128,8); + ch_rate_s<=(others=>'0'); ch_depth_s<=(others=>'0'); ch_mix_s<=(others=>'0'); + delay_time_s<=to_unsigned(1,16); delay_mix_s<=(others=>'0'); + delay_fb_s<=(others=>'0'); delay_damp_s<=(others=>'0'); + rev_decay_s<=(others=>'0'); rev_damp_s<=(others=>'0'); rev_mix_s<=(others=>'0'); + rev_size_s<=(others=>'0'); rev_diff_s<=(others=>'0'); + out_trim_s<=x"FF"; master_mix_s<=(others=>'0'); + dry_hold_l<=Q123_ZERO; dry_hold_r<=Q123_ZERO; polish_s<=(others=>'0'); + elsif valid_in='1' then + da:=unsigned(ctrl0(17 downto 10)); if drive_en='0' then da:=(others=>'0'); end if; + ta:=unsigned(ctrl0(9 downto 2)); if tone_en='0' then ta:=to_unsigned(128,8); end if; + cr:=unsigned(ctrl1(23 downto 16)); cd:=unsigned(ctrl1(15 downto 8)); + cm:=unsigned(ctrl1(7 downto 0)); if chorus_en='0' then cm:=(others=>'0'); end if; + dt:=delay_target(ctrl2); dm:=unsigned(ctrl2(7 downto 0)); + if delay_en='0' then dm:=(others=>'0'); end if; + df:=unsigned(ctrl3(23 downto 16)); dd:=unsigned(ctrl3(15 downto 8)); + rd:=unsigned(ctrl4(23 downto 16)); rda:=unsigned(ctrl4(15 downto 8)); + rm:=unsigned(ctrl4(7 downto 0)); if reverb_en='0' then rm:=(others=>'0'); end if; + rs:=unsigned(ctrl5(23 downto 16)); rdf:=unsigned(ctrl5(15 downto 8)); + ot:=unsigned(ctrl5(7 downto 0)); pa:=unsigned(ctrl3(6 downto 0)); + if master_en='1' then mm:=x"FF"; else + mm:=(others=>'0'); da:=(others=>'0'); ta:=to_unsigned(128,8); + cm:=(others=>'0'); dm:=(others=>'0'); rm:=(others=>'0'); pa:=(others=>'0'); + end if; + dry_hold_l<=in_l; dry_hold_r<=in_r; + master_mix_s<=approach8(master_mix_s,mm,2); + + -- Initial activation snaps to the preset. Subsequent edits/macro moves + -- slew at audio rate, avoiding zippering without slow startup. + if master_en='1' and master_prev='0' then + drive_s<=da; tone_s<=ta; ch_rate_s<=cr; ch_depth_s<=cd; ch_mix_s<=cm; + delay_time_s<=dt; delay_mix_s<=dm; delay_fb_s<=df; delay_damp_s<=dd; + rev_decay_s<=rd; rev_damp_s<=rda; rev_mix_s<=rm; rev_size_s<=rs; rev_diff_s<=rdf; + out_trim_s<=ot; polish_s<=pa; + else + drive_s<=approach8(drive_s,da,2); tone_s<=approach8(tone_s,ta,2); + ch_rate_s<=approach8(ch_rate_s,cr,1); ch_depth_s<=approach8(ch_depth_s,cd,1); + ch_mix_s<=approach8(ch_mix_s,cm,2); + delay_time_s<=approach16(delay_time_s,dt,1); delay_mix_s<=approach8(delay_mix_s,dm,2); + delay_fb_s<=approach8(delay_fb_s,df,1); delay_damp_s<=approach8(delay_damp_s,dd,1); + rev_decay_s<=approach8(rev_decay_s,rd,1); rev_damp_s<=approach8(rev_damp_s,rda,1); + rev_mix_s<=approach8(rev_mix_s,rm,2); rev_size_s<=approach8(rev_size_s,rs,1); + rev_diff_s<=approach8(rev_diff_s,rdf,1); out_trim_s<=approach8(out_trim_s,ot,2); + polish_s<=approach7(polish_s,pa,1); + end if; + master_prev<=master_en; + end if; + end if; + end process; + drive_i : entity work.fx_drive + port map(clk=>clk,rst=>rst,valid_in=>valid_in,enable=>drive_run,amount=>drive_eff, + in_l=>in_l,in_r=>in_r,out_l=>d_l,out_r=>d_r,valid_out=>d_v); + tone_i : entity work.fx_tone + port map(clk=>clk,rst=>rst,valid_in=>d_v,enable=>tone_run,tone=>tone_eff, + in_l=>d_l,in_r=>d_r,out_l=>t_l,out_r=>t_r,valid_out=>t_v); + chorus_i : entity work.fx_chorus + port map(clk=>clk,rst=>rst,valid_in=>t_v,enable=>chorus_run, + rate=>ch_rate_eff,depth=>ch_depth_eff,mix=>ch_mix_eff, + in_l=>t_l,in_r=>t_r,out_l=>c_l,out_r=>c_r,valid_out=>c_v); + delay_i : entity work.fx_delay + generic map(MAX_DELAY_SAMPLES=>MAX_DELAY) + port map(clk=>clk,rst=>rst,valid_in=>c_v,enable=>delay_run, + time_samples=>delay_time_eff,feedback=>delay_fb_eff,damping=>delay_damp_eff, + pingpong=>delay_ping,mix=>delay_mix_eff, + in_l=>c_l,in_r=>c_r,out_l=>dl_l,out_r=>dl_r,valid_out=>dl_v); + reverb_i : entity work.fx_fdn_reverb + port map(clk=>clk,rst=>rst,valid_in=>dl_v,enable=>reverb_run, + decay=>rev_decay_eff,damping=>rev_damp_eff,size=>rev_size_eff,diffusion=>rev_diff_eff, + mix=>rev_mix_eff,in_l=>dl_l,in_r=>dl_r,out_l=>rv_l,out_r=>rv_r,valid_out=>rv_v); + master_i : entity work.fx_master_bus + port map(clk=>clk,rst=>rst,valid_in=>rv_v,enable=>master_run,amount=>polish_eff, + in_l=>rv_l,in_r=>rv_r,out_l=>mb_l,out_r=>mb_r,valid_out=>mb_v); + + finish : process(clk) + variable yl,yr : q123_t; + begin + if rising_edge(clk) then + valid_out<='0'; + if rst='1' then out_l<=Q123_ZERO; out_r<=Q123_ZERO; + elsif mb_v='1' then + if master_run='1' then + if out_trim_eff=x"FF" then yl:=mb_l;yr:=mb_r; + else yl:=scale_u8(mb_l,out_trim_eff);yr:=scale_u8(mb_r,out_trim_eff);end if; + yl:=soft_clip_acc(to_acc(yl)); yr:=soft_clip_acc(to_acc(yr)); + else yl:=mb_l;yr:=mb_r; end if; + if master_mix_s=0 then + out_l<=dry_hold_l; out_r<=dry_hold_r; + elsif master_mix_s=x"FF" then + out_l<=yl; out_r<=yr; + else + out_l<=mix_u8(dry_hold_l,yl,master_mix_s); + out_r<=mix_u8(dry_hold_r,yr,master_mix_s); + end if; + valid_out<='1'; + end if; + end if; + end process; +end architecture rtl; diff --git a/src/rtl/fx_chorus.vhd b/src/rtl/fx_chorus.vhd new file mode 100644 index 0000000..f08b337 --- /dev/null +++ b/src/rtl/fx_chorus.vhd @@ -0,0 +1,121 @@ +------------------------------------------------------------------------------- +-- fx_chorus.vhd - stereo modulated short delay using single-port BRAMs. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.fdtd_pkg.all; +use work.fx_pkg.all; + +entity fx_chorus is + generic (MEM_LEN : positive := 2048); + port ( + clk, rst, valid_in : in std_logic; + enable : in std_logic; + rate, depth, mix : in unsigned(7 downto 0); + in_l, in_r : in q123_t; + out_l, out_r : out q123_t; + valid_out : out std_logic + ); +end entity; + +architecture rtl of fx_chorus is + type ram_t is array (0 to MEM_LEN-1) of q15_t; + signal ram_l, ram_r : ram_t := (others => (others=>'0')); + signal ram_q_l, ram_q_r, ram_w_l, ram_w_r : q15_t := (others=>'0'); + signal mem_addr_l, mem_addr_r : integer range 0 to MEM_LEN-1 := 0; + signal mem_we : std_logic := '0'; + signal wr_ptr : integer range 0 to MEM_LEN-1 := 0; + signal phase : unsigned(23 downto 0) := (others=>'0'); + type state_t is (IDLE, WAIT1, WAIT2, WRITE_BACK); + signal state : state_t := IDLE; + signal dry_l, dry_r, wet_l, wet_r : q123_t := Q123_ZERO; + signal mix_q : unsigned(7 downto 0) := (others=>'0'); + signal en_q : std_logic := '0'; + + function tri8(p : unsigned(23 downto 0)) return unsigned is + variable v : unsigned(7 downto 0); + begin + if p(23)='0' then v:=p(22 downto 15); else v:=not p(22 downto 15); end if; + return v; + end function; + + function mul_u8_shiftadd(a,b : unsigned(7 downto 0)) return unsigned is + variable sum : unsigned(15 downto 0) := (others=>'0'); + variable aw : unsigned(15 downto 0) := resize(a,16); + begin + for i in 0 to 7 loop + if b(i)='1' then sum:=sum+shift_left(aw,i); end if; + end loop; + return sum; + end function; + + function sub_wrap(p, d : integer) return integer is + variable x : integer; + begin + x := p-d; + if x < 0 then x := x+MEM_LEN; end if; + return x; + end function; +begin + mem : process(clk) + begin + if rising_edge(clk) then + ram_q_l <= ram_l(mem_addr_l); ram_q_r <= ram_r(mem_addr_r); + if mem_we='1' then + ram_l(mem_addr_l) <= ram_w_l; ram_r(mem_addr_r) <= ram_w_r; + end if; + end if; + end process; + control : process(clk) + variable ph_r : unsigned(23 downto 0); + variable prod_l, prod_r, delay_l, delay_r, step : integer; + variable mul_l, mul_r : unsigned(15 downto 0); + begin + if rising_edge(clk) then + valid_out<='0'; + if rst='1' then + state<=IDLE; mem_we<='0'; wr_ptr<=0; phase<=(others=>'0'); + mem_addr_l<=0; mem_addr_r<=0; dry_l<=Q123_ZERO; dry_r<=Q123_ZERO; + wet_l<=Q123_ZERO; wet_r<=Q123_ZERO; out_l<=Q123_ZERO; out_r<=Q123_ZERO; + else + case state is + when IDLE => + mem_we<='0'; + if valid_in='1' then + dry_l<=in_l; dry_r<=in_r; mix_q<=mix; en_q<=enable; + ph_r:=phase+to_unsigned(2**22,24); + mul_l:=mul_u8_shiftadd(depth,tri8(phase)); + mul_r:=mul_u8_shiftadd(depth,tri8(ph_r)); + prod_l:=to_integer(mul_l)+to_integer(mul_l)+to_integer(mul_l); + prod_r:=to_integer(mul_r)+to_integer(mul_r)+to_integer(mul_r); + delay_l:=240+prod_l/256; delay_r:=240+prod_r/256; + if delay_l>MEM_LEN-1 then delay_l:=MEM_LEN-1; end if; + if delay_r>MEM_LEN-1 then delay_r:=MEM_LEN-1; end if; + mem_addr_l<=sub_wrap(wr_ptr,delay_l); + mem_addr_r<=sub_wrap(wr_ptr,delay_r); + step:=64+8*to_integer(rate); + phase<=phase+to_unsigned(step,24); + state<=WAIT1; + end if; + when WAIT1 => state<=WAIT2; + when WAIT2 => + wet_l<=from_q15(ram_q_l); wet_r<=from_q15(ram_q_r); + mem_addr_l<=wr_ptr; mem_addr_r<=wr_ptr; + ram_w_l<=to_q15(dry_l); ram_w_r<=to_q15(dry_r); mem_we<='1'; + state<=WRITE_BACK; + when WRITE_BACK => + mem_we<='0'; + if en_q='1' then + out_l<=mix_u8(dry_l,wet_l,mix_q); out_r<=mix_u8(dry_r,wet_r,mix_q); + else + out_l<=dry_l; out_r<=dry_r; + end if; + if wr_ptr=MEM_LEN-1 then wr_ptr<=0; else wr_ptr<=wr_ptr+1; end if; + valid_out<='1'; state<=IDLE; + end case; + end if; + end if; + end process; +end architecture; diff --git a/src/rtl/fx_delay.vhd b/src/rtl/fx_delay.vhd new file mode 100644 index 0000000..a271044 --- /dev/null +++ b/src/rtl/fx_delay.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------- +-- fx_delay.vhd - stereo/ping-pong feedback delay using one single-port BRAM. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.fdtd_pkg.all; +use work.fx_pkg.all; + +entity fx_delay is + generic (MAX_DELAY_SAMPLES : positive := 24000); + port ( + clk, rst, valid_in : in std_logic; + enable : in std_logic; + time_samples : in unsigned(15 downto 0); + feedback, damping : in unsigned(7 downto 0); + pingpong : in std_logic; + mix : in unsigned(7 downto 0); + in_l, in_r : in q123_t; + out_l, out_r : out q123_t; + valid_out : out std_logic + ); +end entity; + +architecture rtl of fx_delay is + type ram_t is array (0 to MAX_DELAY_SAMPLES-1) of std_logic_vector(31 downto 0); + signal ram : ram_t := (others => (others=>'0')); + signal ram_q, ram_wdata : std_logic_vector(31 downto 0) := (others=>'0'); + signal mem_addr : integer range 0 to MAX_DELAY_SAMPLES-1 := 0; + signal mem_we : std_logic := '0'; + signal wr_ptr : integer range 0 to MAX_DELAY_SAMPLES-1 := 0; + type state_t is (IDLE, WAIT1, WAIT2, WRITE_BACK); + signal state : state_t := IDLE; + signal dry_l, dry_r, wet_l, wet_r : q123_t := Q123_ZERO; + signal lp_l, lp_r : q123_t := Q123_ZERO; + signal fb_q, damp_q, mix_q : unsigned(7 downto 0) := (others=>'0'); + signal ping_q, en_q : std_logic := '0'; + + function sub_wrap(p, d : integer) return integer is + variable x : integer; + begin + x:=p-d; + if x<0 then x:=x+MAX_DELAY_SAMPLES; end if; + return x; + end function; +begin + mem : process(clk) + begin + if rising_edge(clk) then + ram_q<=ram(mem_addr); + if mem_we='1' then ram(mem_addr)<=ram_wdata; end if; + end if; + end process; + + control : process(clk) + variable d : integer; + variable del_l,del_r,dlpf_l,dlpf_r,feed_l,feed_r,write_l,write_r:q123_t; + variable lpacc_l,lpacc_r:acc_t; + variable smooth:unsigned(7 downto 0); + begin + if rising_edge(clk) then + valid_out<='0'; + if rst='1' then + state<=IDLE; mem_we<='0'; mem_addr<=0; wr_ptr<=0; + dry_l<=Q123_ZERO; dry_r<=Q123_ZERO; wet_l<=Q123_ZERO; wet_r<=Q123_ZERO; + lp_l<=Q123_ZERO; lp_r<=Q123_ZERO; out_l<=Q123_ZERO; out_r<=Q123_ZERO; + else + case state is + when IDLE => + mem_we<='0'; + if valid_in='1' then + dry_l<=in_l; dry_r<=in_r; fb_q<=feedback; damp_q<=damping; + mix_q<=mix; ping_q<=pingpong; en_q<=enable; + d:=to_integer(time_samples); + if d<1 then d:=1; end if; + if d>MAX_DELAY_SAMPLES-1 then d:=MAX_DELAY_SAMPLES-1; end if; + mem_addr<=sub_wrap(wr_ptr,d); + state<=WAIT1; + end if; + when WAIT1 => state<=WAIT2; + when WAIT2 => + del_l:=from_q15(signed(ram_q(31 downto 16))); + del_r:=from_q15(signed(ram_q(15 downto 0))); + wet_l<=del_l; wet_r<=del_r; + smooth:=to_unsigned(255-to_integer(damp_q),8); + lpacc_l:=to_acc(lp_l)+scale_acc_u8(to_acc(del_l)-to_acc(lp_l),smooth); + lpacc_r:=to_acc(lp_r)+scale_acc_u8(to_acc(del_r)-to_acc(lp_r),smooth); + dlpf_l:=sat_store(lpacc_l); dlpf_r:=sat_store(lpacc_r); + if en_q='1' then + lp_l<=dlpf_l; lp_r<=dlpf_r; + if ping_q='1' then + feed_l:=scale_u8(dlpf_r,fb_q); feed_r:=scale_u8(dlpf_l,fb_q); + else + feed_l:=scale_u8(dlpf_l,fb_q); feed_r:=scale_u8(dlpf_r,fb_q); + end if; + write_l:=sat_store(to_acc(dry_l)+to_acc(feed_l)); + write_r:=sat_store(to_acc(dry_r)+to_acc(feed_r)); + else + write_l:=dry_l; write_r:=dry_r; + end if; + ram_wdata<=std_logic_vector(to_q15(write_l)) & std_logic_vector(to_q15(write_r)); + mem_addr<=wr_ptr; mem_we<='1'; state<=WRITE_BACK; + when WRITE_BACK => + mem_we<='0'; + if en_q='1' then + out_l<=mix_u8(dry_l,wet_l,mix_q); out_r<=mix_u8(dry_r,wet_r,mix_q); + else out_l<=dry_l; out_r<=dry_r; end if; + if wr_ptr=MAX_DELAY_SAMPLES-1 then wr_ptr<=0; else wr_ptr<=wr_ptr+1; end if; + valid_out<='1'; state<=IDLE; + end case; + end if; + end if; + end process; +end architecture; diff --git a/src/rtl/fx_drive.vhd b/src/rtl/fx_drive.vhd new file mode 100644 index 0000000..5e2e332 --- /dev/null +++ b/src/rtl/fx_drive.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- fx_drive.vhd - sample-rate stereo pre-drive + soft saturation. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.fdtd_pkg.all; +use work.fx_pkg.all; + +entity fx_drive is + port ( + clk, rst, valid_in : in std_logic; + enable : in std_logic; + amount : in unsigned(7 downto 0); + in_l, in_r : in q123_t; + out_l, out_r : out q123_t; + valid_out : out std_logic + ); +end entity; + +architecture rtl of fx_drive is +begin + process(clk) + variable pre_l, pre_r : acc_t; + variable wet_l, wet_r : q123_t; + begin + if rising_edge(clk) then + valid_out <= '0'; + if rst='1' then + out_l <= Q123_ZERO; out_r <= Q123_ZERO; + elsif valid_in='1' then + if enable='1' and amount /= 0 then + -- Pre-gain ranges from 1x to just under 3x. + pre_l := to_acc(in_l) + shift_left(scale_acc_u8(to_acc(in_l), amount), 1); + pre_r := to_acc(in_r) + shift_left(scale_acc_u8(to_acc(in_r), amount), 1); + wet_l := soft_clip_acc(pre_l); + wet_r := soft_clip_acc(pre_r); + out_l <= mix_u8(in_l, wet_l, amount); + out_r <= mix_u8(in_r, wet_r, amount); + else + out_l <= in_l; out_r <= in_r; + end if; + valid_out <= '1'; + end if; + end if; + end process; +end architecture; diff --git a/src/rtl/fx_fdn_reverb.vhd b/src/rtl/fx_fdn_reverb.vhd new file mode 100644 index 0000000..0b5f3b3 --- /dev/null +++ b/src/rtl/fx_fdn_reverb.vhd @@ -0,0 +1,230 @@ +------------------------------------------------------------------------------- +-- fx_fdn_reverb.vhd - eight-line damped FDN with one shared control multiplier. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.fdtd_pkg.all; +use work.fx_pkg.all; + +entity fx_fdn_reverb is + port ( + clk, rst, valid_in : in std_logic; + enable : in std_logic; + decay, damping : in unsigned(7 downto 0); + size, diffusion : in unsigned(7 downto 0); + mix : in unsigned(7 downto 0); + in_l, in_r : in q123_t; + out_l, out_r : out q123_t; + valid_out : out std_logic + ); +end entity; + +architecture rtl of fx_fdn_reverb is + constant L0 : positive := 421; constant L1 : positive := 547; + constant L2 : positive := 631; constant L3 : positive := 733; + constant L4 : positive := 887; constant L5 : positive := 953; + constant L6 : positive := 1061; constant L7 : positive := 1153; + type r0_t is array(0 to L0-1) of q15_t; type r1_t is array(0 to L1-1) of q15_t; + type r2_t is array(0 to L2-1) of q15_t; type r3_t is array(0 to L3-1) of q15_t; + type r4_t is array(0 to L4-1) of q15_t; type r5_t is array(0 to L5-1) of q15_t; + type r6_t is array(0 to L6-1) of q15_t; type r7_t is array(0 to L7-1) of q15_t; + signal m0:r0_t := (others=>(others=>'0')); signal m1:r1_t := (others=>(others=>'0')); + signal m2:r2_t := (others=>(others=>'0')); signal m3:r3_t := (others=>(others=>'0')); + signal m4:r4_t := (others=>(others=>'0')); signal m5:r5_t := (others=>(others=>'0')); + signal m6:r6_t := (others=>(others=>'0')); signal m7:r7_t := (others=>(others=>'0')); + signal p0:integer range 0 to L0-1:=0; signal p1:integer range 0 to L1-1:=0; + signal p2:integer range 0 to L2-1:=0; signal p3:integer range 0 to L3-1:=0; + signal p4:integer range 0 to L4-1:=0; signal p5:integer range 0 to L5-1:=0; + signal p6:integer range 0 to L6-1:=0; signal p7:integer range 0 to L7-1:=0; + signal mod_phase : unsigned(15 downto 0) := (others=>'0'); + + type qvec_t is array(0 to 7) of q123_t; + signal q, lp, damped, matrix, mixed : qvec_t := (others=>Q123_ZERO); + signal dry_l,dry_r,mono_q,wet_l_q,wet_r_q : q123_t := Q123_ZERO; + signal decay_q,damp_q,size_q,diff_q,mix_q : unsigned(7 downto 0):=(others=>'0'); + signal en_q : std_logic := '0'; + signal idx : integer range 0 to 7 := 0; + signal ram_we : std_logic := '0'; + signal ram_wline : integer range 0 to 7 := 0; + signal ram_waddr : integer range 0 to L7-1 := 0; + signal ram_wdata : q15_t := (others=>'0'); + type state_t is (IDLE,DAMP,MATRIX_STEP,DIFFUSE,DECAY_STEP,OUT_LEFT,OUT_RIGHT); + signal state : state_t := IDLE; + + -- One 24x9 multiplier is time-shared across damping, diffusion, decay and mix. + signal mul_a : q123_t := Q123_ZERO; + signal mul_g : unsigned(7 downto 0) := (others=>'0'); + signal mul_p : signed(32 downto 0) := (others=>'0'); + signal mul_scaled : q123_t := Q123_ZERO; + + function mod_offset(p : unsigned(15 downto 0); line : natural; + depth : unsigned(7 downto 0)) return integer is + variable o : integer; + begin + if depth < to_unsigned(64,8) then return 0; end if; + o := ((to_integer(p(15 downto 13)) + integer(line)*3) mod 8) - 4; + if depth < to_unsigned(160,8) then o:=o/2; end if; + return o; + end function; + + function effective_len(base : positive; s : unsigned(7 downto 0); + mo : integer) return positive is + variable e : integer; + begin + case s(7 downto 6) is + when "00" => e:=base/2; + when "01" => e:=(base*5)/8; + when "10" => e:=(base*3)/4; + when others => e:=base; + end case; + e:=e+mo; + if e<2 then e:=2; end if; + if e>base then e:=base; end if; + return positive(e); + end function; +begin + mul_p <= mul_a * signed('0' & std_logic_vector(mul_g)); + mul_scaled <= sat_store(resize(shift_right(resize(mul_p,ACC_BITS) + + to_signed(128,ACC_BITS),8),ACC_BITS)); + + -- One process per line keeps the intended single-port RAM template obvious + -- to GHDL/Vivado while a shared write selector services the time-mux FDN. + mem0:process(clk) begin if rising_edge(clk) then q(0)<=from_q15(m0(p0)); if ram_we='1' and ram_wline=0 then m0(ram_waddr)<=ram_wdata; end if; end if; end process; + mem1:process(clk) begin if rising_edge(clk) then q(1)<=from_q15(m1(p1)); if ram_we='1' and ram_wline=1 then m1(ram_waddr)<=ram_wdata; end if; end if; end process; + mem2:process(clk) begin if rising_edge(clk) then q(2)<=from_q15(m2(p2)); if ram_we='1' and ram_wline=2 then m2(ram_waddr)<=ram_wdata; end if; end if; end process; + mem3:process(clk) begin if rising_edge(clk) then q(3)<=from_q15(m3(p3)); if ram_we='1' and ram_wline=3 then m3(ram_waddr)<=ram_wdata; end if; end if; end process; + mem4:process(clk) begin if rising_edge(clk) then q(4)<=from_q15(m4(p4)); if ram_we='1' and ram_wline=4 then m4(ram_waddr)<=ram_wdata; end if; end if; end process; + mem5:process(clk) begin if rising_edge(clk) then q(5)<=from_q15(m5(p5)); if ram_we='1' and ram_wline=5 then m5(ram_waddr)<=ram_wdata; end if; end if; end process; + mem6:process(clk) begin if rising_edge(clk) then q(6)<=from_q15(m6(p6)); if ram_we='1' and ram_wline=6 then m6(ram_waddr)<=ram_wdata; end if; end if; end process; + mem7:process(clk) begin if rising_edge(clk) then q(7)<=from_q15(m7(p7)); if ram_we='1' and ram_wline=7 then m7(ram_waddr)<=ram_wdata; end if; end if; end process; + + -- Select the shared multiplier operands from the current micro-operation. + mul_select : process(all) + variable delta : acc_t; + begin + mul_a <= Q123_ZERO; mul_g <= (others=>'0'); + case state is + when DAMP => + delta:=to_acc(q(idx))-to_acc(lp(idx)); + mul_a<=sat_store(delta); mul_g<=to_unsigned(255-to_integer(damp_q),8); + when DIFFUSE => + delta:=to_acc(matrix(idx))-to_acc(damped(idx)); + mul_a<=sat_store(delta); mul_g<=diff_q; + when DECAY_STEP => mul_a<=mixed(idx); mul_g<=decay_q; + when OUT_LEFT => + delta:=to_acc(wet_l_q)-to_acc(dry_l); + mul_a<=sat_store(delta); mul_g<=mix_q; + when OUT_RIGHT => + delta:=to_acc(wet_r_q)-to_acc(dry_r); + mul_a<=sat_store(delta); mul_g<=mix_q; + when others => null; + end case; + end process; + control : process(clk) + variable h0,h1,h2,h3,h4,h5,h6,h7 : acc_t; + variable newv : q123_t; + variable fb, inj, wr, wetacc : acc_t; + variable e : positive; + begin + if rising_edge(clk) then + valid_out <= '0'; + ram_we <= '0'; + if rst='1' then + state<=IDLE; idx<=0; en_q<='0'; + p0<=0;p1<=0;p2<=0;p3<=0;p4<=0;p5<=0;p6<=0;p7<=0; + mod_phase<=(others=>'0'); + lp<=(others=>Q123_ZERO); damped<=(others=>Q123_ZERO); + matrix<=(others=>Q123_ZERO); mixed<=(others=>Q123_ZERO); + dry_l<=Q123_ZERO; dry_r<=Q123_ZERO; mono_q<=Q123_ZERO; + wet_l_q<=Q123_ZERO; wet_r_q<=Q123_ZERO; + out_l<=Q123_ZERO; out_r<=Q123_ZERO; + else + case state is + when IDLE => + if valid_in='1' then + dry_l<=in_l; dry_r<=in_r; + mono_q<=sat_store(shift_right(to_acc(in_l)+to_acc(in_r),1)); + decay_q<=decay; damp_q<=damping; size_q<=size; + diff_q<=diffusion; mix_q<=mix; en_q<=enable; + -- ~0.73 Hz base modulation at 48 kHz; per-line phase offsets + -- decorrelate the FDN without another delay RAM or multiplier. + mod_phase<=mod_phase+1; + idx<=0; state<=DAMP; + end if; + when DAMP => + newv:=sat_store(to_acc(lp(idx))+to_acc(mul_scaled)); + damped(idx)<=newv; lp(idx)<=newv; + if idx=7 then idx<=0; state<=MATRIX_STEP; else idx<=idx+1; end if; + + when MATRIX_STEP => + h0:=to_acc(damped(0))+to_acc(damped(1))+to_acc(damped(2))+to_acc(damped(3))+ + to_acc(damped(4))+to_acc(damped(5))+to_acc(damped(6))+to_acc(damped(7)); + h1:=to_acc(damped(0))-to_acc(damped(1))+to_acc(damped(2))-to_acc(damped(3))+ + to_acc(damped(4))-to_acc(damped(5))+to_acc(damped(6))-to_acc(damped(7)); + h2:=to_acc(damped(0))+to_acc(damped(1))-to_acc(damped(2))-to_acc(damped(3))+ + to_acc(damped(4))+to_acc(damped(5))-to_acc(damped(6))-to_acc(damped(7)); + h3:=to_acc(damped(0))-to_acc(damped(1))-to_acc(damped(2))+to_acc(damped(3))+ + to_acc(damped(4))-to_acc(damped(5))-to_acc(damped(6))+to_acc(damped(7)); + h4:=to_acc(damped(0))+to_acc(damped(1))+to_acc(damped(2))+to_acc(damped(3))- + to_acc(damped(4))-to_acc(damped(5))-to_acc(damped(6))-to_acc(damped(7)); + h5:=to_acc(damped(0))-to_acc(damped(1))+to_acc(damped(2))-to_acc(damped(3))- + to_acc(damped(4))+to_acc(damped(5))-to_acc(damped(6))+to_acc(damped(7)); + h6:=to_acc(damped(0))+to_acc(damped(1))-to_acc(damped(2))-to_acc(damped(3))- + to_acc(damped(4))-to_acc(damped(5))+to_acc(damped(6))+to_acc(damped(7)); + h7:=to_acc(damped(0))-to_acc(damped(1))-to_acc(damped(2))+to_acc(damped(3))- + to_acc(damped(4))+to_acc(damped(5))+to_acc(damped(6))-to_acc(damped(7)); + matrix(0)<=sat_store(shift_right(h0,3)); matrix(1)<=sat_store(shift_right(h1,3)); + matrix(2)<=sat_store(shift_right(h2,3)); matrix(3)<=sat_store(shift_right(h3,3)); + matrix(4)<=sat_store(shift_right(h4,3)); matrix(5)<=sat_store(shift_right(h5,3)); + matrix(6)<=sat_store(shift_right(h6,3)); matrix(7)<=sat_store(shift_right(h7,3)); + wetacc:=to_acc(damped(0))+to_acc(damped(2))+to_acc(damped(5))+to_acc(damped(7)); + wet_l_q<=sat_store(shift_right(wetacc,2)); + wetacc:=to_acc(damped(1))+to_acc(damped(3))+to_acc(damped(4))+to_acc(damped(6)); + wet_r_q<=sat_store(shift_right(wetacc,2)); + idx<=0; state<=DIFFUSE; + + when DIFFUSE => + newv:=sat_store(to_acc(damped(idx))+to_acc(mul_scaled)); + mixed(idx)<=newv; + if idx=7 then idx<=0; state<=DECAY_STEP; else idx<=idx+1; end if; + + when DECAY_STEP => + fb:=shift_right(to_acc(mixed(idx))+to_acc(mul_scaled),1); + if en_q='1' then inj:=shift_right(to_acc(mono_q),1); else inj:=(others=>'0'); end if; + if (idx mod 2)=0 then wr:=fb+inj; else wr:=fb-inj; end if; + ram_wline<=idx; ram_wdata<=to_q15(sat_store(wr)); ram_we<='1'; + case idx is + when 0 => ram_waddr<=p0; e:=effective_len(L0,size_q,mod_offset(mod_phase,0,diff_q)); + if p0>=e-1 then p0<=0; else p0<=p0+1; end if; + when 1 => ram_waddr<=p1; e:=effective_len(L1,size_q,mod_offset(mod_phase,1,diff_q)); + if p1>=e-1 then p1<=0; else p1<=p1+1; end if; + when 2 => ram_waddr<=p2; e:=effective_len(L2,size_q,mod_offset(mod_phase,2,diff_q)); + if p2>=e-1 then p2<=0; else p2<=p2+1; end if; + when 3 => ram_waddr<=p3; e:=effective_len(L3,size_q,mod_offset(mod_phase,3,diff_q)); + if p3>=e-1 then p3<=0; else p3<=p3+1; end if; + when 4 => ram_waddr<=p4; e:=effective_len(L4,size_q,mod_offset(mod_phase,4,diff_q)); + if p4>=e-1 then p4<=0; else p4<=p4+1; end if; + when 5 => ram_waddr<=p5; e:=effective_len(L5,size_q,mod_offset(mod_phase,5,diff_q)); + if p5>=e-1 then p5<=0; else p5<=p5+1; end if; + when 6 => ram_waddr<=p6; e:=effective_len(L6,size_q,mod_offset(mod_phase,6,diff_q)); + if p6>=e-1 then p6<=0; else p6<=p6+1; end if; + when others => ram_waddr<=p7; e:=effective_len(L7,size_q,mod_offset(mod_phase,7,diff_q)); + if p7>=e-1 then p7<=0; else p7<=p7+1; end if; + end case; + if idx=7 then state<=OUT_LEFT; else idx<=idx+1; end if; + + when OUT_LEFT => + if en_q='1' then out_l<=sat_store(to_acc(dry_l)+to_acc(mul_scaled)); + else out_l<=dry_l; end if; + state<=OUT_RIGHT; + when OUT_RIGHT => + if en_q='1' then out_r<=sat_store(to_acc(dry_r)+to_acc(mul_scaled)); + else out_r<=dry_r; end if; + valid_out<='1'; state<=IDLE; + end case; + end if; + end if; + end process; +end architecture; diff --git a/src/rtl/fx_master_bus.vhd b/src/rtl/fx_master_bus.vhd new file mode 100644 index 0000000..1b66324 --- /dev/null +++ b/src/rtl/fx_master_bus.vhd @@ -0,0 +1,219 @@ +------------------------------------------------------------------------------- +-- fx_master_bus.vhd - resource-light post-FX mastering/polish stage. +-- +-- POLISH is ctrl3(6 downto 0): 0 is bit-exact bypass; increasing values add +-- subsonic filtering, a fixed production-style EQ curve, low-mono/high-width +-- stereo shaping, linked compression/makeup, and soft limiting. +-- +-- Filters use 24/29-bit shift-add arithmetic. A single 24x11 multiplier is +-- time-shared between the left/right compressor gain operations. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.fdtd_pkg.all; +use work.fx_pkg.all; + +entity fx_master_bus is + port ( + clk, rst, valid_in : in std_logic; + enable : in std_logic; + amount : in unsigned(6 downto 0); + in_l, in_r : in q123_t; + out_l, out_r : out q123_t; + valid_out : out std_logic + ); +end entity fx_master_bus; + +architecture rtl of fx_master_bus is + subtype wide_t is signed(28 downto 0); -- Q*.23, ample headroom for bus sums + type state_t is (IDLE, GAIN_L, GAIN_R, OUTPUT); + signal state : state_t := IDLE; + + signal hp_lp_l, hp_lp_r : q123_t := Q123_ZERO; + signal low_lp_l, low_lp_r : q123_t := Q123_ZERO; + signal mid_lp_l, mid_lp_r : q123_t := Q123_ZERO; + signal side_lp : wide_t := (others=>'0'); + + signal pre_l, pre_r : q123_t := Q123_ZERO; + signal comp_l : acc_t := (others=>'0'); + signal env_q : integer range 0 to 8388608 := 0; + signal slow_env_q : integer range 0 to 8388608 := 0; + signal gain_q : integer range 0 to 2047 := 256; + signal mul_a : q123_t := Q123_ZERO; + signal mul_g : unsigned(10 downto 0) := to_unsigned(256,11); + signal mul_p : signed(35 downto 0) := (others=>'0'); + signal mul_scaled : acc_t := (others=>'0'); + + function widen(x : q123_t) return wide_t is + begin + return resize(x,wide_t'length); + end function; + + function lp_step(s, x : q123_t; sh : natural) return q123_t is + variable d,n : signed(24 downto 0); + begin + d:=resize(x,25)-resize(s,25); + n:=resize(s,25)+shift_right(d,sh); + return sat_q123(n); + end function; + + function sub_q(a,b : q123_t) return q123_t is + variable d : signed(24 downto 0); + begin + d:=resize(a,25)-resize(b,25); + return sat_q123(d); + end function; + + function abs_q(x : q123_t) return integer is + variable v : integer; + begin + v:=to_integer(x); + if v<0 then return -v; else return v; end if; + end function; + + function target_gain(env, amt : integer) return integer is + variable base, floor_g, thr, red, g : integer; + begin + if amt < 32 then + base:=320; floor_g:=240; thr:=1600000; + if env<=thr then return base; end if; + red:=(env-thr)/16384; + elsif amt < 80 then + base:=512; floor_g:=216; thr:=1000000; + if env<=thr then return base; end if; + red:=(env-thr)/8192; + else + base:=768; floor_g:=192; thr:=700000; + if env<=thr then return base; end if; + red:=(env-thr)/4096; + end if; + g:=base-red; if g mul_a <= pre_l; + when GAIN_R => mul_a <= pre_r; + when others => null; + end case; + end process; + + process(clk) + variable hpnl,hpnr,lowl,lowr,midl,midr,hpl,hpr : q123_t; + variable bandl,bandr,highl,highr,eql,eqr : wide_t; + variable m,s,slp,sout,wl,wr : wide_t; + variable peak_i,env_i,slow_i,det_i,tgt,delta,amt_i : integer; + begin + if rising_edge(clk) then + valid_out<='0'; + if rst='1' then + state<=IDLE; + hp_lp_l<=Q123_ZERO; hp_lp_r<=Q123_ZERO; + low_lp_l<=Q123_ZERO; low_lp_r<=Q123_ZERO; + mid_lp_l<=Q123_ZERO; mid_lp_r<=Q123_ZERO; + side_lp<=(others=>'0'); pre_l<=Q123_ZERO; pre_r<=Q123_ZERO; + comp_l<=(others=>'0'); env_q<=0; slow_env_q<=0; gain_q<=256; + out_l<=Q123_ZERO; out_r<=Q123_ZERO; + else + case state is + when IDLE => + if valid_in='1' then + if enable='0' or amount=0 then + out_l<=in_l; out_r<=in_r; valid_out<='1'; + else + amt_i:=to_integer(amount); + + -- 1/256 pole ~= 30 Hz at 48 kHz. + hpnl:=lp_step(hp_lp_l,in_l,8); hpnr:=lp_step(hp_lp_r,in_r,8); + hp_lp_l<=hpnl; hp_lp_r<=hpnr; + hpl:=sub_q(in_l,hpnl); hpr:=sub_q(in_r,hpnr); + + -- Approx. 120 Hz and 480 Hz production-EQ split points. + lowl:=lp_step(low_lp_l,hpl,6); lowr:=lp_step(low_lp_r,hpr,6); + midl:=lp_step(mid_lp_l,hpl,4); midr:=lp_step(mid_lp_r,hpr,4); + low_lp_l<=lowl; low_lp_r<=lowr; mid_lp_l<=midl; mid_lp_r<=midr; + bandl:=widen(midl)-widen(lowl); bandr:=widen(midr)-widen(lowr); + highl:=widen(hpl)-widen(midl); highr:=widen(hpr)-widen(midr); + + if amt_i<32 then + eql:=widen(hpl)+shift_right(widen(lowl),4)-shift_right(bandl,5)+shift_right(highl,5); + eqr:=widen(hpr)+shift_right(widen(lowr),4)-shift_right(bandr,5)+shift_right(highr,5); + elsif amt_i<80 then + eql:=widen(hpl)+shift_right(widen(lowl),3)-shift_right(bandl,4)+shift_right(highl,4); + eqr:=widen(hpr)+shift_right(widen(lowr),3)-shift_right(bandr,4)+shift_right(highr,4); + else + eql:=widen(hpl)+shift_right(widen(lowl),2)-shift_right(bandl,3)+shift_right(highl,3); + eqr:=widen(hpr)+shift_right(widen(lowr),2)-shift_right(bandr,3)+shift_right(highr,3); + end if; + + -- Keep bass nearly mono while opening the upper side signal. + m:=shift_right(eql+eqr,1); s:=shift_right(eql-eqr,1); + slp:=side_lp+shift_right(s-side_lp,6); side_lp<=slp; + if amt_i<32 then + sout:=shift_right(slp,1)+(s-slp)+shift_right(s-slp,4); + elsif amt_i<80 then + sout:=shift_right(slp,2)+(s-slp)+shift_right(s-slp,3); + else + sout:=shift_right(slp,3)+(s-slp)+shift_right(s-slp,2); + end if; + wl:=m+sout; wr:=m-sout; + pre_l<=sat_q123(wl); pre_r<=sat_q123(wr); + -- Stereo-linked compressor envelope and makeup target. + peak_i:=abs_q(sat_q123(wl)); + if abs_q(sat_q123(wr))>peak_i then peak_i:=abs_q(sat_q123(wr)); end if; + env_i:=env_q; + if peak_i>env_i then env_i:=env_i+(peak_i-env_i)/128; + else env_i:=env_i+(peak_i-env_i)/2048; end if; + if env_i<0 then env_i:=0; end if; + env_q<=env_i; + + -- Slow absolute envelope: RMS-like program memory without a + -- squaring multiplier. Blend it with the faster peak detector. + slow_i:=slow_env_q; + if peak_i>slow_i then slow_i:=slow_i+(peak_i-slow_i)/1024; + else slow_i:=slow_i+(peak_i-slow_i)/8192; end if; + if slow_i<0 then slow_i:=0; end if; + slow_env_q<=slow_i; + det_i:=(env_i+slow_i)/2; + + tgt:=target_gain(det_i,amt_i); + if tgtgain_q then + if amt_i>=80 then delta:=(tgt-gain_q)/2048; + else delta:=(tgt-gain_q)/1024; end if; + if delta<1 then delta:=1; end if; + if gain_q+delta>tgt then gain_q<=tgt; else gain_q<=gain_q+delta; end if; + end if; + state<=GAIN_L; + end if; + end if; + + when GAIN_L => + comp_l<=mul_scaled; + state<=GAIN_R; + + when GAIN_R => + out_l<=soft_clip_acc(comp_l); + out_r<=soft_clip_acc(mul_scaled); + state<=OUTPUT; + + when OUTPUT => + valid_out<='1'; + state<=IDLE; + end case; + end if; + end if; + end process; +end architecture rtl; diff --git a/src/rtl/fx_pkg.vhd b/src/rtl/fx_pkg.vhd new file mode 100644 index 0000000..9468a48 --- /dev/null +++ b/src/rtl/fx_pkg.vhd @@ -0,0 +1,95 @@ +------------------------------------------------------------------------------- +-- fx_pkg.vhd - fixed-point helpers shared by the RADIAN stereo FX chain. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.fdtd_pkg.all; + +package fx_pkg is + subtype u8_t is unsigned(7 downto 0); + subtype q15_t is signed(15 downto 0); -- Q1.15 for BRAM-backed wet paths + + function to_q15(x : q123_t) return q15_t; + function from_q15(x : q15_t) return q123_t; + function scale_acc_u8(x : acc_t; g : u8_t) return acc_t; + function scale_u8(x : q123_t; g : u8_t) return q123_t; + function mix_u8(dry, wet : q123_t; amount : u8_t) return q123_t; + function soft_clip_acc(x : acc_t) return q123_t; + function stereo_pack(l, r : q123_t) return std_logic_vector; + function pack_l(x : std_logic_vector(47 downto 0)) return q123_t; + function pack_r(x : std_logic_vector(47 downto 0)) return q123_t; +end package fx_pkg; + +package body fx_pkg is + function to_q15(x : q123_t) return q15_t is + begin + return resize(shift_right(x,8),16); + end function; + + function from_q15(x : q15_t) return q123_t is + begin + return shift_left(resize(x,Q_BITS),8); + end function; + + function scale_acc_u8(x : acc_t; g : u8_t) return acc_t is + variable gs : signed(8 downto 0); + variable p : signed(ACC_BITS + 9 - 1 downto 0); + variable r : signed(ACC_BITS + 9 - 1 downto 0); + begin + gs := signed('0' & std_logic_vector(g)); + p := x * gs; + r := shift_right(p + to_signed(128, p'length), 8); + return resize(r, ACC_BITS); + end function; + + function scale_u8(x : q123_t; g : u8_t) return q123_t is + begin + return sat_store(scale_acc_u8(to_acc(x), g)); + end function; + + function mix_u8(dry, wet : q123_t; amount : u8_t) return q123_t is + variable delta : acc_t; + variable y : acc_t; + begin + delta := to_acc(wet) - to_acc(dry); + y := to_acc(dry) + scale_acc_u8(delta, amount); + return sat_store(y); + end function; + + function soft_clip_acc(x : acc_t) return q123_t is + constant THRESH : acc_t := to_signed(2**22, ACC_BITS); -- 0.5 + variable mag, y : acc_t; + variable neg : boolean; + begin + neg := x < 0; + if neg then mag := -x; else mag := x; end if; + if mag <= THRESH then + y := mag; + else + -- Gentle piecewise knee: 0.5 + (|x|-0.5)/4. + y := THRESH + shift_right(mag - THRESH, 2); + end if; + if neg then y := -y; end if; + return sat_store(y); + end function; + + function stereo_pack(l, r : q123_t) return std_logic_vector is + variable v : std_logic_vector(47 downto 0); + begin + v := std_logic_vector(l) & std_logic_vector(r); + return v; + end function; + + function pack_l(x : std_logic_vector(47 downto 0)) return q123_t is + begin + return signed(x(47 downto 24)); + end function; + + function pack_r(x : std_logic_vector(47 downto 0)) return q123_t is + begin + return signed(x(23 downto 0)); + end function; +end package body fx_pkg; diff --git a/src/rtl/fx_tone.vhd b/src/rtl/fx_tone.vhd new file mode 100644 index 0000000..46d5303 --- /dev/null +++ b/src/rtl/fx_tone.vhd @@ -0,0 +1,66 @@ +------------------------------------------------------------------------------- +-- fx_tone.vhd - low-cost stereo tilt tone control around a one-pole split. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.fdtd_pkg.all; +use work.fx_pkg.all; + +entity fx_tone is + port ( + clk, rst, valid_in : in std_logic; + enable : in std_logic; + tone : in unsigned(7 downto 0); -- 128 = neutral + in_l, in_r : in q123_t; + out_l, out_r : out q123_t; + valid_out : out std_logic + ); +end entity; + +architecture rtl of fx_tone is + signal low_l, low_r : q123_t := Q123_ZERO; +begin + process(clk) + variable dl, dr, hl, hr, yl, yr : acc_t; + variable nl, nr : q123_t; + variable delta : integer; + variable gain : unsigned(7 downto 0); + begin + if rising_edge(clk) then + valid_out <= '0'; + if rst='1' then + low_l<=Q123_ZERO; low_r<=Q123_ZERO; + out_l<=Q123_ZERO; out_r<=Q123_ZERO; + elsif valid_in='1' then + dl := to_acc(in_l)-to_acc(low_l); + dr := to_acc(in_r)-to_acc(low_r); + nl := sat_store(to_acc(low_l)+shift_right(dl,3)); + nr := sat_store(to_acc(low_r)+shift_right(dr,3)); + low_l <= nl; low_r <= nr; + if enable='0' or tone=to_unsigned(128,8) then + out_l <= in_l; out_r <= in_r; + else + hl := to_acc(in_l)-to_acc(nl); + hr := to_acc(in_r)-to_acc(nr); + delta := to_integer(tone)-128; + if delta >= 0 then + if delta*2 > 255 then gain := to_unsigned(255,8); + else gain := to_unsigned(delta*2,8); end if; + yl := to_acc(in_l)+shift_right(scale_acc_u8(hl,gain),1); + yr := to_acc(in_r)+shift_right(scale_acc_u8(hr,gain),1); + else + delta := -delta; + if delta*2 > 255 then gain := to_unsigned(255,8); + else gain := to_unsigned(delta*2,8); end if; + yl := to_acc(in_l)-scale_acc_u8(hl,gain); + yr := to_acc(in_r)-scale_acc_u8(hr,gain); + end if; + out_l <= sat_store(yl); out_r <= sat_store(yr); + end if; + valid_out <= '1'; + end if; + end if; + end process; +end architecture; diff --git a/src/rtl/grid_mesh.vhd b/src/rtl/grid_mesh.vhd index 9306141..6ae0aac 100644 --- a/src/rtl/grid_mesh.vhd +++ b/src/rtl/grid_mesh.vhd @@ -29,12 +29,15 @@ use ieee.numeric_std.all; library work; use work.fdtd_pkg.all; +use work.physical_pkg.all; entity grid_mesh is generic ( NX : positive := 8; NY : positive := 8; FREE_BOUNDARY : boolean := false; + BALANCED_FREE_STRIKE : boolean := false; + HF_DAMPING : boolean := false; -- excitation node (default: centre) EXC_X : natural := NX / 2; EXC_Y : natural := NY / 2; @@ -45,6 +48,21 @@ entity grid_mesh is PICK_RY : natural := NY / 2 ); port ( + free_mode : in boolean := FREE_BOUNDARY; + tap_lx : in natural range 0 to NX-1 := PICK_LX; + tap_ly : in natural range 0 to NY-1 := PICK_LY; + tap_rx : in natural range 0 to NX-1 := PICK_RX; + tap_ry : in natural range 0 to NY-1 := PICK_RY; + tap_lfx,tap_lfy,tap_rfx,tap_rfy : in frac2_t := (others=>'0'); + material : in material_t := (others=>'0'); + anisotropy : in aniso_t := (others=>'0'); + stiffness_ctrl : in unsigned(7 downto 0) := (others=>'0'); + hardness_ctrl : in unsigned(7 downto 0) := (others=>'0'); + mallet_enable : in std_logic := '0'; + rim_ctrl,strike_size : in unsigned(7 downto 0) := (others=>'0'); + strike_x : in natural range 0 to NX-1 := EXC_X; + strike_y : in natural range 0 to NY-1 := EXC_Y; + strike_fx,strike_fy : in frac2_t := (others=>'0'); clk : in std_logic; rst : in std_logic; -- synchronous, resets the whole mesh to rest strobe : in std_logic; -- advance one mesh time-step @@ -59,13 +77,42 @@ end entity grid_mesh; architecture structural of grid_mesh is + function mirror_x return natural is + begin if NX >= NY then return NX-1-EXC_X; else return EXC_X; end if; end; + function mirror_y return natural is + begin if NX >= NY then return EXC_Y; else return NY-1-EXC_Y; end if; end; type grid_t is array (0 to NY-1, 0 to NX-1) of q123_t; type nbgrid_t is array (0 to NY-1, 0 to NX-1) of neighbours_t; + type bgrid_t is array (0 to NY-1, 0 to NX-1) of acc_t; - signal u : grid_t; -- each node's current displacement (u_out) + signal u : grid_t := (others=>(others=>Q123_ZERO)); -- current displacement signal nbw : nbgrid_t; -- assembled N/S/E/W neighbour inputs per node + signal biharm_g : bgrid_t := (others=>(others=>(others=>'0'))); - signal exc_node : q123_t; -- forcing for the exc node + -- Sample the second-ring/diagonal stencil with the same boundary semantics + -- as the legacy first ring. Fixed edges zero-pad; free/compliant edges mirror + -- the inward sample and apply the RIM reflection factor once per crossed axis. + impure function sample_grid(y,x:integer; fm:boolean; rim:unsigned(7 downto 0)) + return q123_t is + variable yy,xx:integer; variable v:q123_t; + variable cross_y,cross_x:boolean:=false; + begin + yy:=y; xx:=x; + if yy<0 then yy:=-yy; cross_y:=true; + elsif yy>=NY then yy:=2*(NY-1)-yy; cross_y:=true; end if; + if xx<0 then xx:=-xx; cross_x:=true; + elsif xx>=NX then xx:=2*(NX-1)-xx; cross_x:=true; end if; + if yy<0 then yy:=0; elsif yy>=NY then yy:=NY-1; end if; + if xx<0 then xx:=0; elsif xx>=NX then xx:=NX-1; end if; + v:=u(yy,xx); + if cross_y then v:=rim_neighbor(v,fm,rim); end if; + if cross_x then v:=rim_neighbor(v,fm,rim); end if; + return v; + end; + + signal exc_node : q123_t; + signal contact_u,mallet_force : q123_t := Q123_ZERO; + signal mallet_contact,mallet_active : std_logic; signal vsr : std_logic_vector(3 downto 0) := (others => '0'); begin @@ -75,10 +122,59 @@ begin report "grid_mesh: FREE_BOUNDARY requires NX >= 2 and NY >= 2" severity failure; - exc_node <= exc_in when exc_en = '1' else (others => '0'); + -- Physical contact reads the actual quarter-cell strike position. + contact_interp : process(all) + variable x1,y1:natural; + begin + if strike_xclk,rst=>rst,enable=>mallet_enable,step=>strobe, + trigger=>exc_en,strike_velocity=>exc_in,hardness=>hardness_ctrl, + surface_u=>contact_u,force_out=>mallet_force, + contact=>mallet_contact,active=>mallet_active, + hammer_x=>open,hammer_v=>open); + + exc_node <= mallet_force when mallet_enable='1' else + exc_in when exc_en='1' else Q123_ZERO; + + -- Wider 13-point plate operator. The first axial ring comes from the exact + -- legacy neighbour fabric; only diagonals and the second axial ring require + -- the boundary-aware sampler above. + biharm_calc : process(all) + begin + for i in 0 to NY-1 loop + for j in 0 to NX-1 loop + biharm_g(i,j) <= biharmonic_term( + u(i,j), nbw(i,j).n, nbw(i,j).s, nbw(i,j).e, nbw(i,j).w, + sample_grid(i-1,j+1,free_mode,rim_ctrl), + sample_grid(i-1,j-1,free_mode,rim_ctrl), + sample_grid(i+1,j+1,free_mode,rim_ctrl), + sample_grid(i+1,j-1,free_mode,rim_ctrl), + sample_grid(i-2,j,free_mode,rim_ctrl), + sample_grid(i+2,j,free_mode,rim_ctrl), + sample_grid(i,j+2,free_mode,rim_ctrl), + sample_grid(i,j-2,free_mode,rim_ctrl)); + end loop; + end loop; + end process; - pick_l <= u(PICK_LY, PICK_LX); - pick_r <= u(PICK_RY, PICK_RX); + pickup_interp : process(all) + variable lx1,ly1,rx1,ry1:natural; + begin + if tap_lx 0 generate nbw(i, j).n <= u(i-1, j); end generate; n_bnd : if i = 0 generate - n_free : if FREE_BOUNDARY generate nbw(i, j).n <= u(i+1, j); end generate; - n_fix : if not FREE_BOUNDARY generate nbw(i, j).n <= Q123_ZERO; end generate; + n_many : if NY > 1 generate + nbw(i,j).n <= rim_neighbor(u(i+1,j),free_mode,rim_ctrl); + end generate; + n_one : if NY = 1 generate nbw(i,j).n <= Q123_ZERO; end generate; end generate; -- South (i+1) s_int : if i < NY-1 generate nbw(i, j).s <= u(i+1, j); end generate; s_bnd : if i = NY-1 generate - s_free : if FREE_BOUNDARY generate nbw(i, j).s <= u(i-1, j); end generate; - s_fix : if not FREE_BOUNDARY generate nbw(i, j).s <= Q123_ZERO; end generate; + s_many : if NY > 1 generate + nbw(i,j).s <= rim_neighbor(u(i-1,j),free_mode,rim_ctrl); + end generate; + s_one : if NY = 1 generate nbw(i,j).s <= Q123_ZERO; end generate; end generate; -- East (j+1) e_int : if j < NX-1 generate nbw(i, j).e <= u(i, j+1); end generate; e_bnd : if j = NX-1 generate - e_free : if FREE_BOUNDARY generate nbw(i, j).e <= u(i, j-1); end generate; - e_fix : if not FREE_BOUNDARY generate nbw(i, j).e <= Q123_ZERO; end generate; + e_many : if NX > 1 generate + nbw(i,j).e <= rim_neighbor(u(i,j-1),free_mode,rim_ctrl); + end generate; + e_one : if NX = 1 generate nbw(i,j).e <= Q123_ZERO; end generate; end generate; -- West (j-1) w_int : if j > 0 generate nbw(i, j).w <= u(i, j-1); end generate; w_bnd : if j = 0 generate - w_free : if FREE_BOUNDARY generate nbw(i, j).w <= u(i, j+1); end generate; - w_fix : if not FREE_BOUNDARY generate nbw(i, j).w <= Q123_ZERO; end generate; + w_many : if NX > 1 generate + nbw(i,j).w <= rim_neighbor(u(i,j+1),free_mode,rim_ctrl); + end generate; + w_one : if NX = 1 generate nbw(i,j).w <= Q123_ZERO; end generate; end generate; - -- Processing element. Only the excitation node drives `exc`; every other - -- node leaves it at its default (rest), so the mesh is linear elsewhere. - exc_node_g : if (i = EXC_Y) and (j = EXC_X) generate - pe : entity work.node_element - port map (clk => clk, rst => rst, strobe => strobe, coeffs => coeffs, - nb => nbw(i, j), exc => exc_node, u_out => u(i, j), valid => open); - end generate; - plain_node_g : if not ((i = EXC_Y) and (j = EXC_X)) generate - pe : entity work.node_element - port map (clk => clk, rst => rst, strobe => strobe, coeffs => coeffs, - nb => nbw(i, j), u_out => u(i, j), valid => open); - end generate; + -- Runtime strike position + footprint. Size 0 is the fractional 2x2 + -- point contact; larger sizes use normalized 3x3 membrane footprints. + force_interp : process(all) + variable pos,neg:q123_t; variable w:natural; + variable dx,dy,mx,my:integer; + begin + pos:=Q123_ZERO; neg:=Q123_ZERO; + dx:=j-integer(strike_x); dy:=i-integer(strike_y); + w:=footprint_weight(strike_size,dx,dy,strike_fx,strike_fy); + if w/=0 then pos:=scale_sixteenth(exc_node,w); end if; + if NX>=NY then mx:=NX-1-integer(strike_x); my:=integer(strike_y); + else mx:=integer(strike_x); my:=NY-1-integer(strike_y); end if; + if BALANCED_FREE_STRIKE and free_mode and i=my and j=mx then + neg:=sat_store(-to_acc(exc_node)); + end if; + forcing<=sat_store(to_acc(pos)+to_acc(neg)); + end process; + pe : entity work.node_element + generic map (HF_DAMPING=>HF_DAMPING) + port map (clk=>clk, rst=>rst, strobe=>strobe, coeffs=>coeffs, + nb=>nbw(i,j), material=>material,anisotropy=>anisotropy, + stiffness_ctrl=>stiffness_ctrl,biharm=>biharm_g(i,j), + exc=>forcing, u_out=>u(i,j), valid=>open); + end generate; end generate; diff --git a/src/rtl/grid_mesh_tdm.vhd b/src/rtl/grid_mesh_tdm.vhd index 900cb68..68e9d64 100644 --- a/src/rtl/grid_mesh_tdm.vhd +++ b/src/rtl/grid_mesh_tdm.vhd @@ -3,27 +3,24 @@ -- -- Functionally identical to grid_mesh (same ports, same Q1.23 result), but -- instead of one node_element per node it stores the whole grid in memory and --- sweeps it through a SINGLE shared datapath, one node per clock. This breaks --- the O(N^2) DSP ceiling of the fully-spatial mesh (README §3): the datapath is --- ~18 DSP regardless of NX*NY, at the cost of NX*NY clocks per mesh step. +-- sweeps it through a SINGLE shared datapath. STIFFNESS=0 retains the legacy +-- one-node-per-clock raster. Nonzero STIFFNESS uses four gather clocks plus one +-- update clock per node for the diagonal/second-ring plate stencil. This breaks +-- the O(N^2) DSP ceiling of the fully-spatial mesh: the datapath remains ~18 DSP +-- regardless of NX*NY. -- -- State storage: two memories (mem_a / mem_b) hold the grid, ping-ponged each --- step. Reads gather the 5-point stencil from the "current" memory (u^n) and --- the node's own u^{n-1} from the "previous" memory; the result u^{n+1} is --- written back into the previous memory (whose u^{n-1} value is no longer --- needed once that node is computed). After the sweep the roles swap. Because --- every neighbour is read from the consistent u^n snapshot, the result is --- bit-exact with the spatial grid_mesh. +-- step. The normal update reads the 5-point stencil from the "current" memory +-- (u^n) and u^{n-1} from the "previous" memory. For the plate term, four gather +-- states capture the additional eight taps two at a time from the same u^n +-- snapshot. The result u^{n+1} is written into the previous memory; after the +-- sweep the roles swap. This keeps the result bit-exact with spatial grid_mesh. -- --- One strobe = one full sweep; `valid` pulses when the sweep completes (so --- mesh_resonator's per-step handshake works unchanged). For larger meshes the --- single datapath becomes a pool of P PEs over partitioned nodes, and the --- combinational-read memory becomes registered-read block RAM with row line --- buffers; both are width/throughput refinements of this structure. --- --- Budget: a sweep is NX*NY + a few clocks; with oversampling OS the mesh costs --- ~OS*NX*NY clocks/frame, well within ~2083 clocks at 100 MHz / 48 kHz for a --- modest grid (e.g. 16x16 at OS=4 ~ 1024 clocks). See docs/timing_budget.md. +-- One strobe = one full sweep; `valid` pulses when the sweep completes, so +-- mesh_resonator's handshake is unchanged. At 8x8, nonzero stiffness measures +-- 322 clocks/mesh-step; OS=4 uses 1288 mesh clocks/frame before small wrapper +-- overhead, within ~2083 clocks at 100 MHz / 48 kHz. STIFFNESS=0 bypasses the +-- gather states and keeps legacy timing. See docs/timing_budget.md. -- -- Synthesisable VHDL-2008. ------------------------------------------------------------------------------- @@ -34,20 +31,38 @@ use ieee.numeric_std.all; library work; use work.fdtd_pkg.all; +use work.physical_pkg.all; entity grid_mesh_tdm is generic ( NX : positive := 8; NY : positive := 8; FREE_BOUNDARY : boolean := false; - EXC_X : natural := 8 / 2; - EXC_Y : natural := 8 / 2; - PICK_LX : natural := 8 / 4; - PICK_LY : natural := 8 / 2; - PICK_RX : natural := (3 * 8) / 4; - PICK_RY : natural := 8 / 2 + BALANCED_FREE_STRIKE : boolean := false; + HF_DAMPING : boolean := false; + EXC_X : natural := NX / 2; + EXC_Y : natural := NY / 2; + PICK_LX : natural := NX / 4; + PICK_LY : natural := NY / 2; + PICK_RX : natural := (3 * NX) / 4; + PICK_RY : natural := NY / 2 ); port ( + free_mode : in boolean := FREE_BOUNDARY; + tap_lx : in natural range 0 to NX-1 := PICK_LX; + tap_ly : in natural range 0 to NY-1 := PICK_LY; + tap_rx : in natural range 0 to NX-1 := PICK_RX; + tap_ry : in natural range 0 to NY-1 := PICK_RY; + tap_lfx,tap_lfy,tap_rfx,tap_rfy : in frac2_t := (others=>'0'); + material : in material_t := (others=>'0'); + anisotropy : in aniso_t := (others=>'0'); + stiffness_ctrl : in unsigned(7 downto 0) := (others=>'0'); + hardness_ctrl : in unsigned(7 downto 0) := (others=>'0'); + mallet_enable : in std_logic := '0'; + rim_ctrl,strike_size : in unsigned(7 downto 0) := (others=>'0'); + strike_x : in natural range 0 to NX-1 := EXC_X; + strike_y : in natural range 0 to NY-1 := EXC_Y; + strike_fx,strike_fy : in frac2_t := (others=>'0'); clk : in std_logic; rst : in std_logic; strobe : in std_logic; @@ -67,13 +82,36 @@ architecture rtl of grid_mesh_tdm is constant A_PL : natural := PICK_LY * NX + PICK_LX; constant A_PR : natural := PICK_RY * NX + PICK_RX; + function mirror_x return natural is + begin if NX >= NY then return NX-1-EXC_X; else return EXC_X; end if; end; + function mirror_y return natural is + begin if NX >= NY then return EXC_Y; else return NY-1-EXC_Y; end if; end; + constant A_NEG : natural := mirror_y*NX+mirror_x; + signal free_lat : boolean := FREE_BOUNDARY; + signal al_lat, ar_lat : natural range 0 to N-1 := 0; + signal tlx_lat,trx_lat,tlx1_lat,trx1_lat : natural range 0 to NX-1 := 0; + signal tly_lat,try_lat,tly1_lat,try1_lat : natural range 0 to NY-1 := 0; + signal lfx_lat,lfy_lat,rfx_lat,rfy_lat,sfx_lat,sfy_lat : frac2_t := (others=>'0'); + signal mat_lat : material_t := (others=>'0'); + signal aniso_lat : aniso_t := (others=>'0'); + signal rim_lat,size_lat,stiff_lat : unsigned(7 downto 0):=(others=>'0'); + signal sx_lat,sx1_lat : natural range 0 to NX-1 := EXC_X; + signal sy_lat,sy1_lat : natural range 0 to NY-1 := EXC_Y; + signal lp00,lp10,lp01,lp11,rp00,rp10,rp01,rp11 : q123_t := Q123_ZERO; + signal cp00,cp10,cp01,cp11 : q123_t := Q123_ZERO; + signal contact_u,mallet_force : q123_t := Q123_ZERO; + signal mallet_contact,mallet_active : std_logic; type mem_t is array (0 to N-1) of q123_t; signal mem_a : mem_t := (others => (others => '0')); signal mem_b : mem_t := (others => (others => '0')); + subtype lap27_t is signed(26 downto 0); + type lap_mem_t is array (0 to N-1) of lap27_t; + signal lap_hist : lap_mem_t := (others => (others=>'0')); signal cur_sel : std_logic := '0'; -- '0': cur=mem_a, prev=mem_b - type state_t is (IDLE, SWEEP, FINISH); + type state_t is (IDLE, GATHER_NE_NW, GATHER_SE_SW, GATHER_NN_SS, GATHER_EE_WW, SWEEP, FINISH); signal state : state_t := IDLE; + signal g_ne,g_nw,g_se,g_sw,g_nn,g_ss,g_ee,g_ww : q123_t := Q123_ZERO; signal a_cnt : integer range 0 to N := 0; -- node address being swept signal i_cnt : integer range 0 to NY-1 := 0; -- its row signal j_cnt : integer range 0 to NX-1 := 0; -- its column @@ -93,7 +131,36 @@ architecture rtl of grid_mesh_tdm is if cur_sel = '0' then return mem_b(addr); else return mem_a(addr); end if; end function; + -- Boundary-aware random access for diagonal and second-ring plate taps. + impure function cur_xy(y,x:integer; fm:boolean; rim:unsigned(7 downto 0)) + return q123_t is + variable yy,xx:integer; variable v:q123_t; + variable cross_y,cross_x:boolean:=false; + begin + yy:=y; xx:=x; + if yy<0 then yy:=-yy; cross_y:=true; + elsif yy>=NY then yy:=2*(NY-1)-yy; cross_y:=true; end if; + if xx<0 then xx:=-xx; cross_x:=true; + elsif xx>=NX then xx:=2*(NX-1)-xx; cross_x:=true; end if; + if yy<0 then yy:=0; elsif yy>=NY then yy:=NY-1; end if; + if xx<0 then xx:=0; elsif xx>=NX then xx:=NX-1; end if; + v:=cur_rd(yy*NX+xx); + if cross_y then v:=rim_neighbor(v,fm,rim); end if; + if cross_x then v:=rim_neighbor(v,fm,rim); end if; + return v; + end function; + + begin + mallet : entity work.physical_mallet + port map(clk=>clk,rst=>rst,enable=>mallet_enable,step=>strobe, + trigger=>exc_en,strike_velocity=>exc_in,hardness=>hardness_ctrl, + surface_u=>contact_u,force_out=>mallet_force, + contact=>mallet_contact,active=>mallet_active, + hammer_x=>open,hammer_v=>open); + + assert not BALANCED_FREE_STRIKE or A_NEG /= A_EXC + report "Balanced free excitation needs distinct mirrored nodes" severity failure; assert not FREE_BOUNDARY or (NX >= 2 and NY >= 2) report "grid_mesh_tdm: FREE_BOUNDARY requires NX >= 2 and NY >= 2" @@ -101,20 +168,31 @@ begin process (clk) variable vC, vP, vN, vS, vE, vW : q123_t; - variable u2, au2, g2l : q123_t; - variable lap, su1, two_u, acc : acc_t; - variable exc_v : q123_t; - variable u_new : q123_t; + variable vNE,vNW,vSE,vSW,vNN,vSS,vEE,vWW : q123_t; + variable u2, au2, g2l : q123_t; + variable lap,lapx,lapy,biharm,su1,two_u,acc : acc_t; + variable exc_v,pos_v,neg_v : q123_t; + variable u_new : q123_t; + variable w : natural; + variable dx,dy,mx,my : integer; begin if rising_edge(clk) then if rst = '1' then mem_a <= (others => (others => '0')); mem_b <= (others => (others => '0')); + lap_hist <= (others => (others=>'0')); cur_sel <= '0'; state <= IDLE; a_cnt <= 0; i_cnt <= 0; j_cnt <= 0; pick_l <= (others => '0'); pick_r <= (others => '0'); + lp00<=Q123_ZERO;lp10<=Q123_ZERO;lp01<=Q123_ZERO;lp11<=Q123_ZERO; + rp00<=Q123_ZERO;rp10<=Q123_ZERO;rp01<=Q123_ZERO;rp11<=Q123_ZERO; + cp00<=Q123_ZERO;cp10<=Q123_ZERO;cp01<=Q123_ZERO;cp11<=Q123_ZERO; + contact_u<=Q123_ZERO; + stiff_lat<=(others=>'0'); + g_ne<=Q123_ZERO;g_nw<=Q123_ZERO;g_se<=Q123_ZERO;g_sw<=Q123_ZERO; + g_nn<=Q123_ZERO;g_ss<=Q123_ZERO;g_ee<=Q123_ZERO;g_ww<=Q123_ZERO; valid <= '0'; else valid <= '0'; @@ -123,41 +201,113 @@ begin when IDLE => if strobe = '1' then a_cnt <= 0; i_cnt <= 0; j_cnt <= 0; - exc_lat <= exc_in; -- hold excitation for the whole sweep - exen_lat <= exc_en; - state <= SWEEP; + free_lat <= free_mode; + al_lat <= tap_ly*NX+tap_lx; ar_lat <= tap_ry*NX+tap_rx; + tlx_lat<=tap_lx; tly_lat<=tap_ly; trx_lat<=tap_rx; try_lat<=tap_ry; + if tap_lx + g_ne<=cur_xy(i_cnt-1,j_cnt+1,free_lat,rim_lat); + g_nw<=cur_xy(i_cnt-1,j_cnt-1,free_lat,rim_lat); + state<=GATHER_SE_SW; + when GATHER_SE_SW => + g_se<=cur_xy(i_cnt+1,j_cnt+1,free_lat,rim_lat); + g_sw<=cur_xy(i_cnt+1,j_cnt-1,free_lat,rim_lat); + state<=GATHER_NN_SS; + when GATHER_NN_SS => + g_nn<=cur_xy(i_cnt-2,j_cnt,free_lat,rim_lat); + g_ss<=cur_xy(i_cnt+2,j_cnt,free_lat,rim_lat); + state<=GATHER_EE_WW; + when GATHER_EE_WW => + g_ee<=cur_xy(i_cnt,j_cnt+2,free_lat,rim_lat); + g_ww<=cur_xy(i_cnt,j_cnt-2,free_lat,rim_lat); + state<=SWEEP; + when SWEEP => -- gather the 5-point stencil from u^n (boundary handled), self u^{n-1} vC := cur_rd(a_cnt); vP := prev_rd(a_cnt); - if i_cnt > 0 then vN := cur_rd(a_cnt - NX); - elsif FREE_BOUNDARY then vN := cur_rd(a_cnt + NX); - else vN := (others => '0'); end if; - if i_cnt < NY-1 then vS := cur_rd(a_cnt + NX); - elsif FREE_BOUNDARY then vS := cur_rd(a_cnt - NX); - else vS := (others => '0'); end if; - if j_cnt < NX-1 then vE := cur_rd(a_cnt + 1); - elsif FREE_BOUNDARY then vE := cur_rd(a_cnt - 1); - else vE := (others => '0'); end if; - if j_cnt > 0 then vW := cur_rd(a_cnt - 1); - elsif FREE_BOUNDARY then vW := cur_rd(a_cnt + 1); - else vW := (others => '0'); end if; + if i_cnt>0 then vN:=cur_rd(a_cnt-NX); + else vN:=rim_neighbor(cur_rd(a_cnt+NX),free_lat,rim_lat); end if; + if i_cnt0 then vW:=cur_rd(a_cnt-1); + else vW:=rim_neighbor(cur_rd(a_cnt+1),free_lat,rim_lat); end if; -- node update (matches node_element exactly, incl. exc forcing) u2 := q_mul(vC, vC); au2 := q_mul(coeffs.alpha, u2); - g2l := clamp(sat_add(coeffs.gamma2, au2), Q123_ZERO, coeffs.gamma2_max); - lap := to_acc(vN) + to_acc(vS) + to_acc(vE) + to_acc(vW) - - shift_left(to_acc(vC), 2); + g2l := clamp(sat_add(coeffs.gamma2, au2), Q123_ZERO, + stiff_gamma2_max(coeffs.gamma2_max,stiff_lat)); + lapx:=to_acc(vE)+to_acc(vW)-shift_left(to_acc(vC),1); + lapy:=to_acc(vN)+to_acc(vS)-shift_left(to_acc(vC),1); + lap:=anisotropic_lap(lapx,lapy,effective_aniso(aniso_lat,mat_lat)); + vNE:=g_ne;vNW:=g_nw;vSE:=g_se;vSW:=g_sw; + vNN:=g_nn;vSS:=g_ss;vEE:=g_ee;vWW:=g_ww; + biharm:=biharmonic_term(vC,vN,vS,vE,vW,vNE,vNW,vSE,vSW,vNN,vSS,vEE,vWW); su1 := mul_coeff(coeffs.sigk1, to_acc(vP)); two_u := shift_left(to_acc(vC), 1); - acc := two_u - su1 + mul_coeff(g2l, lap); - if exen_lat = '1' and a_cnt = A_EXC then exc_v := exc_lat; - else exc_v := (others => '0'); end if; + acc := two_u - su1 + mul_coeff(g2l, lap) - stiffness_term(biharm,stiff_lat); + if HF_DAMPING then + acc:=acc+hf_loss_term(lap-resize(lap_hist(a_cnt),ACC_BITS),mat_lat); + lap_hist(a_cnt)<=resize(lap,lap27_t'length); + end if; + pos_v:=Q123_ZERO; neg_v:=Q123_ZERO; w:=0; + if exen_lat='1' then + dx:=j_cnt-integer(sx_lat); dy:=i_cnt-integer(sy_lat); + w:=footprint_weight(size_lat,dx,dy,sfx_lat,sfy_lat); + if w/=0 then pos_v:=scale_sixteenth(exc_lat,w); end if; + if NX>=NY then mx:=NX-1-integer(sx_lat);my:=integer(sy_lat); + else mx:=integer(sx_lat);my:=NY-1-integer(sy_lat);end if; + if i_cnt=my and j_cnt=mx and free_lat and BALANCED_FREE_STRIKE then + neg_v:=sat_store(-to_acc(exc_lat)); + end if; + end if; + exc_v:=sat_store(to_acc(pos_v)+to_acc(neg_v)); u_new := sat_store(mul_coeff(coeffs.a0, acc) + to_acc(exc_v)); + -- Capture pickup interpolation corners during the normal raster. + if i_cnt=tly_lat and j_cnt=tlx_lat then lp00<=u_new; end if; + if i_cnt=tly_lat and j_cnt=tlx1_lat then lp10<=u_new; end if; + if i_cnt=tly1_lat and j_cnt=tlx_lat then lp01<=u_new; end if; + if i_cnt=tly1_lat and j_cnt=tlx1_lat then lp11<=u_new; end if; + if i_cnt=try_lat and j_cnt=trx_lat then rp00<=u_new; end if; + if i_cnt=try_lat and j_cnt=trx1_lat then rp10<=u_new; end if; + if i_cnt=try1_lat and j_cnt=trx_lat then rp01<=u_new; end if; + if i_cnt=try1_lat and j_cnt=trx1_lat then rp11<=u_new; end if; + if i_cnt=sy_lat and j_cnt=sx_lat then cp00<=u_new; end if; + if i_cnt=sy_lat and j_cnt=sx1_lat then cp10<=u_new; end if; + if i_cnt=sy1_lat and j_cnt=sx_lat then cp01<=u_new; end if; + if i_cnt=sy1_lat and j_cnt=sx1_lat then cp11<=u_new; end if; + -- write u^{n+1} into the previous memory if cur_sel = '0' then mem_b(a_cnt) <= u_new; else mem_a(a_cnt) <= u_new; end if; @@ -169,15 +319,14 @@ begin a_cnt <= a_cnt + 1; if j_cnt = NX-1 then j_cnt <= 0; i_cnt <= i_cnt + 1; else j_cnt <= j_cnt + 1; end if; + if stiff_lat=0 then state<=SWEEP; else state<=GATHER_NE_NW; end if; end if; when FINISH => - -- the just-written (previous) memory becomes the new current - if cur_sel = '0' then - pick_l <= mem_b(A_PL); pick_r <= mem_b(A_PR); - else - pick_l <= mem_a(A_PL); pick_r <= mem_a(A_PR); - end if; + -- Bilinear pickup interpolation from corners captured during sweep. + pick_l<=bilerp_quarter(lp00,lp10,lp01,lp11,lfx_lat,lfy_lat); + pick_r<=bilerp_quarter(rp00,rp10,rp01,rp11,rfx_lat,rfy_lat); + contact_u<=bilerp_quarter(cp00,cp10,cp01,cp11,sfx_lat,sfy_lat); cur_sel <= not cur_sel; valid <= '1'; state <= IDLE; diff --git a/src/rtl/mesh.vhd b/src/rtl/mesh.vhd index 538792f..8c3721c 100644 --- a/src/rtl/mesh.vhd +++ b/src/rtl/mesh.vhd @@ -17,24 +17,43 @@ library ieee; use ieee.std_logic_1164.all; +use ieee.numeric_std.all; library work; use work.fdtd_pkg.all; +use work.physical_pkg.all; entity mesh is generic ( NX : positive := 8; NY : positive := 8; FREE_BOUNDARY : boolean := false; + BALANCED_FREE_STRIKE : boolean := false; + HF_DAMPING : boolean := false; TIME_MUX : boolean := false; - EXC_X : natural := 8 / 2; - EXC_Y : natural := 8 / 2; - PICK_LX : natural := 8 / 4; - PICK_LY : natural := 8 / 2; - PICK_RX : natural := (3 * 8) / 4; - PICK_RY : natural := 8 / 2 + EXC_X : natural := NX / 2; + EXC_Y : natural := NY / 2; + PICK_LX : natural := NX / 4; + PICK_LY : natural := NY / 2; + PICK_RX : natural := (3 * NX) / 4; + PICK_RY : natural := NY / 2 ); port ( + free_mode : in boolean := FREE_BOUNDARY; + tap_lx : in natural range 0 to NX-1 := PICK_LX; + tap_ly : in natural range 0 to NY-1 := PICK_LY; + tap_rx : in natural range 0 to NX-1 := PICK_RX; + tap_ry : in natural range 0 to NY-1 := PICK_RY; + tap_lfx,tap_lfy,tap_rfx,tap_rfy : in frac2_t := (others=>'0'); + material : in material_t := (others=>'0'); + anisotropy : in aniso_t := (others=>'0'); + stiffness_ctrl : in unsigned(7 downto 0) := (others=>'0'); + hardness_ctrl : in unsigned(7 downto 0) := (others=>'0'); + mallet_enable : in std_logic := '0'; + rim_ctrl,strike_size : in unsigned(7 downto 0) := (others=>'0'); + strike_x : in natural range 0 to NX-1 := EXC_X; + strike_y : in natural range 0 to NY-1 := EXC_Y; + strike_fx,strike_fy : in frac2_t := (others=>'0'); clk : in std_logic; rst : in std_logic; strobe : in std_logic; @@ -52,22 +71,36 @@ begin spatial_g : if not TIME_MUX generate u_spatial : entity work.grid_mesh - generic map (NX => NX, NY => NY, FREE_BOUNDARY => FREE_BOUNDARY, + generic map (NX => NX, NY => NY, FREE_BOUNDARY => FREE_BOUNDARY, BALANCED_FREE_STRIKE => BALANCED_FREE_STRIKE, EXC_X => EXC_X, EXC_Y => EXC_Y, PICK_LX => PICK_LX, PICK_LY => PICK_LY, PICK_RX => PICK_RX, PICK_RY => PICK_RY) - port map (clk => clk, rst => rst, strobe => strobe, coeffs => coeffs, + port map (free_mode => free_mode, tap_lx => tap_lx, tap_ly => tap_ly, + tap_rx => tap_rx, tap_ry => tap_ry, + tap_lfx=>tap_lfx,tap_lfy=>tap_lfy,tap_rfx=>tap_rfx,tap_rfy=>tap_rfy, + material=>material,anisotropy=>anisotropy,stiffness_ctrl=>stiffness_ctrl, + hardness_ctrl=>hardness_ctrl,mallet_enable=>mallet_enable, + rim_ctrl=>rim_ctrl,strike_size=>strike_size, + strike_x=>strike_x,strike_y=>strike_y,strike_fx=>strike_fx,strike_fy=>strike_fy, + clk => clk, rst => rst, strobe => strobe, coeffs => coeffs, exc_in => exc_in, exc_en => exc_en, pick_l => pick_l, pick_r => pick_r, valid => valid); end generate; tdm_g : if TIME_MUX generate u_tdm : entity work.grid_mesh_tdm - generic map (NX => NX, NY => NY, FREE_BOUNDARY => FREE_BOUNDARY, + generic map (NX => NX, NY => NY, FREE_BOUNDARY => FREE_BOUNDARY, BALANCED_FREE_STRIKE => BALANCED_FREE_STRIKE, EXC_X => EXC_X, EXC_Y => EXC_Y, PICK_LX => PICK_LX, PICK_LY => PICK_LY, PICK_RX => PICK_RX, PICK_RY => PICK_RY) - port map (clk => clk, rst => rst, strobe => strobe, coeffs => coeffs, + port map (free_mode => free_mode, tap_lx => tap_lx, tap_ly => tap_ly, + tap_rx => tap_rx, tap_ry => tap_ry, + tap_lfx=>tap_lfx,tap_lfy=>tap_lfy,tap_rfx=>tap_rfx,tap_rfy=>tap_rfy, + material=>material,anisotropy=>anisotropy,stiffness_ctrl=>stiffness_ctrl, + hardness_ctrl=>hardness_ctrl,mallet_enable=>mallet_enable, + rim_ctrl=>rim_ctrl,strike_size=>strike_size, + strike_x=>strike_x,strike_y=>strike_y,strike_fx=>strike_fx,strike_fy=>strike_fy, + clk => clk, rst => rst, strobe => strobe, coeffs => coeffs, exc_in => exc_in, exc_en => exc_en, pick_l => pick_l, pick_r => pick_r, valid => valid); end generate; diff --git a/src/rtl/mesh_resonator.vhd b/src/rtl/mesh_resonator.vhd index 22ce288..d493c52 100644 --- a/src/rtl/mesh_resonator.vhd +++ b/src/rtl/mesh_resonator.vhd @@ -32,16 +32,38 @@ use ieee.numeric_std.all; library work; use work.fdtd_pkg.all; +use work.physical_pkg.all; entity mesh_resonator is generic ( NX : positive := 8; NY : positive := 8; + EXC_X : natural := NX / 2; EXC_Y : natural := NY / 2; + PICK_LX : natural := NX/4; PICK_LY : natural := NY/2; + PICK_RX : natural := 3*NX/4; PICK_RY : natural := NY/2; OS : positive := 4; -- oversampling factor (mesh steps / frame) FREE_BOUNDARY : boolean := false; + BALANCED_FREE_STRIKE : boolean := false; + HF_DAMPING : boolean := false; + STRIKE_SHAPING : boolean := false; TIME_MUX : boolean := false -- false: spatial mesh; true: time-multiplexed ); port ( + free_mode : in boolean := FREE_BOUNDARY; + tap_lx : in natural range 0 to NX-1 := PICK_LX; + tap_ly : in natural range 0 to NY-1 := PICK_LY; + tap_rx : in natural range 0 to NX-1 := PICK_RX; + tap_ry : in natural range 0 to NY-1 := PICK_RY; + tap_lfx,tap_lfy,tap_rfx,tap_rfy : in frac2_t := (others=>'0'); + material : in material_t := (others=>'0'); + exciter_mode : in exciter_t := (others=>'0'); + anisotropy : in aniso_t := (others=>'0'); + stiffness_ctrl : in unsigned(7 downto 0) := (others=>'0'); + hardness_ctrl : in unsigned(7 downto 0) := (others=>'0'); + rim_ctrl,strike_size : in unsigned(7 downto 0) := (others=>'0'); + strike_x : in natural range 0 to NX-1 := EXC_X; + strike_y : in natural range 0 to NY-1 := EXC_Y; + strike_fx,strike_fy : in frac2_t := (others=>'0'); clk : in std_logic; rst : in std_logic; frame : in std_logic; -- one pulse per audio sample @@ -61,6 +83,9 @@ architecture rtl of mesh_resonator is -- mesh interface signal m_strobe : std_logic := '0'; signal m_exc_en : std_logic := '0'; + signal m_exc_in : q123_t := Q123_ZERO; + signal m_mallet_enable : std_logic := '0'; + signal m_sfx,m_sfy : frac2_t := (others=>'0'); signal m_pick_l : q123_t; signal m_pick_r : q123_t; signal m_valid : std_logic; @@ -71,16 +96,61 @@ architecture rtl of mesh_resonator is signal suml : acc_t := (others => '0'); signal sumr : acc_t := (others => '0'); + function shaped_strike(x:q123_t; phase:natural; mode:exciter_t) return q123_t is + variable mag:integer; variable a:acc_t; + begin + case to_integer(mode) is + when 1 => if phase=0 then return x; else return Q123_ZERO; end if; + when 2 => if phase<=1 then return sat_store(shift_right(to_acc(x),1)); else return Q123_ZERO; end if; + when 3 => if phase=0 then return x; elsif phase=1 then return sat_store(-shift_right(to_acc(x),1)); else return Q123_ZERO; end if; + when 4 => if phase=0 then return x; elsif phase=1 then return sat_store(-shift_right(to_acc(x),2)); else return Q123_ZERO; end if; + when 5 => + case phase is + when 0 => return sat_store(shift_right(to_acc(x),1)); + when 1 => return sat_store(-shift_right(to_acc(x),2)); + when 2 => return sat_store(shift_right(to_acc(x),2)); + when 3 => return sat_store(-shift_right(to_acc(x),3)); + when others => return Q123_ZERO; + end case; + when others => null; + end case; + mag:=to_integer(x); if mag<0 then mag:=-mag; end if; + if phase>1 then return Q123_ZERO; end if; + if mag<2**21 then return sat_store(shift_right(to_acc(x),1)); + elsif mag<2**22 then + if phase=0 then a:=to_acc(x)-shift_right(to_acc(x),2); return sat_store(a); + else return sat_store(shift_right(to_acc(x),2)); end if; + else + if phase=0 then return x; else return sat_store(-shift_right(to_acc(x),2)); end if; + end if; + end function; + begin + -- HARDNESS=0 is an exact legacy bypass. With nonzero HARDNESS, AUTO or the + -- explicit soft/mallet character selects the stateful physical contact; + -- point/pluck/rim/scrape modes keep their existing shaped envelopes. + m_mallet_enable <= '1' when STRIKE_SHAPING and hardness_ctrl/=0 and + (exciter_mode=to_unsigned(0,3) or exciter_mode=to_unsigned(2,3)) + else '0'; + mesh : entity work.mesh - generic map (NX => NX, NY => NY, FREE_BOUNDARY => FREE_BOUNDARY, - TIME_MUX => TIME_MUX) - port map (clk => clk, rst => rst, strobe => m_strobe, coeffs => coeffs, - exc_in => exc_in, exc_en => m_exc_en, + generic map (NX => NX, NY => NY, FREE_BOUNDARY => FREE_BOUNDARY, BALANCED_FREE_STRIKE => BALANCED_FREE_STRIKE, + HF_DAMPING=>HF_DAMPING, TIME_MUX => TIME_MUX, EXC_X => EXC_X, EXC_Y => EXC_Y) + port map (free_mode => free_mode, tap_lx => tap_lx, tap_ly => tap_ly, + tap_rx => tap_rx, tap_ry => tap_ry, + tap_lfx=>tap_lfx,tap_lfy=>tap_lfy,tap_rfx=>tap_rfx,tap_rfy=>tap_rfy, + material=>material,anisotropy=>anisotropy,stiffness_ctrl=>stiffness_ctrl, + hardness_ctrl=>hardness_ctrl,mallet_enable=>m_mallet_enable, + rim_ctrl=>rim_ctrl,strike_size=>strike_size, + strike_x=>strike_x,strike_y=>strike_y,strike_fx=>m_sfx,strike_fy=>m_sfy, + clk => clk, rst => rst, strobe => m_strobe, coeffs => coeffs, + exc_in => m_exc_in, exc_en => m_exc_en, pick_l => m_pick_l, pick_r => m_pick_r, valid => m_valid); process (clk) + variable mode_eff:exciter_t; + variable fxv,fyv:frac2_t; begin if rising_edge(clk) then if rst = '1' then @@ -90,6 +160,7 @@ begin sumr <= (others => '0'); m_strobe <= '0'; m_exc_en <= '0'; + m_exc_in <= Q123_ZERO; m_sfx<=(others=>'0'); m_sfy<=(others=>'0'); out_l <= (others => '0'); out_r <= (others => '0'); out_valid <= '0'; @@ -109,8 +180,27 @@ begin when FIRE => -- launch one oversampled mesh step m_strobe <= '1'; - if cnt = 0 then - m_exc_en <= exc_en; -- mallet on the first oversample step + mode_eff:=effective_exciter(exciter_mode,material); + fxv:=strike_fx; fyv:=strike_fy; + if EXC_X>=NX-1 then fxv:=(others=>'0'); end if; + if EXC_Y>=NY-1 then fyv:=(others=>'0'); end if; + if mode_eff=to_unsigned(1,3) then fxv:=(others=>'0'); fyv:=(others=>'0'); + elsif m_mallet_enable='0' and mode_eff=to_unsigned(2,3) and strike_fx=0 and strike_fy=0 then + fxv:=to_unsigned(2,2); fyv:=to_unsigned(2,2); + end if; + m_sfx<=fxv; m_sfy<=fyv; + if m_mallet_enable='1' then + -- Trigger the hammer once; force then persists from its own state + -- across later oversample steps and audio frames. + m_exc_in<=exc_in; + if cnt=0 and exc_en='1' then m_exc_en<='1'; else m_exc_en<='0'; end if; + elsif STRIKE_SHAPING and exc_en='1' then + m_exc_in<=shaped_strike(exc_in,cnt,mode_eff); + if shaped_strike(exc_in,cnt,mode_eff)/=Q123_ZERO then m_exc_en<='1'; else m_exc_en<='0'; end if; + elsif cnt=0 then + m_exc_en<=exc_en; m_exc_in<=exc_in; + else + m_exc_en<='0'; m_exc_in<=Q123_ZERO; end if; state <= WAITV; diff --git a/src/rtl/midi_frontend.vhd b/src/rtl/midi_frontend.vhd index 6a82623..c1f08e8 100644 --- a/src/rtl/midi_frontend.vhd +++ b/src/rtl/midi_frontend.vhd @@ -1,27 +1,13 @@ ------------------------------------------------------------------------------- --- midi_frontend.vhd - MIDI note/velocity -> mesh pitch, strike, and timbre +-- midi_frontend.vhd - calibrated MIDI note -> mesh pitch + strike -- --- Turns the engine from a physics demo into an instrument (milestone M8). A --- serial MIDI stream drives: --- * pitch : note number -> gamma0^2 (coeffs.gamma2), README §2. Higher --- note -> stiffer/faster mesh -> higher pitch. A mesh mode's --- frequency scales with the wave speed c, and gamma2 = (c*k/h)^2 --- scales with c^2, so one octave (x2 frequency) needs gamma2 x4: --- gamma2(n) = GAMMA2_REF * 2^((n-NOTE_REF)/6), clamped CFL-safe. --- * strike : note-on -> a one-frame excitation impulse (the mallet) --- whose amplitude scales with velocity. --- * timbre : velocity -> chaos coupling alpha (harder hits ring more --- non-linearly), between ALPHA_MIN and ALPHA_MAX. --- * note-off (or note-on velocity 0) -> no strike; the mesh decays naturally --- through its damping (sigk1), exactly like a struck instrument. --- --- The pitch table, reference note, gains, damping and CFL clamp are all --- generics, so the mapping is documented and configurable (see docs/midi.md). --- The block emits a full coeffs_t plus the excitation, ready to drive --- mesh_resonator / top_resonator in place of the control-bus + I2S excitation. --- --- `frame` is the per-audio-frame tick: a pending note-on is delivered as one --- frame of exc_en so the mesh injects exactly one mallet impulse per note. +-- Serial MIDI Note On/Off drives a musical mesh voice. In calibrated mode the +-- 128-entry pitch table is derived at elaboration from NX/NY, OS, FS_HZ and the +-- selected fixed/free boundary. Velocity scales strike energy only by default; +-- CHAOS is deliberately independent and comes from the live preset / mod path. +-- CALIBRATED_PITCH=false retains the legacy raw gamma2 mapping for experiments. +-- A pending Note On is delivered as exactly one frame of exc_en. +-- See docs/midi.md and musical_pkg.vhd for the calibration relation. -- -- Synthesisable VHDL-2008. ------------------------------------------------------------------------------- @@ -33,9 +19,13 @@ use ieee.math_real.all; library work; use work.fdtd_pkg.all; +use work.musical_pkg.all; entity midi_frontend is generic ( + NX : positive := 8; NY : positive := 8; OS : positive := 4; + FS_HZ : positive := 48_000; + CALIBRATED_PITCH : boolean := true; -- false retains explicit raw-coefficient API CLK_HZ : positive := 100_000_000; BAUD : positive := 31_250; -- pitch mapping (note -> gamma2) @@ -48,13 +38,14 @@ entity midi_frontend is SIGK1 : real := 0.99996875; GAMMA2_MAX : real := 0.451; -- velocity mapping - STRIKE_GAIN : real := 0.9; -- excitation amplitude at max velocity + STRIKE_GAIN : real := 0.002; -- excitation amplitude at max velocity ALPHA_MIN : real := 0.0; -- chaos coupling at min velocity - ALPHA_MAX : real := 0.3 -- chaos coupling at max velocity + ALPHA_MAX : real := 0.0 -- chaos coupling at max velocity ); port ( clk : in std_logic; rst : in std_logic; + free_mode: in boolean := false; rx : in std_logic; -- serial MIDI input frame : in std_logic; -- per-audio-frame tick -- to the mesh @@ -73,7 +64,7 @@ architecture rtl of midi_frontend is -- precomputed pitch table: note number -> gamma2 (Q1.23), CFL-clamped type g2_table_t is array (0 to 127) of q123_t; - function build_g2_table return g2_table_t is + function build_g2_table(free: boolean := false) return g2_table_t is variable t : g2_table_t; variable g : real; begin @@ -81,11 +72,13 @@ architecture rtl of midi_frontend is g := GAMMA2_REF * 2.0 ** (real(n - NOTE_REF) / 6.0); if g > GAMMA2_CLAMP then g := GAMMA2_CLAMP; end if; if g < GAMMA2_MIN then g := GAMMA2_MIN; end if; - t(n) := to_q123(g); + if CALIBRATED_PITCH then t(n) := note_gamma2(n,NX,NY,OS,FS_HZ,free); + else t(n) := to_q123(g); end if; end loop; return t; end function; - constant G2_TABLE : g2_table_t := build_g2_table; + constant G2_TABLE : g2_table_t := build_g2_table(false); + constant G2_FREE : g2_table_t := build_g2_table(true); constant STRIKE_Q : q123_t := to_q123(STRIKE_GAIN); constant AMIN_Q : q123_t := to_q123(ALPHA_MIN); @@ -172,7 +165,8 @@ begin note <= std_logic_vector(d1); velocity <= std_logic_vector(vel); if is_on = '1' and vel /= 0 then -- NOTE ON (strike) - coeffs.gamma2 <= G2_TABLE(to_integer(d1)); + if free_mode then coeffs.gamma2 <= G2_FREE(to_integer(d1)); + else coeffs.gamma2 <= G2_TABLE(to_integer(d1)); end if; coeffs.alpha <= sat_add(AMIN_Q, vscale(ARANGE_Q, vel)); exc_in <= vscale(STRIKE_Q, vel); strike_pending <= '1'; diff --git a/src/rtl/musical_pkg.vhd b/src/rtl/musical_pkg.vhd new file mode 100644 index 0000000..16c6c76 --- /dev/null +++ b/src/rtl/musical_pkg.vhd @@ -0,0 +1,54 @@ +-- Musical calibration for the actual discrete mesh, not a continuous string. +-- Tables are evaluated at elaboration; no real arithmetic is synthesized. +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +use work.fdtd_pkg.all; +package musical_pkg is + function mode_eigenvalue(nx, ny: positive; free: boolean) return real; + function note_gamma2(note: natural; nx, ny, os, fs: positive; + free: boolean) return q123_t; + function tension_scale(g, tension: q123_t) return q123_t; + function coordinate(v: unsigned; size: positive) return natural; +end package; +package body musical_pkg is + function mode_eigenvalue(nx, ny: positive; free: boolean) return real is + variable longest: positive := nx; + begin + if free then + if ny > longest then longest := ny; end if; + assert longest > 1 report "Free mesh requires at least two nodes" severity failure; + return 4.0*sin(MATH_PI/(2.0*real(longest-1)))**2; + end if; + return 4.0*(sin(MATH_PI/(2.0*real(nx+1)))**2 + + sin(MATH_PI/(2.0*real(ny+1)))**2); + end; + function note_gamma2(note: natural; nx, ny, os, fs: positive; + free: boolean) return q123_t is + variable hz: real := 440.0*2.0**((real(note)-69.0)/12.0); + variable g: real; + begin + g := 4.0*sin(MATH_PI*hz/real(fs*os))**2/mode_eigenvalue(nx,ny,free); + if g > 0.45 then g := 0.45; end if; + if g < 2.0**(-23) then g := 2.0**(-23); end if; + return to_q123(g); + end; + -- Register 0 in musical presets is normalized tension: 0.25 = concert tuning. + -- The wide product is rounded only once, preserving bass-note precision. + function tension_scale(g, tension: q123_t) return q123_t is + variable product: signed(47 downto 0); + begin + if tension <= 0 then return Q123_ZERO; end if; + product := g*tension; + return sat_q123(shift_right(product+to_signed(2**20,48),21)); + end; + function coordinate(v: unsigned; size: positive) return natural is + variable n: natural; + begin + if is_x(std_logic_vector(v)) then return 0; end if; + n := to_integer(v); + if n >= size then return size-1; end if; + return n; + end; +end package body; diff --git a/src/rtl/node_element.vhd b/src/rtl/node_element.vhd index ca48b71..8a447eb 100644 --- a/src/rtl/node_element.vhd +++ b/src/rtl/node_element.vhd @@ -12,15 +12,16 @@ -- operands and a registered result): -- stage 1 : Laplacian sum, sigk1*u^{n-1}, u^2, 2*u^n (capture inputs) -- stage 2 : alpha*u^2, gamma2_local = clamp(gamma2+alpha*u^2, 0, gamma2_max) --- stage 3 : gamma2_local*lap, form 2u - sigk1*u1 + g2l*lap +-- stage 3 : gamma2_local*lap - mu2*biharm, form the guarded stiff-surface sum -- stage 4 : a0*(...) + forcing, saturate, commit u^n / u^{n-1} -- Latency from `strobe` to `valid` is 4 clocks. Strobes must be spaced at least -- 4 clocks apart (the mesh has ~2083 clocks per sample at 100 MHz / 48 kHz). -- --- The committed result is bit-exact with node_update (and the Q1.23 reference --- model) when the forcing input `exc` is 0. With coeffs.alpha = 0 and --- coeffs.gamma2_max >= coeffs.gamma2, the non-linear term vanishes and the PE --- reduces exactly to the linear update. +-- With STIFFNESS=0 the committed result is bit-exact with node_update (and the +-- legacy Q1.23 reference) when forcing `exc` is 0. With coeffs.alpha=0 and +-- coeffs.gamma2_max>=coeffs.gamma2, that path reduces exactly to the linear +-- membrane update. Nonzero STIFFNESS adds the separately verified biharmonic +-- plate term. -- -- `exc` is an optional additive forcing (the "mallet"), captured with the -- update and added into the 48-bit guard before the store-saturate. It @@ -35,14 +36,20 @@ use ieee.numeric_std.all; library work; use work.fdtd_pkg.all; +use work.physical_pkg.all; entity node_element is + generic (HF_DAMPING : boolean := false); port ( clk : in std_logic; rst : in std_logic; -- synchronous, active-high; resets to rest strobe : in std_logic; -- begin one sample update coeffs : in coeffs_t; -- gamma2 / a0 / sigk1 / alpha / gamma2_max nb : in neighbours_t; -- N/S/E/W neighbour displacements (u^n) + material : in material_t := (others=>'0'); + anisotropy : in aniso_t := (others=>'0'); + stiffness_ctrl : in unsigned(7 downto 0) := (others=>'0'); + biharm : in acc_t := (others=>'0'); -- 13-point plate operator at u^n exc : in q123_t := (others => '0'); -- additive forcing (mallet); default rest u_out : out q123_t; -- this node's current displacement u^n valid : out std_logic -- 1-cycle pulse when u_out has advanced @@ -55,8 +62,15 @@ architecture rtl of node_element is signal u_n : q123_t := (others => '0'); signal u_nm1 : q123_t := (others => '0'); + -- Previous local curvature for the optional frequency-dependent loss. + -- A 27-bit Q.23 word spans the full 5-point Laplacian range (about +/-8). + signal lap_hist : signed(26 downto 0) := (others=>'0'); + -- Stage-1 registers signal s1_lap : acc_t := (others => '0'); + signal s1_lapv : acc_t := (others => '0'); + signal s1_biharm : acc_t := (others => '0'); + signal s1_stiff : unsigned(7 downto 0) := (others=>'0'); signal s1_su1 : acc_t := (others => '0'); signal s1_u2 : q123_t := (others => '0'); -- u^2 signal s1_two_u : acc_t := (others => '0'); @@ -69,6 +83,9 @@ architecture rtl of node_element is -- Stage-2 registers signal s2_lap : acc_t := (others => '0'); + signal s2_lapv : acc_t := (others => '0'); + signal s2_biharm: acc_t := (others => '0'); + signal s2_stiff : unsigned(7 downto 0) := (others=>'0'); signal s2_su1 : acc_t := (others => '0'); signal s2_g2l : q123_t := (others => '0'); -- gamma2_local (clamped) signal s2_two_u : acc_t := (others => '0'); @@ -96,12 +113,15 @@ begin if rst = '1' then u_n <= (others => '0'); u_nm1 <= (others => '0'); - s1_lap <= (others => '0'); s1_su1 <= (others => '0'); + lap_hist <= (others => '0'); + s1_lap <= (others => '0'); s1_lapv <= (others => '0'); + s1_biharm<= (others => '0'); s1_stiff <= (others=>'0'); s1_su1 <= (others => '0'); s1_u2 <= (others => '0'); s1_two_u <= (others => '0'); s1_ucap <= (others => '0'); s1_exc <= (others => '0'); s1_gamma2<= (others => '0'); s1_alpha <= (others => '0'); s1_gmax <= (others => '0'); s1_a0 <= (others => '0'); - s2_lap <= (others => '0'); s2_su1 <= (others => '0'); + s2_lap <= (others => '0'); s2_lapv <= (others => '0'); + s2_biharm<= (others => '0'); s2_stiff <= (others=>'0'); s2_su1 <= (others => '0'); s2_g2l <= (others => '0'); s2_two_u <= (others => '0'); s2_ucap <= (others => '0'); s2_exc <= (others => '0'); s2_a0 <= (others => '0'); @@ -117,8 +137,22 @@ begin -- Stage 1: capture inputs and the first arithmetic layer if strobe = '1' then - s1_lap <= to_acc(nb.n) + to_acc(nb.s) + to_acc(nb.e) + to_acc(nb.w) - - shift_left(to_acc(u_n), 2); -- (uN+uS+uE+uW) - 4*u^n + s1_lap <= anisotropic_lap( + to_acc(nb.e)+to_acc(nb.w)-shift_left(to_acc(u_n),1), + to_acc(nb.n)+to_acc(nb.s)-shift_left(to_acc(u_n),1), + effective_aniso(anisotropy,material)); + s1_lapv <= anisotropic_lap( + to_acc(nb.e)+to_acc(nb.w)-shift_left(to_acc(u_n),1), + to_acc(nb.n)+to_acc(nb.s)-shift_left(to_acc(u_n),1), + effective_aniso(anisotropy,material)) - resize(lap_hist,ACC_BITS); + if HF_DAMPING then + lap_hist <= resize(anisotropic_lap( + to_acc(nb.e)+to_acc(nb.w)-shift_left(to_acc(u_n),1), + to_acc(nb.n)+to_acc(nb.s)-shift_left(to_acc(u_n),1), + effective_aniso(anisotropy,material)),lap_hist'length); + end if; + s1_biharm <= biharm; + s1_stiff <= stiffness_ctrl; s1_su1 <= mul_coeff(coeffs.sigk1, to_acc(u_nm1));-- sigk1 * u^{n-1} s1_u2 <= q_mul(u_n, u_n); -- u^2 (saturating) s1_two_u <= shift_left(to_acc(u_n), 1); -- 2 * u^n @@ -126,7 +160,7 @@ begin s1_exc <= exc; s1_gamma2 <= coeffs.gamma2; s1_alpha <= coeffs.alpha; - s1_gmax <= coeffs.gamma2_max; + s1_gmax <= stiff_gamma2_max(coeffs.gamma2_max,stiffness_ctrl); s1_a0 <= coeffs.a0; end if; @@ -135,6 +169,9 @@ begin s2_g2l <= clamp(sat_add(s1_gamma2, q_mul(s1_alpha, s1_u2)), Q123_ZERO, s1_gmax); s2_lap <= s1_lap; + s2_lapv <= s1_lapv; + s2_biharm<= s1_biharm; + s2_stiff <= s1_stiff; s2_su1 <= s1_su1; s2_two_u <= s1_two_u; s2_ucap <= s1_ucap; @@ -144,7 +181,16 @@ begin -- Stage 3: gamma2_local * lap, then the guard-accumulator sum if vsr(1) = '1' then - s3_acc <= s2_two_u - s2_su1 + mul_coeff(s2_g2l, s2_lap); + if HF_DAMPING then + -- Kelvin-Voigt-like loss: high-curvature velocity components lose + -- energy faster than low modes. 1/128 is deliberately subtle. + s3_acc <= s2_two_u - s2_su1 + mul_coeff(s2_g2l,s2_lap) + - stiffness_term(s2_biharm,s2_stiff) + + hf_loss_term(s2_lapv,material); + else + s3_acc <= s2_two_u - s2_su1 + mul_coeff(s2_g2l,s2_lap) + - stiffness_term(s2_biharm,s2_stiff); + end if; s3_ucap <= s2_ucap; s3_exc <= s2_exc; s3_a0 <= s2_a0; diff --git a/src/rtl/panel_ctrl.vhd b/src/rtl/panel_ctrl.vhd index 313c911..b07e831 100644 --- a/src/rtl/panel_ctrl.vhd +++ b/src/rtl/panel_ctrl.vhd @@ -1,175 +1,251 @@ ------------------------------------------------------------------------------- --- panel_ctrl.vhd - front-panel controls -> engine (issue #78) +-- panel_ctrl.vhd - six pots + encoder with PLAY/EDIT page selection. -- --- Wires the physical panel to the engine: three macro potentiometers set the --- live coefficients, and a rotary encoder + its push-button select and recall --- presets, all via the preset_bank register / preset interface (#30, #69). +-- edit_mode=0 PLAY: TENSION / DECAY / CHAOS / DRIVE / DELAY / REVERB. +-- edit_mode=1 EDIT: encoder selects an edit page. Page 0 is SURFACE: +-- ANISO / RIM / STRIKE SIZE / STRIKE X / STRIKE Y / CHARACTER. +-- Additional edit pages are deliberately reserved for follow-up features. -- --- pot_pitch -> gamma2 (reg 0) pitch / tension --- pot_decay -> sigk1 (reg 2) + a0 (reg 1) decay time (a0 ~= sigk1 for the --- small sigma*k a knob spans) --- pot_timbre -> alpha (reg 3) chaos coupling / timbre --- encoder -> preset_index (turn), button short = recall, long = save --- --- Each pot is scaled from its ADC range into a per-register Q1.23 range and --- written on change only (a dead-band rejects ADC LSB jitter), one register per --- scan step, so the single-port register bus is never flooded. After a preset --- recall the live registers hold the recalled values until a knob is actually --- moved (its target then differs from the last panel write and takes over) - --- simple "pickup" behaviour. --- --- ADC pot samples are assumed synchronous to clk; the encoder and button are --- brought in through two-flop synchronisers. --- --- Synthesisable VHDL-2008. +-- Every pot uses read-back based soft takeover. After reset, preset recall, +-- PLAY/EDIT changes, or EDIT-page changes, a pot must cross the stored value +-- before it can write. ------------------------------------------------------------------------------- - library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; - +use ieee.math_real.all; library work; use work.fdtd_pkg.all; entity panel_ctrl is generic ( - POT_W : positive := 12; -- ADC width - N_PRESETS : positive := 7; -- selectable presets (3 factory + 4 user) - DEADBAND : natural := 4096; -- Q1.23 LSB dead-band on pot writes - LONG_CYC : positive := 50_000_000; -- long-press threshold (~0.5 s @100 MHz) - -- per-pot Q1.23 mapping ranges - PITCH_LO : real := 0.02; PITCH_HI : real := 0.44; -- gamma2 - DECAY_LO : real := 0.9950; DECAY_HI : real := 0.99999;-- sigk1 / a0 - TIMBRE_LO : real := 0.0; TIMBRE_HI : real := 0.40 -- alpha + FS_HZ : positive := 48_000; OS : positive := 4; + POT_W : positive := 12; N_PRESETS : positive := 7; + N_EDIT_PAGES : positive := 1; -- 1..4; page 0 is SURFACE + DEADBAND : natural := 4096; FX_DEADBAND : natural := 2; + LONG_CYC : positive := 50_000_000; + PITCH_LO : real := 0.0625; PITCH_HI : real := 1.0-2.0**(-23); + DECAY_LO : real := exp(-20.0/real(FS_HZ*OS)); + DECAY_HI : real := exp(-0.8/real(FS_HZ*OS)); + TIMBRE_LO : real := 0.0; TIMBRE_HI : real := 0.40 ); port ( - clk : in std_logic; - rst : in std_logic; - -- panel inputs - pot_pitch : in unsigned(POT_W-1 downto 0); - pot_decay : in unsigned(POT_W-1 downto 0); - pot_timbre : in unsigned(POT_W-1 downto 0); - enc_a : in std_logic; - enc_b : in std_logic; - enc_btn : in std_logic; - -- to preset_bank: register edit + preset control - cfg_wr_en : out std_logic; - cfg_wr_addr : out unsigned(3 downto 0); - cfg_wr_data : out std_logic_vector(23 downto 0); + clk, rst : in std_logic; + edit_mode : in std_logic := '0'; -- 0=PLAY, 1=EDIT + pot_pitch, pot_decay, pot_timbre : in unsigned(POT_W-1 downto 0); + pot_drive, pot_delay, pot_reverb : in unsigned(POT_W-1 downto 0); + enc_a, enc_b, enc_btn : in std_logic; + cfg_wr_en : out std_logic; cfg_wr_addr : out unsigned(3 downto 0); + cfg_wr_data : out std_logic_vector(23 downto 0); + cfg_rd_addr : out unsigned(3 downto 0); + cfg_rd_data : in std_logic_vector(23 downto 0); preset_index : out unsigned(3 downto 0); - preset_recall: out std_logic; - preset_save : out std_logic + preset_recall, preset_save : out std_logic; + edit_page : out unsigned(1 downto 0); + edit_leds : out std_logic_vector(3 downto 0) ); end entity panel_ctrl; architecture rtl of panel_ctrl is - - constant PITCH_LO_Q : q123_t := to_q123(PITCH_LO); - constant PITCH_SPAN : q123_t := to_q123(PITCH_HI - PITCH_LO); - constant DECAY_LO_Q : q123_t := to_q123(DECAY_LO); - constant DECAY_SPAN : q123_t := to_q123(DECAY_HI - DECAY_LO); - constant TIMBRE_LO_Q : q123_t := to_q123(TIMBRE_LO); - constant TIMBRE_SPAN : q123_t := to_q123(TIMBRE_HI - TIMBRE_LO); - - -- q = lo + span * pot / 2^POT_W - function scale_pot(pot : unsigned; lo, span : q123_t) return q123_t is - variable p : signed(span'length + POT_W downto 0); + constant PITCH_LO_Q:q123_t:=to_q123(PITCH_LO); + constant PITCH_SPAN:q123_t:=to_q123(PITCH_HI-PITCH_LO); + constant DECAY_LO_Q:q123_t:=to_q123(DECAY_LO); + constant DECAY_SPAN:q123_t:=to_q123(DECAY_HI-DECAY_LO); + constant TIMBRE_LO_Q:q123_t:=to_q123(TIMBRE_LO); + constant TIMBRE_SPAN:q123_t:=to_q123(TIMBRE_HI-TIMBRE_LO); + + type scan_state_t is (SCAN_REQ,SCAN_WAIT,SCAN_EVAL,WRITE_DECAY); + signal scan_state:scan_state_t:=SCAN_REQ; + signal scan_idx:integer range 0 to 5:=0; + signal armed,side_valid,side_pos:std_logic_vector(5 downto 0):=(others=>'0'); + signal mode_d:std_logic:='0'; + signal holdoff:integer range 0 to 4:=0; + signal decay_second:q123_t:=Q123_ZERO; + + signal a_s,b_s:std_logic_vector(1 downto 0):=(others=>'0'); + signal a_d:std_logic:='0'; signal btn_s:std_logic_vector(1 downto 0):=(others=>'0'); + signal idx:unsigned(3 downto 0):=(others=>'0'); + signal edit_idx:integer range 0 to 3:=0; + signal held:integer range 0 to LONG_CYC:=0; signal saved:std_logic:='0'; + signal btn_blocked:std_logic:='0'; + + function scale_pot(pot:unsigned;lo,span:q123_t) return q123_t is + variable p:signed(span'length+POT_W downto 0); + begin p:=span*signed('0'&pot); return sat_add(lo,resize(shift_right(p,POT_W),Q_BITS)); end; + function byte_pot(pot:unsigned) return unsigned is + begin return resize(pot(POT_W-1 downto POT_W-8),8); end; + function pot_sel(i:integer; p0,p1,p2,p3,p4,p5:unsigned) return unsigned is begin - p := span * signed('0' & pot); - return sat_add(lo, resize(shift_right(p, POT_W), Q_BITS)); - end function; - - -- scan list: 4 register writes (addr + which pot maps to it) - type addr_arr is array (0 to 3) of unsigned(3 downto 0); - constant REG_ADDR : addr_arr := (x"0", x"2", x"1", x"3"); -- gamma2, sigk1, a0, alpha - type q_arr is array (0 to 3) of q123_t; - signal last : q_arr := (others => (others => '0')); - signal sel : integer range 0 to 3 := 0; - - -- encoder + button synchronisers - signal a_s, b_s : std_logic_vector(1 downto 0) := (others => '0'); - signal a_d : std_logic := '0'; -- synced-A delayed 1 cycle (edge det) - signal btn_s : std_logic_vector(1 downto 0) := (others => '0'); - signal idx : unsigned(3 downto 0) := (others => '0'); - signal held : integer range 0 to LONG_CYC := 0; - signal saved : std_logic := '0'; - - function pot_for(s : integer; pp, pd, pt : unsigned) return q123_t is + case i is when 0=>return p0; when 1=>return p1; when 2=>return p2; + when 3=>return p3; when 4=>return p4; when others=>return p5; end case; + end; + function perf_q(i:integer; p0,p1,p2:unsigned) return q123_t is + variable pv:unsigned(POT_W-1 downto 0); variable lo,span:q123_t; + variable prod:signed(Q_BITS+POT_W downto 0); begin - case s is - when 0 => return scale_pot(pp, PITCH_LO_Q, PITCH_SPAN); -- gamma2 - when 1 => return scale_pot(pd, DECAY_LO_Q, DECAY_SPAN); -- sigk1 - when 2 => return scale_pot(pd, DECAY_LO_Q, DECAY_SPAN); -- a0 (= sigk1) - when others => return scale_pot(pt, TIMBRE_LO_Q, TIMBRE_SPAN); -- alpha + case i is + when 0=>pv:=p0;lo:=PITCH_LO_Q;span:=PITCH_SPAN; + when 1=>pv:=p1;lo:=DECAY_LO_Q;span:=DECAY_SPAN; + when others=>pv:=p2;lo:=TIMBRE_LO_Q;span:=TIMBRE_SPAN; end case; - end function; - + -- One shared multiplier after the scanner mux, instead of one multiplier + -- per Performance macro branch. + prod:=span*signed('0'&pv); + return sat_add(lo,resize(shift_right(prod,POT_W),Q_BITS)); + end; + function perf_addr(i:integer) return unsigned is + begin case i is when 0=>return x"0"; when 1=>return x"2"; when 2=>return x"3"; + when 3=>return x"A"; when 4=>return x"C"; when others=>return x"E"; end case; end; + function membrane_addr(i:integer) return unsigned is + begin case i is when 0=>return x"9"; when 1=>return x"5"; when 2=>return x"6"; + when 3=>return x"7"; when 4=>return x"8"; when others=>return x"9"; end case; end; + function aniso_pot(p:unsigned) return integer is + begin return to_integer(p(POT_W-1 downto POT_W-4))-8; end; + function char_pot(p:unsigned) return integer is variable v:integer; + begin v:=to_integer(p(POT_W-1 downto POT_W-3)); if v>5 then v:=5; end if; return v; end; begin - - preset_index <= idx; - - process (clk) - variable target : q123_t; - variable diff : integer; + assert POT_W>=8 report "panel_ctrl requires POT_W >= 8" severity failure; + assert N_EDIT_PAGES<=4 report "panel_ctrl supports at most four EDIT pages" severity failure; + preset_index<=idx; + edit_page<=to_unsigned(edit_idx,edit_page'length); + edit_leds<=std_logic_vector(shift_left(to_unsigned(1,4),edit_idx)) + when edit_mode='1' else (others=>'0'); + + process(clk) + variable potv:unsigned(POT_W-1 downto 0); + variable qv:q123_t; variable bv:unsigned(7 downto 0); + variable cand,cur,diff,thr:integer; variable crossing,write_now:boolean; + variable w:std_logic_vector(23 downto 0); begin if rising_edge(clk) then - if rst = '1' then - cfg_wr_en <= '0'; cfg_wr_addr <= (others => '0'); cfg_wr_data <= (others => '0'); - preset_recall <= '0'; preset_save <= '0'; - last <= (others => (others => '0')); - sel <= 0; idx <= (others => '0'); held <= 0; saved <= '0'; - a_s <= "00"; b_s <= "00"; a_d <= '0'; btn_s <= "00"; + cfg_wr_en<='0'; preset_recall<='0'; preset_save<='0'; + if rst='1' then + cfg_wr_addr<=(others=>'0');cfg_wr_data<=(others=>'0');cfg_rd_addr<=(others=>'0'); + scan_state<=SCAN_REQ;scan_idx<=0;armed<=(others=>'0');side_valid<=(others=>'0'); + side_pos<=(others=>'0');mode_d<='0';holdoff<=2;decay_second<=Q123_ZERO; + idx<=(others=>'0');edit_idx<=0;held<=0;saved<='0';btn_blocked<='0'; + a_s<="00";b_s<="00";a_d<='0';btn_s<="00"; else - -- synchronise async panel inputs (2FF), plus a 1-cycle delay of synced A - a_s <= a_s(0) & enc_a; - b_s <= b_s(0) & enc_b; - a_d <= a_s(1); - btn_s <= btn_s(0) & enc_btn; - - cfg_wr_en <= '0'; - preset_recall <= '0'; - preset_save <= '0'; - - -------------------------------------------------------------------- - -- pot scan: write one register per cycle, on change only - -------------------------------------------------------------------- - target := pot_for(sel, pot_pitch, pot_decay, pot_timbre); - diff := to_integer(target) - to_integer(last(sel)); - if diff > DEADBAND or diff < -DEADBAND then - cfg_wr_en <= '1'; - cfg_wr_addr <= REG_ADDR(sel); - cfg_wr_data <= std_logic_vector(target); - last(sel) <= target; + a_s<=a_s(0)&enc_a;b_s<=b_s(0)&enc_b;a_d<=a_s(1);btn_s<=btn_s(0)&enc_btn; + + if edit_mode/=mode_d then + mode_d<=edit_mode; armed<=(others=>'0'); side_valid<=(others=>'0'); + scan_idx<=0; scan_state<=SCAN_REQ; holdoff<=2; + held<=0; saved<='0'; btn_blocked<='1'; + elsif holdoff>0 then + holdoff<=holdoff-1; scan_state<=SCAN_REQ; + else + case scan_state is + when SCAN_REQ => + if edit_mode='0' then + cfg_rd_addr<=perf_addr(scan_idx); scan_state<=SCAN_WAIT; + elsif edit_idx=0 then + cfg_rd_addr<=membrane_addr(scan_idx); scan_state<=SCAN_WAIT; + else + -- Reserved EDIT pages are inert until their backing features + -- land; selecting one must never alias the SURFACE registers. + scan_idx<=0; scan_state<=SCAN_REQ; + end if; + when SCAN_WAIT => + if edit_mode='1' and edit_idx/=0 then scan_state<=SCAN_REQ; + else scan_state<=SCAN_EVAL; end if; + when SCAN_EVAL => + potv:=pot_sel(scan_idx,pot_pitch,pot_decay,pot_timbre,pot_drive,pot_delay,pot_reverb); + thr:=0; cand:=0; cur:=0; + if edit_mode='0' and scan_idx<=2 then + qv:=perf_q(scan_idx,pot_pitch,pot_decay,pot_timbre); + cand:=to_integer(qv);cur:=to_integer(signed(cfg_rd_data)); + if scan_idx=1 then thr:=1; else thr:=integer(DEADBAND); end if; + elsif edit_mode='0' then + bv:=byte_pot(potv);cand:=to_integer(bv);thr:=integer(FX_DEADBAND); + case scan_idx is + when 3=>cur:=to_integer(unsigned(cfg_rd_data(17 downto 10))); + when others=>cur:=to_integer(unsigned(cfg_rd_data(7 downto 0))); + end case; + elsif scan_idx=0 then + cand:=aniso_pot(potv);cur:=to_integer(signed(cfg_rd_data(10 downto 7)));thr:=0; + elsif scan_idx=5 then + cand:=char_pot(potv);cur:=to_integer(unsigned(cfg_rd_data(6 downto 4)));thr:=0; + else + bv:=byte_pot(potv);cand:=to_integer(bv);cur:=to_integer(unsigned(cfg_rd_data(15 downto 8))); + thr:=integer(FX_DEADBAND); + end if; + diff:=cand-cur; write_now:=false; crossing:=false; + if armed(scan_idx)='1' then + if diff>thr or diff< -thr then write_now:=true; end if; + elsif diff<=thr and diff>=-thr then armed(scan_idx)<='1'; + elsif side_valid(scan_idx)='0' then + side_valid(scan_idx)<='1'; if diff>0 then side_pos(scan_idx)<='1'; else side_pos(scan_idx)<='0'; end if; + else + crossing:=(diff>0 and side_pos(scan_idx)='0') or (diff<0 and side_pos(scan_idx)='1'); + if crossing then armed(scan_idx)<='1'; write_now:=true; end if; + end if; + + if write_now then + if edit_mode='0' and scan_idx<=2 then + qv:=perf_q(scan_idx,pot_pitch,pot_decay,pot_timbre); + cfg_wr_en<='1';cfg_wr_addr<=perf_addr(scan_idx);cfg_wr_data<=std_logic_vector(qv); + if scan_idx=1 then decay_second<=qv;scan_state<=WRITE_DECAY; + else if scan_idx=5 then scan_idx<=0; else scan_idx<=scan_idx+1; end if;scan_state<=SCAN_REQ;end if; + else + w:=cfg_rd_data; + if edit_mode='0' then + bv:=byte_pot(potv); + if scan_idx=3 then w(17 downto 10):=std_logic_vector(bv); else w(7 downto 0):=std_logic_vector(bv); end if; + elsif scan_idx=0 then + w(10 downto 7):=std_logic_vector(to_signed(aniso_pot(potv),4)); + elsif scan_idx=5 then + w(6 downto 4):=std_logic_vector(to_unsigned(char_pot(potv),3)); + else + w(15 downto 8):=std_logic_vector(byte_pot(potv)); + end if; + cfg_wr_en<='1'; if edit_mode='0' then cfg_wr_addr<=perf_addr(scan_idx);else cfg_wr_addr<=membrane_addr(scan_idx);end if; + cfg_wr_data<=w; + if scan_idx=5 then scan_idx<=0;else scan_idx<=scan_idx+1;end if;scan_state<=SCAN_REQ; + end if; + else + if scan_idx=5 then scan_idx<=0;else scan_idx<=scan_idx+1;end if;scan_state<=SCAN_REQ; + end if; + when WRITE_DECAY => + cfg_wr_en<='1';cfg_wr_addr<=x"1";cfg_wr_data<=std_logic_vector(decay_second); + if scan_idx=5 then scan_idx<=0;else scan_idx<=scan_idx+1;end if;scan_state<=SCAN_REQ; + end case; end if; - if sel = 3 then sel <= 0; else sel <= sel + 1; end if; - -------------------------------------------------------------------- - -- encoder: 1 step per rising edge of A, direction from B - -------------------------------------------------------------------- - if a_s(1) = '1' and a_d = '0' then -- A rising edge (1 cycle) - if b_s(1) = '0' then - if idx < N_PRESETS-1 then idx <= idx + 1; end if; - else - if idx > 0 then idx <= idx - 1; end if; + -- Encoder is contextual: presets in PLAY, EDIT pages in EDIT. + if a_s(1)='1' and a_d='0' then + if edit_mode='0' then + if b_s(1)='0' then if idx0 then idx<=idx-1;end if;end if; + elsif N_EDIT_PAGES>1 then + if b_s(1)='0' then + if edit_idx=N_EDIT_PAGES-1 then edit_idx<=0; else edit_idx<=edit_idx+1; end if; + else + if edit_idx=0 then edit_idx<=N_EDIT_PAGES-1; else edit_idx<=edit_idx-1; end if; + end if; + armed<=(others=>'0'); side_valid<=(others=>'0'); + scan_idx<=0; scan_state<=SCAN_REQ; holdoff<=2; end if; end if; - -------------------------------------------------------------------- - -- button: short press = recall, long press = save - -------------------------------------------------------------------- - if btn_s(1) = '1' then -- held - if held = LONG_CYC then - if saved = '0' then preset_save <= '1'; saved <= '1'; end if; - else - held <= held + 1; + -- Preset button gestures exist only in PLAY. Any press made in EDIT + -- stays blocked until the physical button is released after returning + -- to PLAY, preventing an EDIT gesture from becoming a recall/save. + if edit_mode='1' then + held<=0; saved<='0'; btn_blocked<='1'; + elsif btn_blocked='1' then + held<=0; saved<='0'; + if btn_s(1)='0' then btn_blocked<='0'; end if; + elsif btn_s(1)='1' then + if held=LONG_CYC then if saved='0' then preset_save<='1';saved<='1';end if; + else held<=held+1;end if; + else + if held>0 and saved='0' then + preset_recall<='1'; armed<=(others=>'0');side_valid<=(others=>'0');holdoff<=3;scan_state<=SCAN_REQ; end if; - else -- released - if held > 0 and saved = '0' then preset_recall <= '1'; end if; - held <= 0; - saved <= '0'; + held<=0;saved<='0'; end if; end if; end if; end process; - end architecture rtl; diff --git a/src/rtl/physical_mallet.vhd b/src/rtl/physical_mallet.vhd new file mode 100644 index 0000000..cb0e2f6 --- /dev/null +++ b/src/rtl/physical_mallet.vhd @@ -0,0 +1,89 @@ +------------------------------------------------------------------------------- +-- physical_mallet.vhd - stateful bidirectional lumped contact exciter (#87) +-- +-- Normalized hammer dynamics: +-- eta = hammer_x - surface_u +-- F ~= hardness * [eta]_+^2 +-- v' = v - F/128 +-- x' = x + v' +-- +-- physical_pkg implements the power-law approximation and hardness scaling +-- with shifts/adds only. No DSP multiplier is required. force_out is a +-- separately normalized surface-force unit conversion; the raw contact force +-- drives the hammer reaction. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.fdtd_pkg.all; +use work.physical_pkg.all; + +entity physical_mallet is + generic (MAX_AGE : positive := 2047); + port ( + clk, rst : in std_logic; + enable : in std_logic := '0'; + step : in std_logic; + trigger : in std_logic := '0'; + strike_velocity : in q123_t := Q123_ZERO; + hardness : in unsigned(7 downto 0) := (others=>'0'); + surface_u : in q123_t := Q123_ZERO; + force_out : out q123_t; + contact : out std_logic; + active : out std_logic; + hammer_x : out q123_t; + hammer_v : out q123_t + ); +end entity; + +architecture rtl of physical_mallet is + constant GAP : q123_t := to_q123(0.008); + signal hx : q123_t := Q123_ZERO; + signal hv : q123_t := Q123_ZERO; + signal running : std_logic := '0'; + signal touched : std_logic := '0'; + signal age : natural range 0 to MAX_AGE := 0; + signal compression, raw_force : q123_t := Q123_ZERO; +begin + compression <= sat_store(to_acc(hx)-to_acc(surface_u)) + when running='1' else Q123_ZERO; + raw_force <= mallet_contact_force(compression,hardness) + when running='1' and enable='1' else Q123_ZERO; + force_out <= sat_store(shift_left(to_acc(raw_force),4)) + when running='1' and enable='1' else Q123_ZERO; + contact <= '1' when running='1' and raw_force>Q123_ZERO else '0'; + active<=running; hammer_x<=hx; hammer_v<=hv; + + process(clk) + variable vnext,launch:q123_t; + begin + if rising_edge(clk) then + if rst='1' or enable='0' then + hx<=Q123_ZERO; hv<=Q123_ZERO; running<='0'; touched<='0'; age<=0; + elsif step='1' then + if trigger='1' then + launch:=mallet_launch_velocity(strike_velocity); + hx<=sat_store(to_acc(surface_u)-to_acc(GAP)); + hv<=launch; touched<='0'; age<=0; + if launch=Q123_ZERO or hardness=0 then running<='0'; + else running<='1'; end if; + elsif running='1' then + vnext:=sat_store(to_acc(hv)-shift_right(to_acc(raw_force),7)); + hv<=vnext; + hx<=sat_store(to_acc(hx)+to_acc(vnext)); + if raw_force>Q123_ZERO then + touched<='1'; + elsif touched='1' then + running<='0'; + end if; + if age=MAX_AGE then + running<='0'; + else + age<=age+1; + end if; + end if; + end if; + end if; + end process; +end architecture; diff --git a/src/rtl/physical_pkg.vhd b/src/rtl/physical_pkg.vhd new file mode 100644 index 0000000..deaea25 --- /dev/null +++ b/src/rtl/physical_pkg.vhd @@ -0,0 +1,313 @@ +------------------------------------------------------------------------------- +-- physical_pkg.vhd - shared low-cost physical-model helpers. +-- +-- New physical controls deliberately use shift/add arithmetic so anisotropy, +-- sub-grid interpolation and material shaping do not consume another bank of +-- DSP multipliers. All-zero control fields preserve the existing musical path. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.fdtd_pkg.all; + +package physical_pkg is + subtype frac2_t is unsigned(1 downto 0); + subtype material_t is unsigned(2 downto 0); + subtype exciter_t is unsigned(2 downto 0); + subtype aniso_t is signed(3 downto 0); + + function lerp_quarter(a,b:q123_t; f:frac2_t) return q123_t; + function bilerp_quarter(a00,a10,a01,a11:q123_t; + fx,fy:frac2_t) return q123_t; + function frac_weight(fx,fy:frac2_t; dx,dy:natural) return natural; + function scale_sixteenth(x:q123_t; w:natural) return q123_t; + function rim_neighbor(x:q123_t; free_mode:boolean; rim:unsigned(7 downto 0)) return q123_t; + function footprint_weight(size:unsigned(7 downto 0); dx,dy:integer; + fx,fy:frac2_t) return natural; + function effective_aniso(user:aniso_t; material:material_t) return aniso_t; + function anisotropic_lap(lapx,lapy:acc_t; a:aniso_t) return acc_t; + -- STIFFNESS is stored as an unsigned byte. Production encoding is + -- mu2 = ctrl / 4096, spanning 0 .. 255/4096 ~= 0.06226 (near pure plate). + function stiffness_mu2(ctrl:unsigned(7 downto 0)) return q123_t; + function stiff_gamma2_max(base_max:q123_t; ctrl:unsigned(7 downto 0)) return q123_t; + function biharmonic_term(c,n,s,e,w,ne,nw,se,sw,nn,ss,ee,ww:q123_t) return acc_t; + function stiffness_term(biharm:acc_t; ctrl:unsigned(7 downto 0)) return acc_t; + -- Multiplier-free physical mallet helpers (#87). The contact law is a + -- piecewise-leading-bit approximation to eta^2, scaled continuously by the + -- 8-bit HARDNESS control. The mesh coupling scale is applied once in + -- physical_mallet after this raw contact force is computed. + function mallet_contact_force(compression:q123_t; hardness:unsigned(7 downto 0)) return q123_t; + function mallet_launch_velocity(strike:q123_t) return q123_t; + function hf_loss_term(delta:acc_t; material:material_t) return acc_t; + function material_alpha(x:q123_t; material:material_t) return q123_t; + function effective_exciter(user:exciter_t; material:material_t) return exciter_t; +end package; +package body physical_pkg is + function lerp_quarter(a,b:q123_t; f:frac2_t) return q123_t is + variable d,y:acc_t; + begin + if is_x(std_logic_vector(a)) or is_x(std_logic_vector(b)) or is_x(std_logic_vector(f)) then return Q123_ZERO; end if; + d:=to_acc(b)-to_acc(a); y:=to_acc(a); + case to_integer(f) is + when 1 => y:=y+shift_right(d,2); + when 2 => y:=y+shift_right(d,1); + when 3 => y:=y+shift_right(d,1)+shift_right(d,2); + when others => null; + end case; + return sat_store(y); + end; + + function bilerp_quarter(a00,a10,a01,a11:q123_t; + fx,fy:frac2_t) return q123_t is + variable lo,hi:q123_t; + begin + lo:=lerp_quarter(a00,a10,fx); + hi:=lerp_quarter(a01,a11,fx); + return lerp_quarter(lo,hi,fy); + end; + + function frac_weight(fx,fy:frac2_t; dx,dy:natural) return natural is + variable x,y:natural; + begin + if is_x(std_logic_vector(fx)) or is_x(std_logic_vector(fy)) then return 0; end if; + if dx=0 then x:=4-to_integer(fx); else x:=to_integer(fx); end if; + if dy=0 then y:=4-to_integer(fy); else y:=to_integer(fy); end if; + case x is + when 0 => return 0; + when 1 => return y; + when 2 => return y+y; + when 3 => return y+y+y; + when others => return y+y+y+y; + end case; + end; + function scale_sixteenth(x:q123_t; w:natural) return q123_t is + variable a,y:acc_t; + begin + if is_x(std_logic_vector(x)) then return Q123_ZERO; end if; + a:=to_acc(x); y:=(others=>'0'); + case w is + when 1=>y:=shift_right(a,4); when 2=>y:=shift_right(a,3); + when 3=>y:=shift_right(a,3)+shift_right(a,4); when 4=>y:=shift_right(a,2); + when 5=>y:=shift_right(a,2)+shift_right(a,4); when 6=>y:=shift_right(a,2)+shift_right(a,3); + when 7=>y:=shift_right(a,2)+shift_right(a,3)+shift_right(a,4); when 8=>y:=shift_right(a,1); + when 9=>y:=shift_right(a,1)+shift_right(a,4); when 10=>y:=shift_right(a,1)+shift_right(a,3); + when 11=>y:=shift_right(a,1)+shift_right(a,3)+shift_right(a,4); when 12=>y:=shift_right(a,1)+shift_right(a,2); + when 13=>y:=shift_right(a,1)+shift_right(a,2)+shift_right(a,4); + when 14=>y:=shift_right(a,1)+shift_right(a,2)+shift_right(a,3); + when 15=>y:=a-shift_right(a,4); when 16=>y:=a; when others=>null; + end case; + return sat_store(y); + end; + + function rim_neighbor(x:q123_t; free_mode:boolean; rim:unsigned(7 downto 0)) return q123_t is + variable w:natural; + begin + if rim=0 then + if free_mode then return x; else return Q123_ZERO; end if; + end if; + if rim=x"FF" then return x; end if; + w:=to_integer(rim(7 downto 4)); + return scale_sixteenth(x,w); + end; + + function footprint_weight(size:unsigned(7 downto 0); dx,dy:integer; + fx,fy:frac2_t) return natural is + variable tier:natural; + begin + if is_x(std_logic_vector(size)) then tier:=0; else tier:=to_integer(size(7 downto 6)); end if; + if tier=0 then + if (dx=0 or dx=1) and (dy=0 or dy=1) then + return frac_weight(fx,fy,natural(dx),natural(dy)); + else return 0; end if; + elsif tier=1 then + if dx=0 and dy=0 then return 8; + elsif ((dx=1 or dx=-1) and dy=0) or ((dy=1 or dy=-1) and dx=0) then return 2; + else return 0; end if; + elsif tier=2 then + if dx=0 and dy=0 then return 4; + elsif ((dx=1 or dx=-1) and dy=0) or ((dy=1 or dy=-1) and dx=0) then return 2; + elsif (dx=1 or dx=-1) and (dy=1 or dy=-1) then return 1; + else return 0; end if; + else + -- Wide 13-node footprint: 3x3 unit skirt + four radius-2 axes. + if dx=0 and dy=0 then return 4; + elsif (dx>=-1 and dx<=1 and dy>=-1 and dy<=1) then return 1; + elsif ((dx=2 or dx=-2) and dy=0) or ((dy=2 or dy=-2) and dx=0) then return 1; + else return 0; end if; + end if; + end; + + function effective_aniso(user:aniso_t; material:material_t) return aniso_t is + variable v,b:integer; + begin + if is_x(std_logic_vector(user)) or is_x(std_logic_vector(material)) then return (others=>'0'); end if; + v:=to_integer(user); + case to_integer(material) is + when 2 => b:=2; -- wood: mild grain direction + when 3 => b:=-3; -- metal: opposite-axis split + when 4 => b:=5; -- glass: stronger modal split + when others => b:=0; + end case; + v:=v+b; if v>7 then v:=7; elsif v< -8 then v:=-8; end if; + return to_signed(v,4); + end; + function anisotropic_lap(lapx,lapy:acc_t; a:aniso_t) return acc_t is + variable base,d,adj:acc_t; variable k:integer; + begin + base:=lapx+lapy; d:=lapx-lapy; adj:=(others=>'0'); k:=to_integer(a); + case k is + when 1 => adj:=shift_right(d,5); + when 2 => adj:=shift_right(d,4); + when 3 => adj:=shift_right(d,4)+shift_right(d,5); + when 4 => adj:=shift_right(d,3); + when 5 => adj:=shift_right(d,3)+shift_right(d,5); + when 6 => adj:=shift_right(d,3)+shift_right(d,4); + when 7 => adj:=shift_right(d,3)+shift_right(d,4)+shift_right(d,5); + when -1 => adj:=-shift_right(d,5); + when -2 => adj:=-shift_right(d,4); + when -3 => adj:=-shift_right(d,4)-shift_right(d,5); + when -4 => adj:=-shift_right(d,3); + when -5 => adj:=-shift_right(d,3)-shift_right(d,5); + when -6 => adj:=-shift_right(d,3)-shift_right(d,4); + when -7 => adj:=-shift_right(d,3)-shift_right(d,4)-shift_right(d,5); + when -8 => adj:=-shift_right(d,2); + when others => null; + end case; + return base+adj; + end; + function stiffness_mu2(ctrl:unsigned(7 downto 0)) return q123_t is + variable q:q123_t; + begin + if is_x(std_logic_vector(ctrl)) then return Q123_ZERO; end if; + -- q123(ctrl / 4096) = ctrl * 2^(23-12) = ctrl << 11. + q:=signed(resize(ctrl,Q_BITS)); + return shift_left(q,11); + end; + + function stiff_gamma2_max(base_max:q123_t; ctrl:unsigned(7 downto 0)) return q123_t is + variable allowed_i:signed(Q_BITS downto 0); + variable allowed:q123_t; + begin + if is_x(std_logic_vector(base_max)) or is_x(std_logic_vector(ctrl)) then return Q123_ZERO; end if; + -- Isotropic/axis-biased RADIAN keeps g2x+g2y = 2*g2. The stiff CFL bound + -- 2*g2 + 16*mu2 <= 1 therefore gives g2 <= 0.5 - 8*mu2. + -- With mu2=ctrl/4096, Q1.23 allowed = 2^22 - ctrl*2^14 exactly. + allowed_i:=to_signed(2**22,Q_BITS+1) + - shift_left(resize(signed('0' & std_logic_vector(ctrl)),Q_BITS+1),14); + if allowed_i<=0 then return Q123_ZERO; end if; + allowed:=resize(allowed_i,Q_BITS); + if allowed'0'); + end if; + -- Exact product for the production encoding mu2=ctrl/4096, implemented as + -- eight static shift/add terms so this control does not claim another DSP. + base:=resize(biharm,wide_t'length); sum:=(others=>'0'); + for b in 0 to 7 loop + if ctrl(b)='1' then sum:=sum+shift_left(base,b); end if; + end loop; + -- Match mul_coeff's round-then-arithmetic-shift convention at /4096. + rounded:=shift_right(sum+to_signed(2**11,wide_t'length),12); + return resize(rounded,ACC_BITS); + end; + + function mallet_contact_force(compression:q123_t; hardness:unsigned(7 downto 0)) return q123_t is + variable sq_approx:q123_t:=Q123_ZERO; + variable base,sum,scaled:acc_t; + variable found:boolean:=false; + begin + if is_x(std_logic_vector(compression)) or is_x(std_logic_vector(hardness)) + or compression<=Q123_ZERO or hardness=0 then return Q123_ZERO; end if; + + -- Multiplier-free eta^2 approximation. If the leading one is bit p, eta + -- lies in [2^(p-23), 2^(p-22)); eta*2^(p-23) approximates eta^2 within + -- a factor <2, with continuous piecewise-linear segments. + for p in 22 downto 0 loop + if not found and compression(p)='1' then + sq_approx:=shift_right(compression,FRAC-p); + found:=true; + end if; + end loop; + if not found then return Q123_ZERO; end if; + + -- Continuous HARDNESS gain: (32 + h)/64 = 0.5 .. 4.484375. + -- The h multiplication is eight static shift/add terms, not a DSP. + base:=to_acc(sq_approx); sum:=(others=>'0'); + for b in 0 to 7 loop + if hardness(b)='1' then sum:=sum+shift_left(base,b); end if; + end loop; + scaled:=shift_right(base,1)+shift_right(sum+to_signed(32,ACC_BITS),6); + return sat_store(scaled); + end; + + function mallet_launch_velocity(strike:q123_t) return q123_t is + variable a:acc_t; variable mag:q123_t; + begin + if is_x(std_logic_vector(strike)) then return Q123_ZERO; end if; + a:=to_acc(strike); + if a<0 then a:=-a; end if; + mag:=sat_store(a); + -- Velocity is displacement per oversampled mesh step. It depends only on + -- strike energy/velocity, never HARDNESS. + return shift_right(mag,9); + end; + + function hf_loss_term(delta:acc_t; material:material_t) return acc_t is + begin + if is_x(std_logic_vector(material)) then return shift_right(delta,7); end if; + case to_integer(material) is + when 2 => return shift_right(delta,6); -- wood: fastest HF loss + when 3 => return shift_right(delta,8); -- metal: long bright ring + when 4 => return shift_right(delta,9); -- glass: longest HF ring + when others => return shift_right(delta,7); -- current/neutral + membrane + end case; + end; + + function material_alpha(x:q123_t; material:material_t) return q123_t is + variable a,y:acc_t; + begin + if is_x(std_logic_vector(x)) then return Q123_ZERO; end if; + if is_x(std_logic_vector(material)) then return x; end if; + a:=to_acc(x); y:=a; + case to_integer(material) is + when 1 => y:=a-shift_right(a,2); -- membrane: smoother / more linear + when 2 => y:=a-shift_right(a,3); -- wood + when 3 => y:=a+shift_right(a,2); -- metal + when 4 => y:=a+shift_right(a,1); -- glass + when others => null; + end case; + return sat_store(y); + end; + + function effective_exciter(user:exciter_t; material:material_t) return exciter_t is + begin + if is_x(std_logic_vector(user)) or is_x(std_logic_vector(material)) then return (others=>'0'); end if; + if user/=0 then return user; end if; + case to_integer(material) is + when 1 => return to_unsigned(2,3); -- soft mallet + when 2 => return to_unsigned(2,3); -- broad wooden mallet + when 3 => return to_unsigned(4,3); -- rim/hard impulse + when 4 => return to_unsigned(3,3); -- pluck/bipolar + when others => return to_unsigned(0,3); -- current velocity-auto behavior + end case; + end; +end package body; diff --git a/src/rtl/poly_voices.vhd b/src/rtl/poly_voices.vhd index 67b2243..64ba62b 100644 --- a/src/rtl/poly_voices.vhd +++ b/src/rtl/poly_voices.vhd @@ -28,9 +28,11 @@ use ieee.numeric_std.all; library work; use work.fdtd_pkg.all; +use work.physical_pkg.all; entity poly_voices is generic ( + MUSICAL_VOICES : boolean := false; NVOICES : positive := 4; NX : positive := 8; NY : positive := 8; @@ -39,6 +41,21 @@ entity poly_voices is TIME_MUX : boolean := false ); port ( + free_mode : in boolean := FREE_BOUNDARY; + tap_lx : in natural range 0 to NX-1 := NX/4; + tap_ly : in natural range 0 to NY-1 := NY/2; + tap_rx : in natural range 0 to NX-1 := 3*NX/4; + tap_ry : in natural range 0 to NY-1 := NY/2; + tap_lfx,tap_lfy,tap_rfx,tap_rfy : in frac2_t := (others=>'0'); + material : in material_t := (others=>'0'); + exciter_mode : in exciter_t := (others=>'0'); + anisotropy : in aniso_t := (others=>'0'); + stiffness_ctrl : in unsigned(7 downto 0) := (others=>'0'); + hardness_ctrl : in unsigned(7 downto 0) := (others=>'0'); + rim_ctrl,strike_size : in unsigned(7 downto 0) := (others=>'0'); + strike_x : in natural range 0 to NX-1 := NX/3; + strike_y : in natural range 0 to NY-1 := NY/3; + strike_fx,strike_fy : in frac2_t := (others=>'0'); clk : in std_logic; rst : in std_logic; frame : in std_logic; -- per-audio-frame tick @@ -73,10 +90,58 @@ architecture rtl of poly_voices is signal vout_r : q123_arr; signal vout_v : std_logic_vector(NVOICES-1 downto 0); + type bool_arr is array (0 to NVOICES-1) of boolean; + type x_arr is array (0 to NVOICES-1) of natural range 0 to NX-1; + type y_arr is array (0 to NVOICES-1) of natural range 0 to NY-1; + type fade_arr is array (0 to NVOICES-1) of natural range 0 to 32; + type frac_arr is array (0 to NVOICES-1) of frac2_t; + type material_arr is array (0 to NVOICES-1) of material_t; + type exciter_arr is array (0 to NVOICES-1) of exciter_t; + type aniso_arr is array (0 to NVOICES-1) of aniso_t; + type byte_arr2 is array (0 to NVOICES-1) of unsigned(7 downto 0); + signal vf : bool_arr := (others=>FREE_BOUNDARY); + signal vlx : x_arr := (others=>NX/4); signal vrx : x_arr := (others=>3*NX/4); + signal vly, vry : y_arr := (others=>NY/2); + signal vlfx,vlfy,vrfx,vrfy,vsfx,vsfy : frac_arr := (others=>(others=>'0')); + signal vmat : material_arr := (others=>(others=>'0')); + signal vexmode : exciter_arr := (others=>(others=>'0')); + signal vaniso : aniso_arr := (others=>(others=>'0')); + signal vstiff,vhard,vrim,vsize : byte_arr2 := (others=>(others=>'0')); + signal vsx : x_arr := (others=>NX/3); signal vsy : y_arr := (others=>NY/3); + signal fade : fade_arr := (others=>32); + signal carry_l, carry_r : q123_arr := (others=>Q123_ZERO); + signal voice_reset, reset_pulse : std_logic_vector(NVOICES-1 downto 0) := (others=>'0'); signal strike_voice : integer range 0 to NVOICES-1; signal strike : std_logic; + signal human_lfsr : unsigned(15 downto 0) := x"ACE1"; + + function jitter_coord(base:natural; lim:positive; code:unsigned(1 downto 0)) return natural is + variable b:integer:=integer(base); variable d:integer:=0; + begin + case to_integer(code) is when 0=>d:=-1; when 2=>d:=1; when others=>d:=0; end case; + b:=b+d; if b<0 then b:=0; end if; if b>=lim then b:=lim-1; end if; + return natural(b); + end function; + function vary_strike(x:q123_t; up:boolean) return q123_t is + variable a:acc_t:=to_acc(x); variable d:acc_t; + begin + d:=shift_right(a,5); -- +/-3.125%, deterministic pseudo-human variation + if up then return sat_store(a+d); else return sat_store(a-d); end if; + end function; + + type mix_state_t is (MIX_IDLE,MIX_LEFT,MIX_RIGHT,MIX_OUT); + signal mix_state : mix_state_t := MIX_IDLE; + signal mix_idx : integer range 0 to NVOICES-1 := 0; + signal mix_al,mix_ar : acc_t := (others=>'0'); + signal fade_diff : signed(24 downto 0) := (others=>'0'); + signal fade_gain : signed(6 downto 0) := (others=>'0'); + signal fade_product : signed(31 downto 0); begin + -- One shared 25x7 multiply services every fading voice/channel over a few + -- spare system clocks after the aligned mesh outputs. A DSP48 handles this + -- efficiently; normal (fully faded-in) voices bypass it entirely. + fade_product <= fade_diff * fade_gain; ---------------------------------------------------------------------------- -- voice allocation / stealing @@ -98,16 +163,22 @@ begin vexc <= (others => (others => '0')); vexc_en <= (others => '0'); vpend <= (others => '0'); + reset_pulse<=(others=>'0'); fade<=(others=>32); + carry_l<=(others=>Q123_ZERO);carry_r<=(others=>Q123_ZERO); + vf<=(others=>FREE_BOUNDARY); human_lfsr<=x"ACE1"; + vlfx<=(others=>(others=>'0')); vlfy<=(others=>(others=>'0')); + vrfx<=(others=>(others=>'0')); vrfy<=(others=>(others=>'0')); + vsfx<=(others=>(others=>'0')); vsfy<=(others=>(others=>'0')); + vmat<=(others=>(others=>'0')); vexmode<=(others=>(others=>'0')); vaniso<=(others=>(others=>'0')); + vstiff<=(others=>(others=>'0'));vhard<=(others=>(others=>'0')); + vrim<=(others=>(others=>'0'));vsize<=(others=>(others=>'0')); + vsx<=(others=>NX/3);vsy<=(others=>NY/3); else - if strike = '1' then -- latch this note into its voice - vcoeffs(strike_voice) <= coeffs_in; - vexc(strike_voice) <= exc_in; - vpend(strike_voice) <= '1'; - end if; - + reset_pulse<=(others=>'0'); -- deliver each pending strike as one frame of exc_en if frame = '1' then for v in 0 to NVOICES-1 loop + if fade(v)<32 then fade(v)<=fade(v)+1; end if; if vpend(v) = '1' then vexc_en(v) <= '1'; vpend(v) <= '0'; @@ -116,6 +187,45 @@ begin end if; end loop; end if; + -- An arriving event wins over pending-strike consumption on this clock. + if strike = '1' then -- latch this note into its voice + vcoeffs(strike_voice) <= coeffs_in; + if MUSICAL_VOICES then + vexc(strike_voice)<=vary_strike(exc_in,human_lfsr(0)='1'); + else vexc(strike_voice)<=exc_in; end if; + vpend(strike_voice) <= '1'; + end if; + + if strike='1' then + vf(strike_voice)<=free_mode; + vlfx(strike_voice)<=tap_lfx; vlfy(strike_voice)<=tap_lfy; + vrfx(strike_voice)<=tap_rfx; vrfy(strike_voice)<=tap_rfy; + vsfx(strike_voice)<=strike_fx; vsfy(strike_voice)<=strike_fy; + vmat(strike_voice)<=material; vexmode(strike_voice)<=exciter_mode; + vaniso(strike_voice)<=anisotropy; vstiff(strike_voice)<=stiffness_ctrl; + vhard(strike_voice)<=hardness_ctrl; + vrim(strike_voice)<=rim_ctrl; vsize(strike_voice)<=strike_size; + vsx(strike_voice)<=strike_x; vsy(strike_voice)<=strike_y; + if MUSICAL_VOICES then + -- Tiny deterministic pickup motion prevents repeated strikes from + -- producing an identical modal/stereo fingerprint. + vlx(strike_voice)<=jitter_coord(tap_lx,NX,human_lfsr(2 downto 1)); + vly(strike_voice)<=jitter_coord(tap_ly,NY,human_lfsr(4 downto 3)); + vrx(strike_voice)<=jitter_coord(tap_rx,NX,human_lfsr(6 downto 5)); + vry(strike_voice)<=jitter_coord(tap_ry,NY,human_lfsr(8 downto 7)); + human_lfsr<=human_lfsr(14 downto 0) & + (human_lfsr(15) xor human_lfsr(13) xor human_lfsr(12) xor human_lfsr(10)); + else + vlx(strike_voice)<=tap_lx; vly(strike_voice)<=tap_ly; + vrx(strike_voice)<=tap_rx; vry(strike_voice)<=tap_ry; + end if; + if MUSICAL_VOICES then + reset_pulse(strike_voice)<='1'; fade(strike_voice)<=0; + carry_l(strike_voice)<=vout_l(strike_voice); + carry_r(strike_voice)<=vout_r(strike_voice); + vexc_en(strike_voice)<='0'; + end if; + end if; end if; end if; end process; @@ -124,10 +234,20 @@ begin -- the voices: NVOICES independent resonators ---------------------------------------------------------------------------- voices : for v in 0 to NVOICES-1 generate + voice_reset(v)<=rst or reset_pulse(v); u_voice : entity work.mesh_resonator generic map (NX => NX, NY => NY, OS => OS, - FREE_BOUNDARY => FREE_BOUNDARY, TIME_MUX => TIME_MUX) - port map (clk => clk, rst => rst, frame => frame, coeffs => vcoeffs(v), + FREE_BOUNDARY => FREE_BOUNDARY, TIME_MUX => TIME_MUX, + HF_DAMPING=>MUSICAL_VOICES, STRIKE_SHAPING=>MUSICAL_VOICES, + EXC_X=>NX/3,EXC_Y=>NY/3,BALANCED_FREE_STRIKE=>MUSICAL_VOICES) + port map (free_mode=>vf(v), tap_lx=>vlx(v),tap_ly=>vly(v),tap_rx=>vrx(v),tap_ry=>vry(v), + tap_lfx=>vlfx(v),tap_lfy=>vlfy(v),tap_rfx=>vrfx(v),tap_rfy=>vrfy(v), + material=>vmat(v),exciter_mode=>vexmode(v),anisotropy=>vaniso(v), + stiffness_ctrl=>vstiff(v),hardness_ctrl=>vhard(v), + rim_ctrl=>vrim(v),strike_size=>vsize(v), + strike_x=>vsx(v),strike_y=>vsy(v), + strike_fx=>vsfx(v),strike_fy=>vsfy(v), + clk => clk, rst => voice_reset(v), frame => frame, coeffs => vcoeffs(v), exc_in => vexc(v), exc_en => vexc_en(v), out_l => vout_l(v), out_r => vout_r(v), out_valid => vout_v(v)); end generate; @@ -135,26 +255,56 @@ begin ---------------------------------------------------------------------------- -- mixer: average the voices' pickups (all share `frame`, so vout_v aligns) ---------------------------------------------------------------------------- - mixer : process (clk) - variable al, ar : acc_t; + fade_select : process(all) + variable d : signed(24 downto 0); + begin + fade_diff <= (others=>'0'); fade_gain <= (others=>'0'); + d := (others=>'0'); + if MUSICAL_VOICES and fade(mix_idx)<32 then + if mix_state=MIX_LEFT then + d:=resize(vout_l(mix_idx),25)-resize(carry_l(mix_idx),25); + elsif mix_state=MIX_RIGHT then + d:=resize(vout_r(mix_idx),25)-resize(carry_r(mix_idx),25); + end if; + fade_diff<=d; + fade_gain<=signed('0' & std_logic_vector(to_unsigned(fade(mix_idx),6))); + end if; + end process; + + mixer : process(clk) + variable interp : acc_t; begin if rising_edge(clk) then - if rst = '1' then - out_l <= (others => '0'); - out_r <= (others => '0'); - out_valid <= '0'; + out_valid<='0'; + if rst='1' then + out_l<=Q123_ZERO; out_r<=Q123_ZERO; + mix_state<=MIX_IDLE; mix_idx<=0; + mix_al<=(others=>'0'); mix_ar<=(others=>'0'); else - out_valid <= vout_v(0); - if vout_v(0) = '1' then - al := (others => '0'); - ar := (others => '0'); - for v in 0 to NVOICES-1 loop - al := al + to_acc(vout_l(v)); - ar := ar + to_acc(vout_r(v)); - end loop; - out_l <= sat_store(mul_coeff(RECIP, al)); - out_r <= sat_store(mul_coeff(RECIP, ar)); - end if; + case mix_state is + when MIX_IDLE => + if vout_v(0)='1' then + mix_al<=(others=>'0'); mix_ar<=(others=>'0'); mix_idx<=0; + mix_state<=MIX_LEFT; + end if; + when MIX_LEFT => + if MUSICAL_VOICES and fade(mix_idx)<32 then + interp:=to_acc(carry_l(mix_idx))+resize(shift_right(fade_product,5),ACC_BITS); + mix_al<=mix_al+interp; + else mix_al<=mix_al+to_acc(vout_l(mix_idx)); end if; + mix_state<=MIX_RIGHT; + when MIX_RIGHT => + if MUSICAL_VOICES and fade(mix_idx)<32 then + interp:=to_acc(carry_r(mix_idx))+resize(shift_right(fade_product,5),ACC_BITS); + mix_ar<=mix_ar+interp; + else mix_ar<=mix_ar+to_acc(vout_r(mix_idx)); end if; + if mix_idx=NVOICES-1 then mix_state<=MIX_OUT; + else mix_idx<=mix_idx+1; mix_state<=MIX_LEFT; end if; + when MIX_OUT => + out_l<=sat_store(mul_coeff(RECIP,mix_al)); + out_r<=sat_store(mul_coeff(RECIP,mix_ar)); + out_valid<='1'; mix_state<=MIX_IDLE; + end case; end if; end if; end process; diff --git a/src/rtl/preset_bank.vhd b/src/rtl/preset_bank.vhd index 346a6ce..d958386 100644 --- a/src/rtl/preset_bank.vhd +++ b/src/rtl/preset_bank.vhd @@ -12,11 +12,19 @@ -- 2 sigk1 = 1 - sigma*k backward damping (decay time) -- 3 alpha = chaos coupling timbre (amplitude stiffening) -- 4 gamma2_max = CFL-safe clamp ceiling (< 1/2) --- 5 pick_lx left pickup column --- 6 pick_ly left pickup row --- 7 pick_rx right pickup column --- 8 pick_ry right pickup row --- 9 boundary bit 0: 0 = fixed (Dirichlet), 1 = free (Neumann) +-- 5 low coord=pick_lx; bits15..8 RIM compliance; bits23..16 STIFFNESS +-- 6 low coord=pick_ly; bits15..8 STRIKE SIZE; bits23..16 HARDNESS +-- 7 low coord=pick_rx; bits15..8 STRIKE X +-- 8 low coord=pick_ry; bits15..8 STRIKE Y +-- 9 bit0 boundary; 3..1 MATERIAL; 6..4 CHARACTER/EXCITER; +-- 10..7 signed ANISO; 12..11 MIDI/CV source mode; +-- 16..15 L pick X frac; 18..17 L pick Y; 20..19 R X; 22..21 R Y +-- 10 FX master/enables + drive + tone +-- 11 chorus rate + depth + mix +-- 12 delay time (samples) + mix +-- 13 delay feedback + damping + ping-pong + POLISH macro (bits 6..0) +-- 14 reverb decay + damping + mix +-- 15 reverb size + diffusion + output trim -- -- Presets are addressed in one index space: -- 0 .. N_FACTORY-1 factory presets (ROM, read-only) @@ -27,10 +35,9 @@ -- * recall preset : recall with preset_index -> live regs load -- * save preset : save with preset_index -> live regs -> user slot -- --- The live registers drive the mesh continuously (sampled when it strobes). --- boundary is exposed as free_boundary for observability; the mesh's boundary is --- still a build-time generic today, so recall of the boundary bit is advisory --- (see docs/presets.md). +-- The live registers are exposed continuously. In the playable synth, TENSION, +-- DECAY, CHAOS, pickup taps and boundary mode are captured into each new voice; +-- standalone/legacy users can still consume the raw register outputs directly. -- -- Synthesisable VHDL-2008. ------------------------------------------------------------------------------- @@ -44,6 +51,9 @@ use work.fdtd_pkg.all; entity preset_bank is generic ( + MUSICAL_MODE : boolean := false; + NX : positive := 8; NY : positive := 8; OS : positive := 4; + FS_HZ : positive := 48_000; RESET_FREE : boolean := false; COORD_W : positive := 6; -- pickup-coordinate width N_USER : positive := 4 -- writable user preset slots ); @@ -67,13 +77,18 @@ entity preset_bank is pick_ly : out unsigned(COORD_W-1 downto 0); pick_rx : out unsigned(COORD_W-1 downto 0); pick_ry : out unsigned(COORD_W-1 downto 0); - free_boundary: out std_logic + free_boundary: out std_logic; + physical_ctrl: out std_logic_vector(23 downto 0); + rim_ctrl, strike_size, strike_x_ctrl, strike_y_ctrl : out unsigned(7 downto 0); + stiffness_ctrl, hardness_ctrl : out unsigned(7 downto 0); + fx_ctrl0, fx_ctrl1, fx_ctrl2 : out std_logic_vector(23 downto 0); + fx_ctrl3, fx_ctrl4, fx_ctrl5 : out std_logic_vector(23 downto 0) ); end entity preset_bank; architecture rtl of preset_bank is - constant NUM_REGS : natural := 10; + constant NUM_REGS : natural := 16; constant N_FACTORY : natural := 3; type bundle_t is array (0 to NUM_REGS-1) of std_logic_vector(23 downto 0); @@ -94,25 +109,79 @@ architecture rtl of preset_bank is b(7) := std_logic_vector(to_unsigned(rx, 24)); b(8) := std_logic_vector(to_unsigned(ry, 24)); b(9) := std_logic_vector(to_unsigned(free, 24)); + -- FX reset/preset defaults: the musical chain is active out of reset. + -- POLISH=64 gives a medium mastering curve without adding a panel control. + b(10) := x"FC6200"; -- master+FX enabled; DRIVE=24, TONE=128 (neutral) + b(11) := x"306040"; -- chorus rate=48, depth=96, mix=64 + b(12) := x"2EE040"; -- delay=12000 samples (250 ms), mix=64 + b(13) := x"6E50C0"; -- feedback=110, damping=80, ping-pong, POLISH=64 + b(14) := x"D26446"; -- reverb decay=210, damping=100, mix=70 + b(15) := x"B496FF"; -- size=180, diffusion=150, trim=unity return b; end function; -- Factory presets (see docs/presets.md for the physical rationale). Damping -- pairs are consistent: a0 = 1/(1+x), sigk1 = 1-x with x = sigma*k. -- gamma2 a0 sigk1 alpha g2max Lx Ly Rx Ry free - constant FACTORY : bank_t(0 to N_FACTORY-1) := ( + constant LEGACY_FACTORY : bank_t(0 to N_FACTORY-1) := ( 0 => mk(0.180, 0.995025, 0.995000, 0.10, 0.451, 2, 4, 6, 4, 0), -- drum 1 => mk(0.300, 0.999990, 0.999990, 0.40, 0.451, 1, 6, 6, 1, 1), -- gong 2 => mk(0.400, 0.999800, 0.999800, 0.30, 0.451, 3, 3, 5, 5, 1)); -- metallic plate + -- The musical top uses normalized tension and damping at its actual step rate. + function select_factory return bank_t is + variable b: bank_t(0 to N_FACTORY-1) := LEGACY_FACTORY; + variable x: real; + begin + if MUSICAL_MODE then + x := 18.0/real(FS_HZ*OS); + b(0) := mk(0.25,1.0/(1.0+x),1.0-x,0.0,0.451,NX/4,NY/2,3*NX/4,NY/2,0); + b(0)(9)(3 downto 1):="001"; -- membrane MATERIAL + b(0)(5)(15 downto 8):=x"00"; -- fixed rim + b(0)(7)(15 downto 8):=std_logic_vector(to_unsigned(32*(NX/3),8)); + b(0)(8)(15 downto 8):=std_logic_vector(to_unsigned(32*(NY/3),8)); + x := 2.0/real(FS_HZ*OS); + if NX >= NY then + b(1) := mk(0.25,1.0/(1.0+x),1.0-x,0.0,0.451,1,NY/3,1,2*NY/3,1); + else + b(1) := mk(0.25,1.0/(1.0+x),1.0-x,0.0,0.451,NX/3,1,2*NX/3,1,1); + end if; + b(1)(9)(3 downto 1):="011"; -- metal MATERIAL for gong + b(1)(5)(15 downto 8):=x"FF"; -- compliant/free rim + b(1)(7)(15 downto 8):=std_logic_vector(to_unsigned(32*(NX/3),8)); + b(1)(8)(15 downto 8):=std_logic_vector(to_unsigned(32*(NY/3),8)); + x := 5.0/real(FS_HZ*OS); + b(2) := mk(0.25,1.0/(1.0+x),1.0-x,0.02,0.451,NX/3,NY/3,2*NX/3,2*NY/3,0); + b(2)(9)(3 downto 1):="011"; -- metal MATERIAL for plate + b(2)(5)(15 downto 8):=x"00"; + b(2)(7)(15 downto 8):=std_logic_vector(to_unsigned(32*(NX/3),8)); + b(2)(8)(15 downto 8):=std_logic_vector(to_unsigned(32*(NY/3),8)); + end if; + return b; + end; + constant FACTORY: bank_t(0 to N_FACTORY-1) := select_factory; -- Reset default: the safe linear operating point (matches control_bus). - constant DEF_PRESET : bundle_t := mk(0.09, 0.99996875, 0.99996875, 0.0, 0.451, + constant LEGACY_DEFAULT : bundle_t := mk(0.09, 0.99996875, 0.99996875, 0.0, 0.451, 2, 4, 6, 4, 0); + function select_default return bundle_t is + variable b: bundle_t := LEGACY_DEFAULT; + begin + if MUSICAL_MODE then + b := mk(0.25,1.0/(1.0+5.0/real(FS_HZ*OS)),1.0-5.0/real(FS_HZ*OS), + 0.0,0.451,NX/4,NY/2,3*NX/4,NY/2,0); + b(7)(15 downto 8):=std_logic_vector(to_unsigned(32*(NX/3),8)); + b(8)(15 downto 8):=std_logic_vector(to_unsigned(32*(NY/3),8)); + if RESET_FREE then b(9)(0) := '1'; b(5)(15 downto 8):=x"FF"; end if; + end if; + return b; + end; + constant DEF_PRESET: bundle_t := select_default; signal regs : bundle_t := DEF_PRESET; -- live registers signal user : bank_t(0 to N_USER-1) := (others => DEF_PRESET); begin + assert COORD_W<=8 report "preset_bank: upper bytes of regs 5..8 are reserved for physical controls" severity failure; -- continuous distribution to the mesh coeffs.gamma2 <= signed(regs(0)); @@ -125,6 +194,15 @@ begin pick_rx <= unsigned(regs(7)(COORD_W-1 downto 0)); pick_ry <= unsigned(regs(8)(COORD_W-1 downto 0)); free_boundary <= regs(9)(0); + physical_ctrl <= regs(9); + rim_ctrl<=unsigned(regs(5)(15 downto 8)); + stiffness_ctrl<=unsigned(regs(5)(23 downto 16)); + strike_size<=unsigned(regs(6)(15 downto 8)); + hardness_ctrl<=unsigned(regs(6)(23 downto 16)); + strike_x_ctrl<=unsigned(regs(7)(15 downto 8)); + strike_y_ctrl<=unsigned(regs(8)(15 downto 8)); + fx_ctrl0 <= regs(10); fx_ctrl1 <= regs(11); fx_ctrl2 <= regs(12); + fx_ctrl3 <= regs(13); fx_ctrl4 <= regs(14); fx_ctrl5 <= regs(15); process (clk) variable idx : integer; diff --git a/src/rtl/synth_top.vhd b/src/rtl/synth_top.vhd index 00bca77..568cfa6 100644 --- a/src/rtl/synth_top.vhd +++ b/src/rtl/synth_top.vhd @@ -24,9 +24,10 @@ -- LRCLK->frame strobe (sample_strobe); a single global reset is used for both -- (sufficient for simulation, synchronise per-domain for a real build). -- --- Coefficient split: the note sets pitch (gamma2) and, via velocity, timbre --- (alpha); the recalled preset sets the "body" (a0/sigk1 decay + gamma2_max --- CFL clamp). So a preset picks the instrument and notes play it. +-- Musical merge: the calibrated note supplies base pitch and strike; normalized +-- preset TENSION retunes it, while DECAY / independent CHAOS / pickup positions / +-- boundary mode come from the live preset. A 20 Hz DC blocker conditions the +-- mixed pickup, then the preset-controlled stereo FX chain runs before I2S CDC. -- -- Output-only (a synth voice): the codec ADC input is unused (sd_rx tied off). -- @@ -39,9 +40,14 @@ use ieee.numeric_std.all; library work; use work.fdtd_pkg.all; +use work.musical_pkg.all; +use work.physical_pkg.all; +use ieee.math_real.all; entity synth_top is generic ( + FS_HZ : positive := 48_000; + OUTPUT_GAIN_SHIFT : natural := 5; -- voices / mesh NVOICES : positive := 4; NX : positive := 8; @@ -66,7 +72,8 @@ entity synth_top is mclk : in std_logic; -- serial MIDI in midi_rx : in std_logic; - -- control voltage in (system domain); cv_sel = '1' plays from CV, else MIDI + -- CV input; cv_sel='1' is a legacy/debug force-CV override. Normal board + -- operation leaves it low and AUTO arbitration follows note/gate activity. cv_sel : in std_logic := '0'; pitch_cv : in signed(CV_W-1 downto 0) := (others => '0'); gate : in std_logic := '0'; @@ -93,6 +100,29 @@ end entity synth_top; architecture rtl of synth_top is + signal p_lx, p_ly, p_rx, p_ry : unsigned(7 downto 0) := (others=>'0'); + signal p_free : std_logic := '0'; + signal p_phys : std_logic_vector(23 downto 0) := (others=>'0'); + signal p_material : material_t := (others=>'0'); + signal p_exciter : exciter_t := (others=>'0'); + signal p_aniso : aniso_t := (others=>'0'); + signal p_stiffness,p_hardness,p_rim,p_strike_size,p_strike_xc,p_strike_yc : unsigned(7 downto 0):=(others=>'0'); + signal p_strike_fx,p_strike_fy : frac2_t := (others=>'0'); + signal p_strike_x : natural range 0 to NX-1 := NX/3; + signal p_strike_y : natural range 0 to NY-1 := NY/3; + signal p_source_mode : unsigned(1 downto 0):=(others=>'0'); + signal auto_cv,source_cv : std_logic:='0'; + signal p_lfx,p_lfy,p_rfx,p_rfy : frac2_t := (others=>'0'); + signal free_selected : boolean; + signal dc_xl, dc_xr : q123_t := Q123_ZERO; + signal dc_yl, dc_yr : acc_t := (others=>'0'); + signal audio_l, audio_r : q123_t := Q123_ZERO; + signal audio_valid : std_logic := '0'; + signal fx_l, fx_r : q123_t := Q123_ZERO; + signal fx_valid : std_logic := '0'; + signal fx_ctrl0, fx_ctrl1, fx_ctrl2 : std_logic_vector(23 downto 0); + signal fx_ctrl3, fx_ctrl4, fx_ctrl5 : std_logic_vector(23 downto 0); + constant DC_R : q123_t := to_q123(exp(-2.0*MATH_PI*20.0/real(FS_HZ))); -- generated I2S clocks (audio domain) signal bclk_i, lrclk_i : std_logic; @@ -130,6 +160,7 @@ architecture rtl of synth_top is -- merged voice coefficients (note pitch/timbre + preset body) signal v_coeffs : coeffs_t; + signal tuned_gamma2, chaos_ctl : q123_t := Q123_ZERO; -- polyphonic mix (system domain) signal mix_l, mix_r : q123_t; @@ -140,7 +171,32 @@ architecture rtl of synth_top is signal pick_dst : std_logic_vector(47 downto 0); signal tx_l, tx_r : q123_t; + function strike_qcode(c:unsigned(7 downto 0); lim:positive) return natural is + variable q,m:natural; + begin + m:=(lim-1)*4; + if is_x(std_logic_vector(c)) then q:=4*(lim/3); + elsif lim=8 then q:=to_integer(c(7 downto 3)); + else q:=(to_integer(c)*m+127)/255; end if; + if q>m then q:=m; end if; return q; + end; + function strike_base(c:unsigned(7 downto 0); lim:positive) return natural is + begin return strike_qcode(c,lim)/4; end; + function strike_frac(c:unsigned(7 downto 0); lim:positive) return frac2_t is + begin return to_unsigned(strike_qcode(c,lim) mod 4,2); end; + begin + assert NX >= 4 and NY >= 4 report "Musical synth requires NX/NY >= 4" severity failure; + assert OUTPUT_GAIN_SHIFT <= 8 report "Excessive output gain" severity failure; + free_selected <= p_free = '1'; + p_material<=unsigned(p_phys(3 downto 1)); + p_exciter<=unsigned(p_phys(6 downto 4)); + p_aniso<=signed(p_phys(10 downto 7)); + p_source_mode<=unsigned(p_phys(12 downto 11)) when not is_x(p_phys(12 downto 11)) else "00"; + p_strike_x<=strike_base(p_strike_xc,NX); p_strike_y<=strike_base(p_strike_yc,NY); + p_strike_fx<=strike_frac(p_strike_xc,NX); p_strike_fy<=strike_frac(p_strike_yc,NY); + p_lfx<=unsigned(p_phys(16 downto 15)); p_lfy<=unsigned(p_phys(18 downto 17)); + p_rfx<=unsigned(p_phys(20 downto 19)); p_rfy<=unsigned(p_phys(22 downto 21)); ---------------------------------------------------------------------------- -- I2S master clock generation + codec clock pins @@ -177,8 +233,8 @@ begin -- MIDI front-end: note -> pitch / strike / timbre ---------------------------------------------------------------------------- midi : entity work.midi_frontend - generic map (CLK_HZ => CLK_HZ, BAUD => BAUD) - port map (clk => sys_clk, rst => sys_rst, rx => rx_sync, frame => frame, + generic map (CLK_HZ => CLK_HZ, BAUD => BAUD, NX=>NX, NY=>NY, OS=>OS, FS_HZ=>FS_HZ) + port map (free_mode=>free_selected, clk => sys_clk, rst => sys_rst, rx => rx_sync, frame => frame, coeffs => m_coeffs, exc_in => m_exc_in, exc_en => m_exc_en, note_on => m_note_on, note_off => m_note_off, note => m_note, velocity => m_vel); @@ -187,47 +243,83 @@ begin -- CV front-end: pitch/gate/mod -> note mapping (same interface as MIDI) ---------------------------------------------------------------------------- cv : entity work.cv_frontend - generic map (CV_W => CV_W) - port map (clk => sys_clk, rst => sys_rst, frame => frame, + generic map (CV_W => CV_W, NX=>NX, NY=>NY, OS=>OS, FS_HZ=>FS_HZ) + port map (free_mode=>free_selected, clk => sys_clk, rst => sys_rst, frame => frame, pitch_cv => pitch_cv, gate => gate, mod_cv => mod_cv, coeffs => c_coeffs, exc_in => c_exc_in, exc_en => open, note_on => c_note_on, note_off => c_note_off, note => c_note, velocity => open); - -- select the active source (MIDI or CV) - s_coeffs <= c_coeffs when cv_sel = '1' else m_coeffs; - s_exc_in <= c_exc_in when cv_sel = '1' else m_exc_in; - s_note_on <= c_note_on when cv_sel = '1' else m_note_on; - s_note_off <= c_note_off when cv_sel = '1' else m_note_off; - s_note <= c_note when cv_sel = '1' else m_note; + -- AUTO source arbitration: the newest note-on/gate edge claims the source. + -- Register-9 source mode: 00/11=AUTO, 01=force MIDI, 10=force CV. + source_claim : process(sys_clk) + begin + if rising_edge(sys_clk) then + if sys_rst='1' then auto_cv<='0'; + elsif m_note_on='1' then auto_cv<='0'; + elsif c_note_on='1' then auto_cv<='1'; end if; + end if; + end process; + source_cv <= '1' when cv_sel='1' or p_source_mode="10" else + '0' when p_source_mode="01" else + '1' when c_note_on='1' and m_note_on='0' else + '0' when m_note_on='1' else auto_cv; + s_coeffs <= c_coeffs when source_cv='1' else m_coeffs; + s_exc_in <= c_exc_in when source_cv='1' else m_exc_in; + s_note_on <= c_note_on when source_cv='1' else m_note_on; + -- Releases from the inactive source still free their allocated voice. + s_note_off <= c_note_off or m_note_off; + s_note <= c_note when c_note_on='1' or (c_note_off='1' and m_note_on='0' and m_note_off='0') else + m_note when m_note_on='1' or m_note_off='1' else + c_note when source_cv='1' else m_note; ---------------------------------------------------------------------------- -- Preset bank: base "body" coefficients + register edit/read-back ---------------------------------------------------------------------------- presets : entity work.preset_bank + generic map (MUSICAL_MODE=>true,NX=>NX,NY=>NY,OS=>OS,FS_HZ=>FS_HZ,COORD_W=>8,RESET_FREE=>FREE_BOUNDARY) port map (clk => sys_clk, rst => sys_rst, wr_en => cfg_wr_en, wr_addr => cfg_wr_addr, wr_data => cfg_wr_data, rd_addr => cfg_rd_addr, rd_data => cfg_rd_data, preset_index => preset_index, recall => preset_recall, save => preset_save, coeffs => p_coeffs, - pick_lx => open, pick_ly => open, pick_rx => open, pick_ry => open, - free_boundary => open); + pick_lx => p_lx, pick_ly => p_ly, pick_rx => p_rx, pick_ry => p_ry, + free_boundary => p_free, physical_ctrl=>p_phys, + rim_ctrl=>p_rim,strike_size=>p_strike_size, + strike_x_ctrl=>p_strike_xc,strike_y_ctrl=>p_strike_yc, + stiffness_ctrl=>p_stiffness,hardness_ctrl=>p_hardness, + fx_ctrl0 => fx_ctrl0, fx_ctrl1 => fx_ctrl1, fx_ctrl2 => fx_ctrl2, + fx_ctrl3 => fx_ctrl3, fx_ctrl4 => fx_ctrl4, fx_ctrl5 => fx_ctrl5); -- merge: the selected source sets pitch (gamma2) + timbre (alpha); the preset -- sets the body (decay a0/sigk1, CFL clamp gamma2_max) - v_coeffs.gamma2 <= s_coeffs.gamma2; - v_coeffs.alpha <= s_coeffs.alpha; - v_coeffs.a0 <= p_coeffs.a0; - v_coeffs.sigk1 <= p_coeffs.sigk1; - v_coeffs.gamma2_max <= p_coeffs.gamma2_max; + tuned_gamma2 <= clamp(tension_scale(s_coeffs.gamma2,p_coeffs.gamma2), + to_q123(2.0**(-23)),to_q123(0.45)) when sys_rst='0' else Q123_ZERO; + chaos_ctl <= clamp(sat_add(p_coeffs.alpha,s_coeffs.alpha),Q123_ZERO,to_q123(0.4)) + when sys_rst='0' else Q123_ZERO; + v_coeffs.gamma2 <= tuned_gamma2; + -- CHAOS is independent of MIDI velocity; scale its physical effect with pitch. + v_coeffs.alpha <= material_alpha( + sat_store(shift_left(mul_coeff(chaos_ctl,to_acc(tuned_gamma2)),4)),p_material); + v_coeffs.a0 <= p_coeffs.a0 when sys_rst='0' else Q123_ZERO; + v_coeffs.sigk1 <= p_coeffs.sigk1 when sys_rst='0' else Q123_ZERO; + v_coeffs.gamma2_max <= p_coeffs.gamma2_max when sys_rst='0' else Q123_ZERO; ---------------------------------------------------------------------------- -- Polyphonic voice pool (system domain) ---------------------------------------------------------------------------- voices : entity work.poly_voices generic map (NVOICES => NVOICES, NX => NX, NY => NY, OS => OS, - FREE_BOUNDARY => FREE_BOUNDARY, TIME_MUX => TIME_MUX) - port map (clk => sys_clk, rst => sys_rst, frame => frame, + FREE_BOUNDARY => FREE_BOUNDARY, TIME_MUX => TIME_MUX, MUSICAL_VOICES=>true) + port map (free_mode=>free_selected, tap_lx=>coordinate(p_lx,NX),tap_ly=>coordinate(p_ly,NY), + tap_rx=>coordinate(p_rx,NX),tap_ry=>coordinate(p_ry,NY), + tap_lfx=>p_lfx,tap_lfy=>p_lfy,tap_rfx=>p_rfx,tap_rfy=>p_rfy, + material=>p_material,exciter_mode=>p_exciter,anisotropy=>p_aniso, + stiffness_ctrl=>p_stiffness,hardness_ctrl=>p_hardness, + rim_ctrl=>p_rim,strike_size=>p_strike_size, + strike_x=>p_strike_x,strike_y=>p_strike_y, + strike_fx=>p_strike_fx,strike_fy=>p_strike_fy, + clk => sys_clk, rst => sys_rst, frame => frame, note_on => s_note_on, note_off => s_note_off, note => s_note, coeffs_in => v_coeffs, exc_in => s_exc_in, out_l => mix_l, out_r => mix_r, out_valid => mix_valid, @@ -236,12 +328,40 @@ begin ---------------------------------------------------------------------------- -- Pickup CDC: stereo mix crosses into the I2S (audio) domain ---------------------------------------------------------------------------- - pick_src <= std_logic_vector(mix_l) & std_logic_vector(mix_r); + -- Remove DC in the RTL, then restore listening level without overdriving cells. + condition_audio : process(sys_clk) + variable yl, yr: acc_t; + begin + if rising_edge(sys_clk) then + audio_valid <= '0'; + if sys_rst='1' then + dc_xl<=Q123_ZERO; dc_xr<=Q123_ZERO; + dc_yl<=(others=>'0'); dc_yr<=(others=>'0'); + audio_l<=Q123_ZERO; audio_r<=Q123_ZERO; + elsif mix_valid='1' then + yl:=to_acc(mix_l)-to_acc(dc_xl)+mul_coeff(DC_R,dc_yl); + yr:=to_acc(mix_r)-to_acc(dc_xr)+mul_coeff(DC_R,dc_yr); + dc_xl<=mix_l; dc_xr<=mix_r; dc_yl<=yl; dc_yr<=yr; + audio_l<=sat_store(shift_left(yl,OUTPUT_GAIN_SHIFT)); + audio_r<=sat_store(shift_left(yr,OUTPUT_GAIN_SHIFT)); + audio_valid<='1'; + end if; + end if; + end process; + fx : entity work.fx_chain + generic map (FS_HZ=>FS_HZ) + port map (clk=>sys_clk, rst=>sys_rst, valid_in=>audio_valid, + in_l=>audio_l, in_r=>audio_r, + ctrl0=>fx_ctrl0, ctrl1=>fx_ctrl1, ctrl2=>fx_ctrl2, + ctrl3=>fx_ctrl3, ctrl4=>fx_ctrl4, ctrl5=>fx_ctrl5, + out_l=>fx_l, out_r=>fx_r, valid_out=>fx_valid); + + pick_src <= std_logic_vector(fx_l) & std_logic_vector(fx_r); cdc_pick : entity work.cdc_word generic map (WIDTH => 48) port map (src_clk => sys_clk, src_rst => sys_rst, - src_data => pick_src, src_valid => mix_valid, + src_data => pick_src, src_valid => fx_valid, dst_clk => bclk_i, dst_rst => sys_rst, dst_data => pick_dst, dst_valid => open); diff --git a/src/rtl/top_resonator.vhd b/src/rtl/top_resonator.vhd index fbb3dd6..b88de01 100644 --- a/src/rtl/top_resonator.vhd +++ b/src/rtl/top_resonator.vhd @@ -72,6 +72,7 @@ architecture rtl of top_resonator is -- coefficients (system domain) signal coeffs : coeffs_t; + signal stiffness_ctrl,hardness_ctrl : unsigned(7 downto 0) := (others=>'0'); -- excitation CDC (I2S -> system) signal exc_slv : std_logic_vector(23 downto 0); @@ -107,7 +108,11 @@ begin preset_index => preset_index, recall => preset_recall, save => preset_save, coeffs => coeffs, pick_lx => open, pick_ly => open, pick_rx => open, pick_ry => open, - free_boundary => open); + free_boundary => open, physical_ctrl => open, + rim_ctrl=>open,strike_size=>open,strike_x_ctrl=>open,strike_y_ctrl=>open, + stiffness_ctrl=>stiffness_ctrl,hardness_ctrl=>hardness_ctrl, + fx_ctrl0 => open, fx_ctrl1 => open, fx_ctrl2 => open, + fx_ctrl3 => open, fx_ctrl4 => open, fx_ctrl5 => open); ---------------------------------------------------------------------------- -- Excitation CDC: the mallet (rx_l) crosses into the mesh domain. Its @@ -127,7 +132,8 @@ begin generic map (NX => NX, NY => NY, OS => OS, FREE_BOUNDARY => FREE_BOUNDARY, TIME_MUX => TIME_MUX) port map (clk => sys_clk, rst => sys_rst, - frame => exc_valid, coeffs => coeffs, + frame => exc_valid, coeffs => coeffs, stiffness_ctrl=>stiffness_ctrl, + hardness_ctrl=>hardness_ctrl, exc_in => signed(exc_slv), exc_en => '1', out_l => out_l, out_r => out_r, out_valid => out_valid); diff --git a/src/tb/adc_mcp3208_tb.vhd b/src/tb/adc_mcp3208_tb.vhd new file mode 100644 index 0000000..1ed289a --- /dev/null +++ b/src/tb/adc_mcp3208_tb.vhd @@ -0,0 +1,168 @@ +------------------------------------------------------------------------------- +-- adc_mcp3208_tb.vhd - checks the panel/CV ADC master against a device model +-- +-- The model below behaves like the real MCP3208 rather than like the master's +-- own assumptions: it waits for the start bit instead of counting from CS, +-- latches DIN on the rising edge, drives DOUT on the falling edge, and emits a +-- null bit before the twelve data bits. A master that only works against a +-- model written from the same misreading of the datasheet would pass a test +-- that proves nothing. +-- +-- Checks, in order: +-- * every channel is addressed, in order, and the sweep repeats; +-- * the code presented on a channel is the code that appears on its output; +-- * pot outputs are 12-bit unsigned and CV outputs are the same code +-- zero-extended into a signed word, as panel_ctrl and cv_frontend expect; +-- * scan_done is a single cycle and marks a complete sweep of all eight. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.env.finish; + +entity adc_mcp3208_tb is +end entity adc_mcp3208_tb; + +architecture sim of adc_mcp3208_tb is + + constant CLK_HZ : positive := 100_000_000; + constant SCLK_HZ : positive := 1_000_000; + constant CLK_T : time := 10 ns; + + signal clk : std_logic := '0'; + signal rst : std_logic := '1'; + + signal sclk, cs_n, mosi, miso : std_logic; + + signal pot_pitch, pot_decay, pot_timbre : unsigned(11 downto 0); + signal pot_drive, pot_delay, pot_reverb : unsigned(11 downto 0); + signal pitch_cv, mod_cv : signed(15 downto 0); + signal scan_done : std_logic; + + -- Codes the model returns, one per channel. + type codes_t is array (0 to 7) of unsigned(11 downto 0); + constant CODES : codes_t := (x"000", x"FFF", x"ABC", x"555", x"123", x"246", x"789", x"DEF"); + + signal seen_ch : integer := -1; -- channel the model last decoded + signal n_frames : natural := 0; + signal n_scans : natural := 0; + signal done : boolean := false; + +begin + + clk <= '0' when done else not clk after CLK_T/2; + + dut : entity work.adc_mcp3208 + generic map (CLK_HZ => CLK_HZ, SCLK_HZ => SCLK_HZ) + port map ( + clk => clk, rst => rst, + adc_sclk => sclk, adc_cs_n => cs_n, adc_mosi => mosi, adc_miso => miso, + pot_pitch => pot_pitch, pot_decay => pot_decay, pot_timbre => pot_timbre, + pot_drive => pot_drive, pot_delay => pot_delay, pot_reverb => pot_reverb, + pitch_cv => pitch_cv, mod_cv => mod_cv, scan_done => scan_done); + + -- ---------------------------------------------------------------- model --- + model : process + variable ch : unsigned(2 downto 0); + variable code : unsigned(11 downto 0); + variable framed : boolean; + begin + miso <= 'Z'; + wait until falling_edge(cs_n); + + -- Wait for the start bit, exactly as the part does. A frame that is + -- abandoned (CS raised early) just returns to waiting rather than + -- desynchronising the model from the master. + framed := false; + loop + wait until rising_edge(sclk) or rising_edge(cs_n); + exit when cs_n = '1'; + if mosi = '1' then + framed := true; + exit; + end if; + end loop; + + if framed then + -- SGL/DIFF then three channel bits, latched on rising edges. + wait until rising_edge(sclk); + assert mosi = '1' + report "model: SGL/DIFF low -- master requested differential mode" + severity failure; + for i in 2 downto 0 loop + wait until rising_edge(sclk); + ch(i) := mosi; + end loop; + + assert to_integer(ch) < 8 + report "model: master addressed unused channel " & + integer'image(to_integer(ch)) + severity failure; + seen_ch <= to_integer(ch); + code := CODES(to_integer(ch)); + + -- Null bit, then twelve data bits, each driven on the falling edge. + wait until falling_edge(sclk); + miso <= '0'; + for i in 11 downto 0 loop + wait until falling_edge(sclk); + miso <= code(i); + end loop; + wait until rising_edge(cs_n); + miso <= 'Z'; + n_frames <= n_frames + 1; + end if; + end process; + + -- --------------------------------------------------------------- checks --- + count_scans : process (clk) is + variable prev : std_logic := '0'; + begin + if rising_edge(clk) then + if scan_done = '1' then + assert prev = '0' + report "scan_done asserted for more than one cycle" severity failure; + n_scans <= n_scans + 1; + end if; + prev := scan_done; + end if; + end process; + + stim : process + begin + rst <= '1'; + wait for 200 ns; + rst <= '0'; + + -- Two complete sweeps, so the channel counter is seen to wrap. + wait until n_scans = 2; + wait for 5 us; + + assert pot_pitch = CODES(0) + report "CH0 -> pot_pitch wrong" severity failure; + assert pot_decay = CODES(1) + report "CH1 -> pot_decay wrong" severity failure; + assert pot_timbre = CODES(2) + report "CH2 -> pot_timbre wrong" severity failure; + assert pitch_cv = signed(resize(CODES(3), 16)) + report "CH3 -> pitch_cv wrong" severity failure; + assert mod_cv = signed(resize(CODES(4), 16)) + report "CH4 -> mod_cv wrong" severity failure; + assert pot_drive = CODES(5) report "CH5 -> pot_drive wrong" severity failure; + assert pot_delay = CODES(6) report "CH6 -> pot_delay wrong" severity failure; + assert pot_reverb = CODES(7) report "CH7 -> pot_reverb wrong" severity failure; + + assert n_frames >= 16 + report "expected at least 16 conversions in two sweeps, got " & + integer'image(n_frames) + severity failure; + + report "adc_mcp3208_tb: all checks passed (" & integer'image(n_frames) & + " conversions, " & integer'image(n_scans) & " complete sweeps)" + severity note; + done <= true; + finish; + end process; + +end architecture sim; diff --git a/src/tb/cv_frontend_tb.vhd b/src/tb/cv_frontend_tb.vhd index a5de1ec..7fa6db4 100644 --- a/src/tb/cv_frontend_tb.vhd +++ b/src/tb/cv_frontend_tb.vhd @@ -145,7 +145,7 @@ begin wait_note_on(p); assert to_integer(unsigned(cv_note)) = 69 report "cv_frontend_tb: 0 V did not map to the reference note" severity failure; - assert coeffs.gamma2 = to_q123(0.09) + assert coeffs.gamma2 = to_signed(7210,24) report "cv_frontend_tb: reference-note gamma2 wrong" severity failure; a_lo := to_integer(coeffs.alpha); -- alpha at mod = 0 wait_exc_en; @@ -168,7 +168,7 @@ begin wait_note_on(p); assert to_integer(unsigned(cv_note)) = 81 report "cv_frontend_tb: +1 octave CV did not map +12 semitones" severity failure; - assert coeffs.gamma2 = to_q123(0.36) + assert coeffs.gamma2 = to_signed(28837,24) report "cv_frontend_tb: octave-up gamma2 not x4" severity failure; gate <= '0'; wait_note_off(noff_count); diff --git a/src/tb/fx_chain_tb.vhd b/src/tb/fx_chain_tb.vhd new file mode 100644 index 0000000..269c026 --- /dev/null +++ b/src/tb/fx_chain_tb.vhd @@ -0,0 +1,172 @@ +------------------------------------------------------------------------------- +-- fx_chain_tb.vhd - smoke/integration tests for the onboard stereo FX chain. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.env.all; +library work; +use work.fdtd_pkg.all; + +entity fx_chain_tb is end entity; + +architecture sim of fx_chain_tb is + constant T : time := 10 ns; + signal clk : std_logic := '0'; + signal rst : std_logic := '1'; + signal vin : std_logic := '0'; + signal il,ir,ol,orx : q123_t := Q123_ZERO; + signal vout : std_logic; + signal c0,c1,c2,c3,c4,c5 : std_logic_vector(23 downto 0) := (others=>'0'); + signal done : boolean := false; +begin + clock : process begin + while not done loop clk<='0'; wait for T/2; clk<='1'; wait for T/2; end loop; wait; + end process; + + dut : entity work.fx_chain + port map(clk=>clk,rst=>rst,valid_in=>vin,in_l=>il,in_r=>ir, + ctrl0=>c0,ctrl1=>c1,ctrl2=>c2,ctrl3=>c3,ctrl4=>c4,ctrl5=>c5, + out_l=>ol,out_r=>orx,valid_out=>vout); + + watchdog : process begin + wait for 20 ms; assert done report "fx_chain_tb timeout" severity failure; wait; + end process; + + stim : process + procedure step is begin wait until rising_edge(clk); end procedure; + procedure push(lv,rv : integer; variable lo,ro : out integer) is + variable guard : integer := 0; + begin + il<=to_signed(lv,24); ir<=to_signed(rv,24); vin<='1'; step; vin<='0'; + loop + step; guard:=guard+1; + exit when vout='1'; + assert guard<100 report "fx_chain_tb: pipeline failed to return valid" severity failure; + end loop; + lo:=to_integer(ol); ro:=to_integer(orx); + end procedure; + procedure settle_master is + variable a,b : integer; + begin + for i in 1 to 132 loop push(0,0,a,b); end loop; + end procedure; + variable l,r,first_l,fade_l : integer; + variable polish_changed : boolean := false; + variable chorus_seen, echo_seen, sync_seen, triplet_seen, tail_seen : boolean := false; + begin + rst<='1'; step; step; rst<='0'; step; + + -- Master bypass must be bit-exact even though samples traverse the pipeline. + push(1000000,-500000,l,r); + assert l=1000000 and r=-500000 + report "fx_chain_tb: master bypass is not bit exact" severity failure; + + -- Master may be on while POLISH remains zero; the new bus block itself + -- must then be bit-exact when all other effects are disabled. + c0<=x"800000"; c3<=(others=>'0'); c5<=x"0000FF"; + push(900000,-450000,l,r); + assert l=900000 and r=-450000 + report "fx_chain_tb: POLISH=0 is not bit exact" severity failure; + + -- Drive only: verify that a moderate positive sample is audibly reshaped. + c0<=x"C20000"; -- master + drive, amount 128 + c5<=x"0000FF"; -- unity output trim + -- Parameter edits slew at 2 LSB/sample: the first changed sample must be + -- gentler than the settled drive value rather than a one-sample jump. + push(2500000,2500000,l,r); first_l:=l; + for i in 0 to 70 loop push(2500000,2500000,l,r); end loop; + assert l>first_l and l>2500000 and r>2500000 + report "fx_chain_tb: smoothed drive did not settle progressively" severity failure; + + -- Global master-off crossfades, then reaches an exact dry bypass. + c0<=x"400000"; -- drive bit left set, master cleared + push(2500000,2500000,l,r); fade_l:=l; + assert fade_l/=2500000 report "fx_chain_tb: master bypass hard-jumped instead of fading" severity failure; + for i in 0 to 140 loop push(2500000,2500000,l,r); end loop; + assert l=2500000 and r=2500000 + report "fx_chain_tb: master fade did not converge to bit-exact dry" severity failure; + + -- Tone only: a bright setting must alter a fresh broadband-ish sample. + rst<='1'; step; step; rst<='0'; step; + c0<=x"A003FC"; c1<=(others=>'0'); c5<=x"0000FF"; + settle_master; + push(1000000,1000000,l,r); + assert l/=1000000 and r/=1000000 + report "fx_chain_tb: tone control did not alter signal" severity failure; + + -- Chorus only: fixed 240-sample pure-wet short delay must return the impulse. + rst<='1'; step; step; rst<='0'; step; + c0<=x"900000"; c1<=x"0000FF"; c2<=(others=>'0'); c3<=(others=>'0'); + c4<=(others=>'0'); c5<=x"0000FF"; + settle_master; + push(1600000,0,l,r); + for i in 1 to 245 loop + push(0,0,l,r); + if abs(l)>100000 or abs(r)>100000 then chorus_seen:=true; end if; + end loop; + assert chorus_seen report "fx_chain_tb: chorus delay produced no wet return" severity failure; + + -- Reset state, then exercise a four-sample pure-wet delay. + rst<='1'; step; step; rst<='0'; step; + c0<=x"880000"; c2<=x"0004FF"; c3<=x"000000"; c5<=x"0000FF"; + settle_master; + push(1600000,0,l,r); + for i in 1 to 4 loop + push(0,0,l,r); + if abs(l)>100000 or abs(r)>100000 then echo_seen:=true; end if; + end loop; + assert echo_seen report "fx_chain_tb: short delay produced no echo" severity failure; + + -- Tempo-grid mode: 180 BPM, 1/16 = 4000 samples at 48 kHz. The high bit + -- selects sync mode; raw-sample presets keep bit 23 clear and are unchanged. + rst<='1'; step; step; rst<='0'; step; + c0<=x"880000"; c2<=x"F800FF"; c3<=x"000000"; c5<=x"0000FF"; + settle_master; + push(1600000,0,l,r); + for i in 1 to 4004 loop + push(0,0,l,r); + if i>=3996 and abs(l)>100000 then sync_seen:=true; end if; + end loop; + assert sync_seen report "fx_chain_tb: tempo-synced 1/16 delay did not land near 4000 samples" severity failure; + + -- Same 180 BPM clock, 1/8-triplet code 6 -> floor(16000/3)=5333 samples. + rst<='1'; step; step; rst<='0'; step; + c0<=x"880000"; c2<=x"F8C0FF"; c3<=x"000000"; c5<=x"0000FF"; + settle_master; + push(1600000,0,l,r); + for i in 1 to 5337 loop + push(0,0,l,r); + if i>=5329 and abs(l)>100000 then triplet_seen:=true; end if; + end loop; + assert triplet_seen report "fx_chain_tb: tempo-synced triplet delay did not land near 5333 samples" severity failure; + + -- Reverb: smallest room must produce a delayed FDN tail after an impulse. + rst<='1'; step; step; rst<='0'; step; + c0<=x"840000"; c2<=(others=>'0'); c3<=(others=>'0'); + c4<=x"C040FF"; c5<=x"0080FF"; + settle_master; + push(1600000,1600000,l,r); + for i in 1 to 260 loop + push(0,0,l,r); + if abs(l)>1000 or abs(r)>1000 then tail_seen:=true; end if; + end loop; + assert tail_seen report "fx_chain_tb: FDN produced no reverberant tail" severity failure; + + -- POLISH uses the formerly-unused low seven bits of ctrl3. With the + -- ordinary effects bypassed it must still reshape/make up a small AC tone. + rst<='1'; step; step; rst<='0'; step; + c0<=x"800000"; c1<=(others=>'0'); c2<=(others=>'0'); + c3<=x"000040"; c4<=(others=>'0'); c5<=x"0000FF"; + settle_master; + for i in 0 to 95 loop + if (i mod 2)=0 then push(120000,-120000,l,r); + else push(-120000,120000,l,r); end if; + if abs(l)>130000 or abs(r)>130000 then polish_changed:=true; end if; + end loop; + assert polish_changed report "fx_chain_tb: POLISH bus stage did not reshape/make up signal" severity failure; + + report "fx_chain_tb: bypass, drive, tone, chorus, delay, FDN and POLISH checks passed" severity note; + done<=true; finish; + end process; +end architecture; diff --git a/src/tb/mallet_tb.vhd b/src/tb/mallet_tb.vhd new file mode 100644 index 0000000..9c6d7ed --- /dev/null +++ b/src/tb/mallet_tb.vhd @@ -0,0 +1,158 @@ +------------------------------------------------------------------------------- +-- mallet_tb.vhd - stateful physical mallet / HARDNESS acceptance (#87) +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.env.all; +use std.textio.all; +library work; +use work.fdtd_pkg.all; + +entity mallet_tb is end; +architecture sim of mallet_tb is + constant T:time:=10 ns; + signal clk:std_logic:='0'; signal rst:std_logic:='1'; + signal step,trig,en:std_logic:='0'; + signal vel,surf,force_sig,hx,hv:q123_t:=Q123_ZERO; + signal hard:unsigned(7 downto 0):=(others=>'0'); + signal contact,active:std_logic; + signal m_rst,m_strobe,m_exen:std_logic:='1'; + signal m_exc:q123_t:=Q123_ZERO; + signal coeffs:coeffs_t; + signal sp_l,sp_r,tm_l,tm_r:q123_t; signal sp_v,tm_v:std_logic; + signal done:boolean:=false; +begin + clock:process begin + while not done loop clk<='0';wait for T/2;clk<='1';wait for T/2;end loop;wait; + end process; + dut:entity work.physical_mallet + port map(clk=>clk,rst=>rst,enable=>en,step=>step,trigger=>trig, + strike_velocity=>vel,hardness=>hard,surface_u=>surf, + force_out=>force_sig,contact=>contact,active=>active, + hammer_x=>hx,hammer_v=>hv); + + spatial:entity work.grid_mesh + generic map(NX=>8,NY=>8,FREE_BOUNDARY=>false) + port map(clk=>clk,rst=>m_rst,strobe=>m_strobe,coeffs=>coeffs, + mallet_enable=>'1',hardness_ctrl=>x"80",strike_x=>4,strike_y=>4, + exc_in=>m_exc,exc_en=>m_exen,pick_l=>sp_l,pick_r=>sp_r,valid=>sp_v); + folded:entity work.grid_mesh_tdm + generic map(NX=>8,NY=>8,FREE_BOUNDARY=>false) + port map(clk=>clk,rst=>m_rst,strobe=>m_strobe,coeffs=>coeffs, + mallet_enable=>'1',hardness_ctrl=>x"80",strike_x=>4,strike_y=>4, + exc_in=>m_exc,exc_en=>m_exen,pick_l=>tm_l,pick_r=>tm_r,valid=>tm_v); + + stim:process + procedure tick is begin wait until rising_edge(clk);end; + procedure reset_mallet is begin + rst<='1';en<='1';step<='0';trig<='0';surf<=Q123_ZERO; + tick;tick;rst<='0';tick; + end; + procedure run_contact(h:unsigned(7 downto 0); amplitude:real; + variable csteps:out natural; variable energy:out integer) is + variable started:boolean:=false; variable quiet:natural:=0; + begin + reset_mallet; hard<=h;vel<=to_q123(amplitude); + step<='1';trig<='1';tick;trig<='0'; + csteps:=0;energy:=0; + for k in 0 to 1200 loop + tick; + if contact='1' then + csteps:=csteps+1;started:=true;energy:=energy+abs(to_integer(force_sig)); + elsif started then + quiet:=quiet+1; exit when active='0' and quiet>1; + end if; + end loop; + step<='0'; + assert started and energy>0 report "mallet_tb: contact never started" severity failure; + assert active='0' and force_sig=Q123_ZERO report "mallet_tb: mallet did not release cleanly" severity failure; + end; + + procedure mesh_reset is begin + m_rst<='1';m_strobe<='0';m_exen<='0';m_exc<=Q123_ZERO; + tick;tick;m_rst<='0';tick; + end; + procedure mesh_step(first:boolean) is begin + m_exc<=to_q123(0.55); + if first then m_exen<='1';else m_exen<='0';end if; + m_strobe<='1';tick;m_strobe<='0';m_exen<='0'; + wait until rising_edge(clk) and tm_v='1'; + end; + variable cs,cm,ch,cvslow,cvfast:natural; + variable es,em,eh,evs,evf:integer; + variable f0,f1:q123_t; + variable mesh_energy:integer:=0; + file ft:text; variable fs:file_open_status; variable ln:line; + variable gf,gc,ga,gx,gv:integer; variable trace_n:natural:=0; + begin + coeffs<=(gamma2=>to_q123(0.09),a0=>to_q123(0.9995), + sigk1=>to_q123(0.9995),alpha=>Q123_ZERO, + gamma2_max=>to_q123(0.451)); + + run_contact(x"20",0.50,cs,es); + run_contact(x"80",0.50,cm,em); + run_contact(x"FF",0.50,ch,eh); + assert cs>cm and cm>ch + report "mallet_tb: HARDNESS did not shorten contact monotonically: "& + integer'image(cs)&"/"&integer'image(cm)&"/"&integer'image(ch) severity failure; + + run_contact(x"80",0.20,cvslow,evs); + run_contact(x"80",0.85,cvfast,evf); + assert cvslow>cvfast + report "mallet_tb: higher strike velocity did not shorten contact" severity failure; + + -- Independent Python fixed-point golden: medium HARDNESS, velocity 0.5. + reset_mallet;hard<=x"80";vel<=to_q123(0.5); + step<='1';trig<='1';tick;trig<='0'; + file_open(fs,ft,"../src/tb/mallet_trace.txt",read_mode); + assert fs=open_ok report "mallet_tb: cannot open mallet_trace.txt" severity failure; + readline(ft,ln); -- header + trace_n:=0; + while not endfile(ft) loop + readline(ft,ln);read(ln,gf);read(ln,gc);read(ln,ga);read(ln,gx);read(ln,gv); + tick;wait for 1 ps;trace_n:=trace_n+1; + assert to_integer(force_sig)=gf and to_integer(hx)=gx and to_integer(hv)=gv + report "mallet_tb: golden force/state mismatch at sample "&integer'image(trace_n)& + " got F/X/V="&integer'image(to_integer(force_sig))&"/"&integer'image(to_integer(hx))&"/"&integer'image(to_integer(hv))& + " expected "&integer'image(gf)&"/"&integer'image(gx)&"/"&integer'image(gv) severity failure; + assert (contact='1')=(gc=1) and (active='1')=(ga=1) + report "mallet_tb: golden contact/active mismatch at sample "&integer'image(trace_n) severity failure; + end loop; + file_close(ft);step<='0'; + assert trace_n>100 report "mallet_tb: golden trace unexpectedly short" severity failure; + + -- Bidirectional dependency: changing the surface position changes contact + -- force even though hammer state/HARDNESS are otherwise untouched. + reset_mallet;hard<=x"80";vel<=to_q123(0.5);step<='1';trig<='1';tick;trig<='0'; + for k in 0 to 80 loop tick;exit when contact='1';end loop; + assert contact='1' severity failure; + f0:=force_sig; surf<=to_q123(0.01); wait for 1 ns; f1:=force_sig; + assert f1/=f0 report "mallet_tb: surface displacement did not feed back into contact force" severity failure; + step<='0';en<='0';tick; + + -- If contact is made impossible, MAX_AGE must still terminate the state + -- machine with zero output rather than leaving a stuck active/DC exciter. + reset_mallet;hard<=x"80";vel<=to_q123(0.10);step<='1';trig<='1';tick;trig<='0'; + surf<=to_q123(0.90); + for k in 0 to 2060 loop tick; end loop; + assert active='0' and force_sig=Q123_ZERO + report "mallet_tb: no-contact timeout failed" severity failure; + step<='0';en<='0';tick;surf<=Q123_ZERO; + + -- Full mesh integration: same stateful mallet must drive both backends + -- identically and continue injecting after the one-cycle trigger is gone. + mesh_reset; + for k in 0 to 159 loop + mesh_step(k=0); + assert sp_l=tm_l and sp_r=tm_r + report "mallet_tb: spatial/TDM physical-mallet mismatch at step "&integer'image(k) severity failure; + mesh_energy:=mesh_energy+abs(to_integer(tm_l))+abs(to_integer(tm_r)); + end loop; + assert mesh_energy>0 report "mallet_tb: integrated physical mallet was silent" severity failure; + + report "mallet_tb: HARDNESS/velocity contact ordering, release, feedback and backend parity passed" severity note; + done<=true;finish;wait; + end process; + watchdog:process begin wait for 10 ms;assert done report "mallet_tb timeout" severity failure;wait;end process; +end architecture; diff --git a/src/tb/midi_frontend_tb.vhd b/src/tb/midi_frontend_tb.vhd index 9787dcc..d634be4 100644 --- a/src/tb/midi_frontend_tb.vhd +++ b/src/tb/midi_frontend_tb.vhd @@ -199,9 +199,9 @@ begin report "midi_frontend_tb: A4 note/velocity mis-parsed (note " & integer'image(cap_note) & " vel " & integer'image(cap_vel) & ")" severity failure; - assert coeffs.gamma2 = to_q123(0.09) + assert coeffs.gamma2 = to_signed(7210,24) report "midi_frontend_tb: A4 pitch (gamma2) wrong" severity failure; - assert exc_in = vscale(to_q123(0.9), 100) + assert exc_in = vscale(to_q123(0.002), 100) report "midi_frontend_tb: A4 strike amplitude wrong" severity failure; g2_a4 := to_integer(coeffs.gamma2); @@ -215,18 +215,16 @@ begin p := no_count; note_on_msg(81, 100); wait_note_on(p); - assert coeffs.gamma2 = to_q123(0.36) + assert coeffs.gamma2 = to_signed(28837,24) report "midi_frontend_tb: A5 pitch (octave up) not gamma2 x4" severity failure; g2_a5 := to_integer(coeffs.gamma2); assert g2_a5 > g2_a4 report "midi_frontend_tb: higher note did not raise gamma2" severity failure; -------------------------------------------------------------------------- - -- 3. Velocity sensitivity: a harder hit scales both the strike amplitude - -- (louder) and alpha (brighter / more non-linear timbre). Both are held - -- coefficient levels, so this is checked exactly. (Raw pickup energy is - -- deliberately NOT asserted monotonic: with the velocity->alpha coupling - -- the non-linear mesh redistributes energy, which is real behaviour.) + -- 3. Velocity sensitivity: a harder hit scales strike amplitude only. + -- CHAOS is deliberately independent from MIDI velocity so dynamics and + -- non-linearity can be controlled separately from the panel / mod CV. -------------------------------------------------------------------------- p := no_count; note_on_msg(60, 20); @@ -244,8 +242,8 @@ begin report "midi_frontend_tb: harder hit did not raise strike amplitude (" & integer'image(e_hard) & " <= " & integer'image(e_soft) & ")" severity failure; - assert g2_a5 > g2_a4 - report "midi_frontend_tb: harder hit did not raise alpha (timbre)" + assert g2_a5 = 0 and g2_a4 = 0 + report "midi_frontend_tb: velocity changed CHAOS" severity failure; -- and the mesh actually makes sound in response to a strike (from rest) diff --git a/src/tb/musical_controls_tb.vhd b/src/tb/musical_controls_tb.vhd new file mode 100644 index 0000000..0d85c6f --- /dev/null +++ b/src/tb/musical_controls_tb.vhd @@ -0,0 +1,80 @@ +-- End-to-end differential acceptance: only one control differs between DUTs. +library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +use std.env.all; use work.fdtd_pkg.all; +entity musical_controls_tb is end; +architecture sim of musical_controls_tb is + signal clk,mclk: std_logic:='0'; signal rst:std_logic:='1'; signal midi:std_logic:='1'; + signal we:std_logic:='0'; signal wa:unsigned(3 downto 0):=(others=>'0'); + signal wd:std_logic_vector(23 downto 0):=(others=>'0'); + signal ba,bb,sa,sb,da,db,va,vb:std_logic; + signal la,ra,lb,rb:q123_t; + signal measuring:boolean:=false; + signal changed,sounded,clipped:boolean:=false; +begin + clk<=not clk after 5 ns; mclk<=not mclk after 41 ns; + a:entity work.synth_top generic map(NVOICES=>1,NX=>8,NY=>8,OS=>4,TIME_MUX=>true,CLK_HZ=>1_000_000) + port map(sys_clk=>clk,sys_rst=>rst,mclk=>mclk,midi_rx=>midi,cfg_rd_data=>open, + codec_mclk=>open,codec_bclk=>ba,codec_lrclk=>sa,sd_tx=>da,active=>open); + b:entity work.synth_top generic map(NVOICES=>1,NX=>8,NY=>8,OS=>4,TIME_MUX=>true,CLK_HZ=>1_000_000) + port map(sys_clk=>clk,sys_rst=>rst,mclk=>mclk,midi_rx=>midi,cfg_rd_data=>open, + cfg_wr_en=>we,cfg_wr_addr=>wa,cfg_wr_data=>wd, + codec_mclk=>open,codec_bclk=>bb,codec_lrclk=>sb,sd_tx=>db,active=>open); + ca:entity work.i2s_transceiver port map(rst=>rst,bclk=>ba,lrclk=>sa,sd_rx=>da,sd_tx=>open, + rx_l=>la,rx_r=>ra,rx_valid=>va,tx_l=>Q123_ZERO,tx_r=>Q123_ZERO); + cb:entity work.i2s_transceiver port map(rst=>rst,bclk=>bb,lrclk=>sb,sd_rx=>db,sd_tx=>open, + rx_l=>lb,rx_r=>rb,rx_valid=>vb,tx_l=>Q123_ZERO,tx_r=>Q123_ZERO); + monitor:process begin + wait until rising_edge(ba); wait for 1 ps; -- allow both loopback decoders to settle + if rst='1' then changed<=false;sounded<=false;clipped<=false; + elsif measuring and va='1' then + assert vb='1' report "Differential I2S decoders lost frame alignment" severity failure; + assert not is_x(std_logic_vector(la & ra & lb & rb)) severity failure; + if la/=lb or ra/=rb then changed<=true; end if; + if la/=0 and lb/=0 then sounded<=true; end if; + if la=Q123_MIN or la=Q123_MAX or lb=Q123_MIN or lb=Q123_MAX then clipped<=true; end if; + end if; + end process; + process + procedure ticks(n:positive) is begin for k in 1 to n loop wait until falling_edge(clk);end loop;end; + procedure wr(addr:natural;value:real) is begin + wa<=to_unsigned(addr,4);wd<=std_logic_vector(to_q123(value));we<='1';ticks(2);we<='0';ticks(2); + end; + procedure send(v:natural) is begin + midi<='0';ticks(32); + for k in 0 to 7 loop + if (v/2**k) mod 2=1 then midi<='1';else midi<='0';end if;ticks(32); + end loop; + midi<='1';ticks(64); + end; + procedure frames(n:positive) is begin + for k in 1 to n loop wait until rising_edge(ba) and va='1';end loop; + end; + begin + for test in 0 to 7 loop + measuring<=false;rst<='1';we<='0';ticks(100);rst<='0';ticks(100); + case test is + when 1=>wr(0,0.5); -- tension, not just a disconnected register + when 2=>wr(3,0.4); -- independently set CHAOS at identical note velocity + when 3=>wa<=x"5";wd<=x"000000";we<='1';ticks(2);we<='0'; -- left pickup + when 4=>wa<=x"9";wd<=x"000001";we<='1';ticks(2);we<='0'; -- boundary + when 5=>wr(1,0.9998);wr(2,0.9998); -- decay + when 6=>wa<=x"5";wd<=x"600002";we<='1';ticks(2);we<='0'; -- STIFFNESS=0x60, keep L pickup X=2 + when 7=>wa<=x"6";wd<=x"800004";we<='1';ticks(2);we<='0'; -- HARDNESS=0x80, physical mallet, keep L pickup Y=4 + when others=>null; + end case; + ticks(10);send(16#90#);send(57);send(96); + frames(8); -- flush reset/CDC/I2S startup pipeline before strict measurement + measuring<=true;frames(96);measuring<=false;ticks(10); + assert sounded report "Control acceptance produced silence" severity failure; + assert not clipped report "Control acceptance clipped output" severity failure; + if test=0 then + assert not changed report "Identical DUTs differ" severity failure; + else + assert changed report "Control did not reach audio: case "&integer'image(test) severity failure; + end if; + report "musical_controls_tb: control case "&integer'image(test)&" passed through I2S"; + end loop; + finish;wait; + end process; + process begin wait for 100 ms;assert false report "musical_controls_tb watchdog" severity failure;wait;end process; +end; diff --git a/src/tb/musical_refine_tb.vhd b/src/tb/musical_refine_tb.vhd new file mode 100644 index 0000000..888b719 --- /dev/null +++ b/src/tb/musical_refine_tb.vhd @@ -0,0 +1,153 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.env.all; +library work; +use work.fdtd_pkg.all; +use work.physical_pkg.all; + +entity musical_refine_tb is end entity; +architecture sim of musical_refine_tb is + constant T:time:=10 ns; + signal clk:std_logic:='0'; signal rst:std_logic:='1'; signal frame:std_logic:='0'; + signal coeffs:coeffs_t; + signal free_m:boolean:=false; + signal mat:material_t:=(others=>'0'); signal exmode:exciter_t:=(others=>'0'); + signal aniso:aniso_t:=(others=>'0'); + signal rim,size,hardness:unsigned(7 downto 0):=(others=>'0'); + signal sx:natural range 0 to 7:=2; signal sy:natural range 0 to 7:=2; + signal sfx,sfy,lfx,lfy,rfx,rfy:frac2_t:=(others=>'0'); + signal exc:q123_t:=Q123_ZERO; signal exen:std_logic:='0'; + signal sl,sr,tl,tr:q123_t; signal sv,tv:std_logic; + signal p_on,p_off:std_logic:='0'; signal p_note:std_logic_vector(6 downto 0):=(others=>'0'); + signal pl,pr:q123_t; signal pv:std_logic; signal pact:std_logic_vector(0 downto 0); + signal done:boolean:=false; +begin + clock:process begin + while not done loop clk<='0';wait for T/2;clk<='1';wait for T/2;end loop;wait; + end process; + + spatial:entity work.mesh_resonator + generic map(NX=>8,NY=>8,OS=>4,TIME_MUX=>false,BALANCED_FREE_STRIKE=>true, + HF_DAMPING=>true,STRIKE_SHAPING=>true) + port map(free_mode=>free_m, + tap_lfx=>lfx,tap_lfy=>lfy,tap_rfx=>rfx,tap_rfy=>rfy, + material=>mat,exciter_mode=>exmode,anisotropy=>aniso, + hardness_ctrl=>hardness,rim_ctrl=>rim,strike_size=>size, + strike_x=>sx,strike_y=>sy,strike_fx=>sfx,strike_fy=>sfy, + clk=>clk,rst=>rst,frame=>frame,coeffs=>coeffs, + exc_in=>exc,exc_en=>exen,out_l=>sl,out_r=>sr,out_valid=>sv); + + folded:entity work.mesh_resonator + generic map(NX=>8,NY=>8,OS=>4,TIME_MUX=>true,BALANCED_FREE_STRIKE=>true, + HF_DAMPING=>true,STRIKE_SHAPING=>true) + port map(free_mode=>free_m, + tap_lfx=>lfx,tap_lfy=>lfy,tap_rfx=>rfx,tap_rfy=>rfy, + material=>mat,exciter_mode=>exmode,anisotropy=>aniso, + hardness_ctrl=>hardness,rim_ctrl=>rim,strike_size=>size, + strike_x=>sx,strike_y=>sy,strike_fx=>sfx,strike_fy=>sfy, + clk=>clk,rst=>rst,frame=>frame,coeffs=>coeffs, + exc_in=>exc,exc_en=>exen,out_l=>tl,out_r=>tr,out_valid=>tv); + + musical_poly:entity work.poly_voices + generic map(MUSICAL_VOICES=>true,NVOICES=>1,NX=>8,NY=>8,OS=>4,TIME_MUX=>true) + port map(free_mode=>free_m,clk=>clk,rst=>rst,frame=>frame, + note_on=>p_on,note_off=>p_off,note=>p_note,coeffs_in=>coeffs,exc_in=>exc, + out_l=>pl,out_r=>pr,out_valid=>pv,active=>pact); + stim:process + procedure step is begin wait until rising_edge(clk); end; + procedure one_frame(strike:boolean; amp:real; variable energy:inout integer) is + variable a,b,c,d:integer; + begin + exc<=to_q123(amp); if strike then exen<='1';else exen<='0';end if; + frame<='1';step;frame<='0'; + loop step; exit when sv='1'; end loop; a:=to_integer(sl);b:=to_integer(sr); + loop step; exit when tv='1'; end loop; c:=to_integer(tl);d:=to_integer(tr); + exen<='0'; + assert a=c and b=d report "musical_refine_tb: spatial/TDM mismatch" severity failure; + energy:=energy+abs(a)+abs(b); + end; + procedure poly_strike(n:natural) is + begin + p_note<=std_logic_vector(to_unsigned(n,7)); p_on<='1'; step; p_on<='0'; step; step; + end; + procedure poly_frames(n:natural; variable energy:inout integer) is + begin + for k in 1 to n loop + frame<='1';step;frame<='0'; + loop step; exit when pv='1'; end loop; + energy:=energy+abs(to_integer(pl))+abs(to_integer(pr)); + end loop; + end; + variable hard_energy,soft_energy,free_energy,physical_energy,shape_energy,scrape_energy,scrape_hard_energy,human_a,human_b:integer:=0; + begin + coeffs<=(gamma2=>to_q123(0.18),a0=>to_q123(0.99997), + sigk1=>to_q123(0.99997),alpha=>to_q123(0.03), + gamma2_max=>to_q123(0.451)); + rst<='1';step;step;rst<='0';step; + for f in 0 to 47 loop one_frame(f=0,0.72,hard_energy); end loop; + assert hard_energy>0 report "musical_refine_tb: hard shaped strike silent" severity failure; + + rst<='1';step;step;rst<='0';step; + for f in 0 to 47 loop one_frame(f=0,0.18,soft_energy); end loop; + assert soft_energy>0 report "musical_refine_tb: soft shaped strike silent" severity failure; + assert hard_energy/=soft_energy + report "musical_refine_tb: velocity-dependent strike shaping had no effect" severity failure; + + free_m<=true; rst<='1';step;step;rst<='0';step; + for f in 0 to 47 loop one_frame(f=0,0.55,free_energy); end loop; + assert free_energy>0 report "musical_refine_tb: balanced free-boundary strike silent" severity failure; + + -- New physical-model pass: MATERIAL + explicit anisotropy + quarter-grid + -- strike/pickup positions must remain bit-exact across the two backends. + free_m<=false; mat<=to_unsigned(3,3); aniso<=to_signed(2,4); exmode<=(others=>'0'); + sfx<=to_unsigned(1,2); sfy<=to_unsigned(2,2); + lfx<=to_unsigned(2,2); lfy<=to_unsigned(1,2); rfx<=to_unsigned(1,2); rfy<=to_unsigned(3,2); + rst<='1';step;step;rst<='0';step; + for f in 0 to 47 loop one_frame(f=0,0.55,physical_energy); end loop; + assert physical_energy>0 and physical_energy/=hard_energy + report "musical_refine_tb: MATERIAL/anisotropy/fractional geometry had no effect" severity failure; + assert material_alpha(to_q123(0.20),to_unsigned(3,3))>to_q123(0.20) + report "musical_refine_tb: metal MATERIAL did not increase nonlinearity macro" severity failure; + + -- Mode-B membrane controls: compliant rim, broad contact and moved strike. + mat<=(others=>'0');aniso<=(others=>'0');rim<=x"80";size<=x"C0";sx<=3;sy<=4; + sfx<=to_unsigned(2,2);sfy<=to_unsigned(1,2);exmode<=(others=>'0'); + rst<='1';step;step;rst<='0';step; + for f in 0 to 47 loop one_frame(f=0,0.55,shape_energy); end loop; + assert shape_energy>0 and shape_energy/=hard_energy + report "musical_refine_tb: RIM/STRIKE SIZE/XY had no effect" severity failure; + + -- Explicit scrape/bow-burst mode uses all four oversample substeps. + mat<=(others=>'0'); aniso<=(others=>'0');rim<=(others=>'0');size<=(others=>'0');sx<=2;sy<=2; + exmode<=to_unsigned(5,3); + sfx<=(others=>'0'); sfy<=(others=>'0'); lfx<=(others=>'0'); lfy<=(others=>'0'); + rfx<=(others=>'0'); rfy<=(others=>'0'); + rst<='1';step;step;rst<='0';step; + for f in 0 to 31 loop one_frame(f=0,0.55,scrape_energy); end loop; + assert scrape_energy>0 and scrape_energy/=hard_energy + report "musical_refine_tb: explicit scrape exciter had no distinct response" severity failure; + + -- HARDNESS must not hijack explicit non-mallet CHARACTER modes. With + -- SCRAPE selected, enabling HARDNESS must be bit-identical to the legacy + -- scrape envelope after reset. + hardness<=x"80";rst<='1';step;step;rst<='0';step; + for f in 0 to 31 loop one_frame(f=0,0.55,scrape_hard_energy); end loop; + assert scrape_hard_energy=scrape_energy + report "musical_refine_tb: HARDNESS altered explicit SCRAPE mode" severity failure; + hardness<=(others=>'0'); + + -- Same note/velocity twice without global reset: musical_poly advances its + -- deterministic LFSR, varying strike level and pickup coordinates slightly. + free_m<=false; rst<='1';step;step;rst<='0';step; exc<=to_q123(0.48); exen<='0'; + poly_strike(60); poly_frames(12,human_a); + poly_strike(60); poly_frames(12,human_b); + assert human_a>0 and human_b>0 report "musical_refine_tb: humanized poly strike silent" severity failure; + assert human_a/=human_b report "musical_refine_tb: repeated musical strikes were identical" severity failure; + + report "musical_refine_tb: shaped strikes + HF damping bit-exact across backends; repeated-note micro-variation active" + severity note; + done<=true;finish;wait; + end process; + watchdog:process begin wait for 10 ms;assert done report "musical_refine_tb timeout" severity failure;wait;end process; +end architecture; diff --git a/src/tb/panel_ctrl_tb.vhd b/src/tb/panel_ctrl_tb.vhd index 0331eb3..232a53d 100644 --- a/src/tb/panel_ctrl_tb.vhd +++ b/src/tb/panel_ctrl_tb.vhd @@ -1,176 +1,143 @@ -------------------------------------------------------------------------------- --- panel_ctrl_tb.vhd - panel knobs/encoder drive the engine (issue #78) --- --- Wires panel_ctrl into a real preset_bank and checks that the front panel --- reaches the engine coefficients: --- * moving a pot writes the mapped coefficient (pitch->gamma2, timbre->alpha, --- decay->sigk1 & a0) and the change shows on preset_bank.coeffs; --- * stable pots produce no further writes (dead-band); --- * the encoder steps preset_index, and a short button press recalls the --- selected preset (coeffs load the factory values); a long press emits save. --- --- The long-press threshold is shrunk via a generic for a fast simulation. --- --- VHDL-2008. -------------------------------------------------------------------------------- - library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.env.all; - library work; use work.fdtd_pkg.all; -entity panel_ctrl_tb is -end entity panel_ctrl_tb; - +entity panel_ctrl_tb is end; architecture sim of panel_ctrl_tb is - - constant CLK_PERIOD : time := 10 ns; - constant POT_W : positive := 12; - - signal clk : std_logic := '0'; - signal rst : std_logic := '1'; - - signal pot_pitch, pot_decay, pot_timbre : unsigned(POT_W-1 downto 0) := (others => '0'); - signal enc_a, enc_b, enc_btn : std_logic := '0'; - - signal cfg_wr_en : std_logic; - signal cfg_wr_addr : unsigned(3 downto 0); - signal cfg_wr_data : std_logic_vector(23 downto 0); - signal p_index : unsigned(3 downto 0); - signal p_recall : std_logic; - signal p_save : std_logic; - - signal coeffs : coeffs_t; - - signal done : boolean := false; - signal recall_seen, save_seen : integer := 0; - + constant T:time:=10 ns; constant POT_W:positive:=12; + signal clk:std_logic:='0'; signal rst:std_logic:='1'; signal mode:std_logic:='0'; + signal p0,p1,p2,p3,p4,p5:unsigned(POT_W-1 downto 0):=(others=>'0'); + signal ea,eb,btn:std_logic:='0'; + signal we:std_logic; signal wa,ra:unsigned(3 downto 0); + signal wd,rd:std_logic_vector(23 downto 0); + signal pi:unsigned(3 downto 0);signal recall,save:std_logic; + signal edit_page:unsigned(1 downto 0); signal edit_leds:std_logic_vector(3 downto 0); + signal c:coeffs_t; signal phys,fx0,fx1,fx2,fx3,fx4,fx5:std_logic_vector(23 downto 0); + signal rim,ss,sx,sy:unsigned(7 downto 0); + signal done:boolean:=false; signal recalls,saves:integer:=0; begin - - clk_gen : process begin - while not done loop clk <= '0'; wait for CLK_PERIOD/2; clk <= '1'; wait for CLK_PERIOD/2; end loop; wait; - end process; - - watchdog : process begin - wait for 2 ms; - assert done report "panel_ctrl_tb: timeout" severity failure; - wait; - end process; - - dut : entity work.panel_ctrl - generic map (POT_W => POT_W, N_PRESETS => 7, DEADBAND => 4096, LONG_CYC => 200) - port map (clk => clk, rst => rst, - pot_pitch => pot_pitch, pot_decay => pot_decay, pot_timbre => pot_timbre, - enc_a => enc_a, enc_b => enc_b, enc_btn => enc_btn, - cfg_wr_en => cfg_wr_en, cfg_wr_addr => cfg_wr_addr, cfg_wr_data => cfg_wr_data, - preset_index => p_index, preset_recall => p_recall, preset_save => p_save); - - bank : entity work.preset_bank - port map (clk => clk, rst => rst, - wr_en => cfg_wr_en, wr_addr => cfg_wr_addr, wr_data => cfg_wr_data, - rd_addr => (others => '0'), rd_data => open, - preset_index => p_index, recall => p_recall, save => p_save, - coeffs => coeffs, - pick_lx => open, pick_ly => open, pick_rx => open, pick_ry => open, - free_boundary => open); - - -- latch the recall/save pulses - mon : process (clk) begin - if rising_edge(clk) then - if p_recall = '1' then recall_seen <= recall_seen + 1; end if; - if p_save = '1' then save_seen <= save_seen + 1; end if; - end if; - end process; - - stim : process - procedure step is begin wait until rising_edge(clk); end procedure; - procedure settle is begin for i in 0 to 15 loop step; end loop; end procedure; - - -- one encoder detent: rising edge of A with B held for direction - procedure enc_step(up : boolean) is - begin - enc_b <= '0' when up else '1'; - step; - enc_a <= '1'; for i in 0 to 5 loop step; end loop; -- A rising (synced) - enc_a <= '0'; for i in 0 to 5 loop step; end loop; - end procedure; - - variable g_lo, g_mid, al_hi, sk_dec : integer; + clock:process begin while not done loop clk<='0';wait for T/2;clk<='1';wait for T/2;end loop;wait;end process; + watchdog:process begin wait for 4 ms;assert done report "panel_ctrl_tb timeout" severity failure;wait;end process; + + -- Three pages exercise the generic page selector. Only page 0 (SURFACE) is + -- populated by issue #85; pages 1/2 must be inert until later features land. + dut:entity work.panel_ctrl + generic map(POT_W=>POT_W,N_PRESETS=>7,N_EDIT_PAGES=>3,DEADBAND=>4096,LONG_CYC=>200) + port map(clk=>clk,rst=>rst,edit_mode=>mode,pot_pitch=>p0,pot_decay=>p1,pot_timbre=>p2, + pot_drive=>p3,pot_delay=>p4,pot_reverb=>p5,enc_a=>ea,enc_b=>eb,enc_btn=>btn, + cfg_wr_en=>we,cfg_wr_addr=>wa,cfg_wr_data=>wd,cfg_rd_addr=>ra,cfg_rd_data=>rd, + preset_index=>pi,preset_recall=>recall,preset_save=>save, + edit_page=>edit_page,edit_leds=>edit_leds); + bank:entity work.preset_bank + port map(clk=>clk,rst=>rst,wr_en=>we,wr_addr=>wa,wr_data=>wd,rd_addr=>ra,rd_data=>rd, + preset_index=>pi,recall=>recall,save=>save,coeffs=>c,pick_lx=>open,pick_ly=>open, + pick_rx=>open,pick_ry=>open,free_boundary=>open,physical_ctrl=>phys, + rim_ctrl=>rim,strike_size=>ss,strike_x_ctrl=>sx,strike_y_ctrl=>sy, + stiffness_ctrl=>open,hardness_ctrl=>open, + fx_ctrl0=>fx0,fx_ctrl1=>fx1,fx_ctrl2=>fx2,fx_ctrl3=>fx3,fx_ctrl4=>fx4,fx_ctrl5=>fx5); + mon:process(clk) begin if rising_edge(clk) then if recall='1' then recalls<=recalls+1;end if; + if save='1' then saves<=saves+1;end if;end if;end process; + + stim:process + procedure step is begin wait until rising_edge(clk);end; + procedure settle is begin for i in 1 to 140 loop step;end loop;end; + procedure enc(up:boolean) is begin eb<='0' when up else '1';step;ea<='1';for i in 1 to 6 loop step;end loop; + ea<='0';for i in 1 to 6 loop step;end loop;end; + procedure short_press is begin btn<='1';for i in 1 to 20 loop step;end loop;btn<='0';settle;end; + procedure long_press is begin btn<='1';for i in 1 to 260 loop step;end loop;btn<='0';settle;end; + variable g_hold:signed(23 downto 0); variable f_hold:std_logic_vector(23 downto 0); + variable phys_hold:std_logic_vector(23 downto 0); + variable rim_hold,ss_hold,sx_hold,sy_hold:unsigned(7 downto 0); + variable pi_hold:unsigned(3 downto 0); begin - rst <= '1'; for i in 0 to 9 loop step; end loop; rst <= '0'; - settle; -- startup writes (pots at 0) settle - - -- pots at 0 -> the LO end of each range - g_lo := to_integer(coeffs.gamma2); - assert g_lo = to_integer(to_q123(0.02)) - report "panel_ctrl_tb: pitch pot=0 did not map to gamma2 LO" severity failure; - - -------------------------------------------------------------------------- - -- 1. move pitch pot -> gamma2 rises to the scaled value - -------------------------------------------------------------------------- - pot_pitch <= to_unsigned(2048, POT_W); -- half scale -> ~0.23 + rst<='1';for i in 1 to 10 loop step;end loop;rst<='0';settle; + assert edit_page=0 and edit_leds="0000" report "panel_ctrl_tb: reset page/LED state failed" severity failure; + assert c.gamma2=to_q123(0.09) report "panel_ctrl_tb: boot moved TENSION before pickup" severity failure; + assert fx0=x"FC6200" and fx2=x"2EE040" and fx4=x"D26446" + report "panel_ctrl_tb: boot moved FX before pickup" severity failure; + + -- PLAY: sweep across stored values to arm, then controls track. + p0<=to_unsigned(4095,POT_W);settle; + assert c.gamma2>to_q123(0.9) report "panel_ctrl_tb: TENSION soft takeover/write failed" severity failure; + p1<=to_unsigned(4095,POT_W);settle; + assert c.a0=c.sigk1 and c.sigk1>to_q123(0.9999) report "panel_ctrl_tb: DECAY failed" severity failure; + p2<=to_unsigned(4095,POT_W);settle; + assert c.alpha>to_q123(0.3) report "panel_ctrl_tb: CHAOS failed" severity failure; + p3<=to_unsigned(4095,POT_W);p4<=to_unsigned(2048,POT_W);p5<=to_unsigned(4095,POT_W);settle; + assert unsigned(fx0(17 downto 10))=255 and unsigned(fx2(7 downto 0))=128 and unsigned(fx4(7 downto 0))=255 + report "panel_ctrl_tb: PLAY FX layer failed" severity failure; + + -- Enter EDIT/SURFACE. Merely switching must not edit anything. + p0<=to_unsigned(2048,POT_W);p1<=(others=>'0');p2<=(others=>'0'); + p3<=(others=>'0');p4<=(others=>'0');p5<=(others=>'0');settle; + g_hold:=c.gamma2;f_hold:=fx0;mode<='1';settle; + assert edit_page=0 and edit_leds="0001" report "panel_ctrl_tb: SURFACE page indication failed" severity failure; + assert c.gamma2=g_hold and fx0=f_hold and phys(10 downto 4)="0000000" and rim=0 and ss=0 and sx=0 and sy=0 + report "panel_ctrl_tb: PLAY->EDIT switch caused parameter jump" severity failure; + + -- SURFACE page: ANISO/RIM/SIZE/X/Y/CHARACTER. + p0<=to_unsigned(4095,POT_W);p1<=to_unsigned(4095,POT_W);p2<=to_unsigned(3072,POT_W); + p3<=to_unsigned(1024,POT_W);p4<=to_unsigned(2048,POT_W);p5<=to_unsigned(1536,POT_W);settle; + assert signed(phys(10 downto 7))=to_signed(7,4) report "panel_ctrl_tb: ANISO failed" severity failure; + assert rim=255 and ss=192 and sx=64 and sy=128 report "panel_ctrl_tb: RIM/SIZE/STRIKE XY failed" severity failure; + assert unsigned(phys(6 downto 4))=3 report "panel_ctrl_tb: CHARACTER failed" severity failure; + + -- In EDIT the encoder changes page, never preset. Reserved pages are inert. + phys_hold:=phys;rim_hold:=rim;ss_hold:=ss;sx_hold:=sx;sy_hold:=sy;pi_hold:=pi; + enc(true); + assert edit_page=1 and edit_leds="0010" and pi=pi_hold + report "panel_ctrl_tb: encoder did not select EDIT page 1 cleanly" severity failure; + p0<=(others=>'0');p1<=(others=>'0');p2<=(others=>'0');p3<=to_unsigned(4095,POT_W); + p4<=to_unsigned(4095,POT_W);p5<=to_unsigned(4095,POT_W);settle; + assert phys=phys_hold and rim=rim_hold and ss=ss_hold and sx=sx_hold and sy=sy_hold + report "panel_ctrl_tb: reserved EDIT page aliased SURFACE controls" severity failure; + + short_press; long_press; + assert recalls=0 and saves=0 and pi=pi_hold + report "panel_ctrl_tb: EDIT button gesture leaked into preset recall/save" severity failure; + + -- A press that begins in EDIT must not turn into a preset action if MODE is + -- flipped to PLAY before the button is released. + btn<='1';for i in 1 to 20 loop step;end loop;mode<='0';settle; + btn<='0';settle; + assert recalls=0 and saves=0 and pi=pi_hold + report "panel_ctrl_tb: EDIT-held button leaked after return to PLAY" severity failure; + mode<='1';settle; + assert edit_page=1 and edit_leds="0010" report "panel_ctrl_tb: page memory lost across held-button transition" severity failure; + + enc(true); + assert edit_page=2 and edit_leds="0100" and pi=pi_hold + report "panel_ctrl_tb: encoder did not select EDIT page 2" severity failure; + enc(true); + assert edit_page=0 and edit_leds="0001" report "panel_ctrl_tb: forward page wrap failed" severity failure; settle; - g_mid := to_integer(coeffs.gamma2); - assert g_mid > g_lo and abs(g_mid - to_integer(to_q123(0.23))) < to_integer(to_q123(0.01)) - report "panel_ctrl_tb: pitch pot did not scale gamma2 (" & integer'image(g_mid) & ")" - severity failure; - - -------------------------------------------------------------------------- - -- 2. timbre pot -> alpha ; decay pot -> sigk1 (and a0) - -------------------------------------------------------------------------- - pot_timbre <= to_unsigned(4095, POT_W); -- full -> ~ALPHA_HI - pot_decay <= to_unsigned(4095, POT_W); -- full -> ~DECAY_HI - settle; - al_hi := to_integer(coeffs.alpha); - sk_dec := to_integer(coeffs.sigk1); - assert al_hi > to_integer(to_q123(0.3)) - report "panel_ctrl_tb: timbre pot did not raise alpha" severity failure; - assert sk_dec > to_integer(to_q123(0.999)) and coeffs.a0 = coeffs.sigk1 - report "panel_ctrl_tb: decay pot did not set sigk1/a0" severity failure; - - -------------------------------------------------------------------------- - -- 3. stable pots -> no more writes - -------------------------------------------------------------------------- - assert cfg_wr_en = '0' report "startup transient" severity note; -- informational - for i in 0 to 40 loop - step; - assert cfg_wr_en = '0' - report "panel_ctrl_tb: writing with stable pots (dead-band failed)" severity failure; - end loop; - - -------------------------------------------------------------------------- - -- 4. encoder steps preset_index - -------------------------------------------------------------------------- - enc_step(true); -- -> 1 - assert p_index = to_unsigned(1, 4) - report "panel_ctrl_tb: encoder up did not step preset_index" severity failure; - - -------------------------------------------------------------------------- - -- 5. short button press -> recall the selected preset (gong = index 1) - -------------------------------------------------------------------------- - enc_btn <= '1'; for i in 0 to 20 loop step; end loop; -- < LONG_CYC (200) - enc_btn <= '0'; settle; - assert recall_seen = 1 and save_seen = 0 - report "panel_ctrl_tb: short press did not recall" severity failure; - assert coeffs.gamma2 = to_q123(0.300) - report "panel_ctrl_tb: recall did not load the gong preset" severity failure; - - -------------------------------------------------------------------------- - -- 6. long button press -> save - -------------------------------------------------------------------------- - enc_step(true); enc_step(true); -- move to a user slot (index 3) - enc_btn <= '1'; for i in 0 to 260 loop step; end loop; -- > LONG_CYC - enc_btn <= '0'; settle; - assert save_seen = 1 and recall_seen = 1 - report "panel_ctrl_tb: long press did not save (or double-recalled)" severity failure; - - report "panel_ctrl_tb: all checks passed (pots -> coeffs; dead-band; encoder " & - "-> preset_index; short=recall, long=save)" severity note; - done <= true; - finish; + assert phys=phys_hold and rim=rim_hold and ss=ss_hold and sx=sx_hold and sy=sy_hold + report "panel_ctrl_tb: page return bypassed soft takeover" severity failure; + enc(false); + assert edit_page=2 and edit_leds="0100" report "panel_ctrl_tb: reverse page wrap failed" severity failure; + + -- Page selection is remembered while PLAY hides the page LEDs. + mode<='0';settle; + assert edit_page=2 and edit_leds="0000" report "panel_ctrl_tb: PLAY did not retain/hide EDIT page" severity failure; + assert c.gamma2=g_hold and fx0=f_hold report "panel_ctrl_tb: EDIT->PLAY switch jumped controls" severity failure; + mode<='1';settle; + assert edit_page=2 and edit_leds="0100" report "panel_ctrl_tb: EDIT page memory failed" severity failure; + enc(true); -- page 2 -> page 0 for later checks + assert edit_page=0 and edit_leds="0001" severity failure; + + -- Return to PLAY: encoder resumes preset navigation and button actions. + mode<='0';settle; + enc(true); assert pi=1 report "panel_ctrl_tb: PLAY encoder preset select failed" severity failure; + short_press; + assert recalls=1 and saves=0 and c.gamma2=to_q123(0.300) + report "panel_ctrl_tb: PLAY short recall failed" severity failure; + enc(true);enc(true);long_press; + assert saves=1 report "panel_ctrl_tb: PLAY long save failed" severity failure; + + report "panel_ctrl_tb: PLAY/EDIT pages + soft takeover + contextual encoder checks passed" severity note; + done<=true;finish;wait; end process; - -end architecture sim; +end architecture; diff --git a/src/tb/pitch_calibration_tb.vhd b/src/tb/pitch_calibration_tb.vhd new file mode 100644 index 0000000..988128b --- /dev/null +++ b/src/tb/pitch_calibration_tb.vhd @@ -0,0 +1,40 @@ +library ieee; +use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; +use std.env.all; use work.fdtd_pkg.all; use work.musical_pkg.all; +entity pitch_calibration_tb is end; +architecture sim of pitch_calibration_tb is begin + process + variable g,lambda,hz,measured,cents: real; + variable side,overs,rate: positive; + variable q: q123_t; variable tests: natural:=0; + begin + for mesh_size in 0 to 1 loop + side:=8+mesh_size*8; + for o in 0 to 2 loop + overs:=2**o; + for r in 1 to 2 loop + rate:=48000*r; + for free in boolean loop + if free then lambda:=2.0-2.0*cos(MATH_PI/real(side-1)); + else lambda:=4.0-4.0*cos(MATH_PI/real(side+1)); end if; + for octave in 0 to 3 loop + hz:=110.0*2.0**octave; + q:=note_gamma2(45+12*octave,side,side,overs,rate,free); + g:=real(to_integer(q))/real(2**23); + measured:=real(rate*overs)/MATH_PI*arcsin(sqrt(g*lambda)/2.0); + cents:=1200.0*log(measured/hz)/log(2.0); + assert abs(cents)<5.0 report "Pitch error "&real'image(cents)&" cents" severity failure; + assert tension_scale(q,to_q123(0.25))=q report "Unity tension lost coefficient precision" severity failure; + tests:=tests+1; + end loop; + end loop; + end loop; + end loop; + end loop; + assert note_gamma2(38,8,8,4,48000,false)/=note_gamma2(40,8,8,4,48000,false) + report "Old low-note pitch-floor plateau returned" severity failure; + assert coordinate(to_unsigned(255,8),8)=7 severity failure; + report "pitch_calibration_tb: "&integer'image(tests)&" grid/rate/OS/boundary pitch cases passed"; + finish; wait; + end process; +end; diff --git a/src/tb/preset_bank_tb.vhd b/src/tb/preset_bank_tb.vhd index cd55840..1b0339f 100644 --- a/src/tb/preset_bank_tb.vhd +++ b/src/tb/preset_bank_tb.vhd @@ -46,6 +46,9 @@ architecture sim of preset_bank_tb is signal coeffs : coeffs_t; signal pick_lx, pick_ly, pick_rx, pick_ry : unsigned(COORD_W-1 downto 0); signal free_boundary : std_logic; + signal phys : std_logic_vector(23 downto 0); + signal rim,size,sx,sy,stiffness,hardness : unsigned(7 downto 0); + signal fx0, fx1, fx2, fx3, fx4, fx5 : std_logic_vector(23 downto 0); signal done : boolean := false; @@ -69,7 +72,11 @@ begin preset_index => preset_index, recall => recall, save => save, coeffs => coeffs, pick_lx => pick_lx, pick_ly => pick_ly, pick_rx => pick_rx, pick_ry => pick_ry, - free_boundary => free_boundary); + free_boundary => free_boundary, physical_ctrl=>phys, + rim_ctrl=>rim,strike_size=>size,strike_x_ctrl=>sx,strike_y_ctrl=>sy, + stiffness_ctrl=>stiffness,hardness_ctrl=>hardness, + fx_ctrl0=>fx0, fx_ctrl1=>fx1, fx_ctrl2=>fx2, + fx_ctrl3=>fx3, fx_ctrl4=>fx4, fx_ctrl5=>fx5); stim : process procedure step is begin wait until rising_edge(clk); end procedure; @@ -107,7 +114,11 @@ begin -- reset default: linear operating point assert coeffs.gamma2 = to_q123(0.09) and coeffs.alpha = to_q123(0.0) + and stiffness=0 and hardness=0 report "preset_bank_tb: reset default wrong" severity failure; + assert fx0=x"FC6200" and fx1=x"306040" and fx2=x"2EE040" + and fx3=x"6E50C0" and fx4=x"D26446" and fx5=x"B496FF" + report "preset_bank_tb: FX defaults wrong" severity failure; -- factory 0: drum do_recall(0); @@ -140,6 +151,18 @@ begin do_write(0, saved_g2); assert coeffs.gamma2 = signed(saved_g2) report "preset_bank_tb: per-register edit did not take" severity failure; + do_write(10, x"FC6200"); -- enable stored FX profile + assert fx0 = x"FC6200" + report "preset_bank_tb: FX register edit did not take" severity failure; + do_write(9, x"15552A"); -- packed physical-model controls + assert phys = x"15552A" + report "preset_bank_tb: physical-control register edit did not take" severity failure; + do_write(5, x"A50002"); -- STIFFNESS=A5, RIM=00, pick_lx=2 + assert stiffness=x"A5" and rim=0 and pick_lx=to_unsigned(2,COORD_W) + report "preset_bank_tb: stiffness field edit did not take" severity failure; + do_write(6, x"5A0004"); -- HARDNESS=5A, STRIKE SIZE=00, pick_ly=4 + assert hardness=x"5A" and size=0 and pick_ly=to_unsigned(4,COORD_W) + report "preset_bank_tb: hardness field edit did not take" severity failure; do_save(3); -- user slot 0 -- clobber the live registers with a different factory preset @@ -151,6 +174,14 @@ begin do_recall(3); assert coeffs.gamma2 = signed(saved_g2) report "preset_bank_tb: user preset recall did not restore" severity failure; + assert fx0 = x"FC6200" + report "preset_bank_tb: user preset did not restore FX words" severity failure; + assert phys = x"15552A" + report "preset_bank_tb: user preset did not restore physical controls, got 0x" & to_hstring(phys) severity failure; + assert stiffness=x"A5" + report "preset_bank_tb: user preset did not restore STIFFNESS" severity failure; + assert hardness=x"5A" + report "preset_bank_tb: user preset did not restore HARDNESS" severity failure; -------------------------------------------------------------------------- -- factory slots are read-only diff --git a/src/tb/runtime_mesh_tb.vhd b/src/tb/runtime_mesh_tb.vhd new file mode 100644 index 0000000..9a0dc44 --- /dev/null +++ b/src/tb/runtime_mesh_tb.vhd @@ -0,0 +1,42 @@ +library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all; +use std.env.all;use work.fdtd_pkg.all; +entity runtime_mesh_tb is end; +architecture sim of runtime_mesh_tb is + signal clk:std_logic:='0'; signal rst:std_logic:='1';signal go,exc:std_logic:='0'; + signal free:boolean:=false;signal lx,ly,rx,ry:natural range 0 to 7:=2; + signal al,ar,bl,br:q123_t;signal av,bv:std_logic; + constant c:coeffs_t:=(to_q123(0.02),to_q123(0.9999),to_q123(0.9999),Q123_ZERO,to_q123(0.451)); +begin + clk<=not clk after 5 ns; + a:entity work.mesh generic map(NX=>8,NY=>8,TIME_MUX=>false,EXC_X=>2,EXC_Y=>2,BALANCED_FREE_STRIKE=>true) + port map(clk=>clk,rst=>rst,strobe=>go,coeffs=>c,exc_in=>to_q123(0.002),exc_en=>exc, + free_mode=>free,tap_lx=>lx,tap_ly=>ly,tap_rx=>rx,tap_ry=>ry,pick_l=>al,pick_r=>ar,valid=>av); + b:entity work.mesh generic map(NX=>8,NY=>8,TIME_MUX=>true,EXC_X=>2,EXC_Y=>2,BALANCED_FREE_STRIKE=>true) + port map(clk=>clk,rst=>rst,strobe=>go,coeffs=>c,exc_in=>to_q123(0.002),exc_en=>exc, + free_mode=>free,tap_lx=>lx,tap_ly=>ly,tap_rx=>rx,tap_ry=>ry,pick_l=>bl,pick_r=>br,valid=>bv); + process + variable seen_a,seen_b:boolean;variable va_l,va_r,vb_l,vb_r:q123_t; + begin + for mode in boolean loop + rst<='1';wait for 100 ns;wait until falling_edge(clk);rst<='0';free<=mode; + for step in 0 to 95 loop + lx<=step mod 8;ly<=(step/8) mod 8;rx<=7-step mod 8;ry<=3; + if step=0 then exc<='1';else exc<='0';end if; + wait until falling_edge(clk);go<='1';wait until falling_edge(clk);go<='0'; + seen_a:=false;seen_b:=false; + for k in 0 to 100 loop + wait until rising_edge(clk); + if av='1' then seen_a:=true;va_l:=al;va_r:=ar;end if; + if bv='1' then seen_b:=true;vb_l:=bl;vb_r:=br;end if; + exit when seen_a and seen_b; + end loop; + assert seen_a and seen_b report "Mesh handshake timeout" severity failure; + assert va_l=vb_l and va_r=vb_r report "Runtime boundary/pickup backends differ" severity failure; + wait until falling_edge(clk); + end loop; + end loop; + report "runtime_mesh_tb: 192 dynamic-pickup steps, fixed and balanced-free, bit-exact across backends"; + finish;wait; + end process; + process begin wait for 1 ms;assert false report "watchdog" severity failure;wait;end process; +end; diff --git a/src/tb/stiffness_tb.vhd b/src/tb/stiffness_tb.vhd new file mode 100644 index 0000000..24aaf24 --- /dev/null +++ b/src/tb/stiffness_tb.vhd @@ -0,0 +1,170 @@ +------------------------------------------------------------------------------- +-- stiffness_tb.vhd - runtime bending-stiffness / plate integration (#86) +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.env.all; +use std.textio.all; +library work; +use work.fdtd_pkg.all; +use work.physical_pkg.all; + +entity stiffness_tb is end; +architecture sim of stiffness_tb is + constant T:time:=10 ns; + constant NX:positive:=8; constant NY:positive:=8; + signal clk:std_logic:='0'; signal rst:std_logic:='1'; + signal strobe:std_logic:='0'; signal exc_en:std_logic:='0'; + signal exc:q123_t:=Q123_ZERO; signal coeffs:coeffs_t; + signal stiff,rim:unsigned(7 downto 0):=(others=>'0'); + signal free_mode:boolean:=false; + signal sl,sr,tl,tr,ml,mr:q123_t; + signal sv,tv,mv:std_logic; signal done:boolean:=false; +begin + clock:process begin + while not done loop clk<='0';wait for T/2;clk<='1';wait for T/2;end loop; + wait; + end process; + watchdog:process begin wait for 5 ms; + assert done report "stiffness_tb timeout" severity failure; wait; + end process; + + spatial:entity work.grid_mesh + generic map(NX=>NX,NY=>NY,FREE_BOUNDARY=>false) + port map(clk=>clk,rst=>rst,strobe=>strobe,coeffs=>coeffs, + free_mode=>free_mode,rim_ctrl=>rim,stiffness_ctrl=>stiff,exc_in=>exc,exc_en=>exc_en, + pick_l=>sl,pick_r=>sr,valid=>sv); + + folded:entity work.grid_mesh_tdm + generic map(NX=>NX,NY=>NY,FREE_BOUNDARY=>false) + port map(clk=>clk,rst=>rst,strobe=>strobe,coeffs=>coeffs, + free_mode=>free_mode,rim_ctrl=>rim,stiffness_ctrl=>stiff,exc_in=>exc,exc_en=>exc_en, + pick_l=>tl,pick_r=>tr,valid=>tv); + + membrane:entity work.grid_mesh_tdm + generic map(NX=>NX,NY=>NY,FREE_BOUNDARY=>false) + port map(clk=>clk,rst=>rst,strobe=>strobe,coeffs=>coeffs, + free_mode=>free_mode,rim_ctrl=>rim,stiffness_ctrl=>(others=>'0'),exc_in=>exc,exc_en=>exc_en, + pick_l=>ml,pick_r=>mr,valid=>mv); + + stim:process + procedure tick is begin wait until rising_edge(clk); end; + procedure reset_mesh is begin + rst<='1'; strobe<='0'; exc_en<='0'; exc<=Q123_ZERO; + tick;tick; rst<='0';tick; + end; + procedure fire(first:boolean) is begin + strobe<='1'; + if first then exc<=to_q123(0.9);exc_en<='1';end if; + tick;strobe<='0';exc_en<='0';exc<=Q123_ZERO; + wait until rising_edge(clk) and tv='1'; + end; + procedure fire_count(first:boolean; variable cycles:out natural) is begin + strobe<='1'; + if first then exc<=to_q123(0.9);exc_en<='1';end if; + tick;strobe<='0';exc_en<='0';exc<=Q123_ZERO;cycles:=0; + loop + tick;cycles:=cycles+1; + exit when tv='1'; + end loop; + end; + variable changed:boolean:=false; + variable b:acc_t; variable c:unsigned(7 downto 0); + variable lim:q123_t; + file ft:text; variable fs:file_open_status; variable ln:line; + variable gl,gr:integer; variable cyc:natural; + begin + + -- Production control encoding and shift/add stiffness multiply are exact. + assert stiffness_mu2(x"00")=Q123_ZERO severity failure; + assert stiffness_mu2(x"FF")=shift_left(to_signed(255,Q_BITS),11) + report "stiffness_tb: mu2 encoding mismatch" severity failure; + assert stiff_gamma2_max(to_q123(0.451),x"00")=to_q123(0.451) + report "stiffness_tb: zero-stiffness clamp changed legacy ceiling" severity failure; + assert stiff_gamma2_max(to_q123(0.451),x"80")=to_q123(0.25) + report "stiffness_tb: combined CFL ceiling wrong at STIFFNESS=128" severity failure; + + b:=biharmonic_term(to_q123(0.12),to_q123(-0.04),to_q123(0.03), + to_q123(0.08),to_q123(-0.02),to_q123(0.01),to_q123(-0.07), + to_q123(0.05),to_q123(0.02),to_q123(-0.03),to_q123(0.06), + to_q123(0.04),to_q123(-0.05)); + for k in 0 to 3 loop + case k is + when 0=>c:=x"01"; when 1=>c:=x"40"; + when 2=>c:=x"7F"; when others=>c:=x"FF"; + end case; + assert stiffness_term(b,c)=mul_coeff(stiffness_mu2(c),b) + report "stiffness_tb: shift/add stiffness multiply mismatch" severity failure; + end loop; + + -- Moderate plate: spatial and TDM must remain bit-exact, while nonzero + -- stiffness must audibly/numerically differ from the membrane path. + + coeffs <= (gamma2=>to_q123(0.08),a0=>to_q123(0.9995), + sigk1=>to_q123(0.9995),alpha=>to_q123(0.10), + gamma2_max=>to_q123(0.451)); + stiff<=x"60"; reset_mesh; changed:=false; + file_open(fs,ft,"../src/tb/stiffness_trace.txt",read_mode); + assert fs=open_ok report "stiffness_tb: cannot open stiffness_trace.txt" severity failure; + readline(ft,ln); -- header + for k in 0 to 59 loop + if k=0 then + fire_count(true,cyc); + assert cyc=322 report "stiffness_tb: 8x8 stiff TDM step cycle budget changed, got "&integer'image(cyc) severity failure; + else fire(false); end if; + readline(ft,ln);read(ln,gl);read(ln,gr); + assert to_integer(tl)=gl and to_integer(tr)=gr + report "stiffness_tb: RTL/reference mismatch at step "&integer'image(k) severity failure; + assert sl=tl and sr=tr + report "stiffness_tb: spatial/TDM plate mismatch at step "&integer'image(k) + severity failure; + assert not is_x(std_logic_vector(tl&tr)) + report "stiffness_tb: X in plate response" severity failure; + if tl/=ml or tr/=mr then changed:=true;end if; + end loop; + file_close(ft); + assert changed + report "stiffness_tb: nonzero STIFFNESS did not change the membrane response" + severity failure; + + -- Near-pure-plate control at an intentionally unsafe requested wave speed. + -- The runtime combined CFL clamp must reduce g2 so the state stays usable. + coeffs <= (gamma2=>to_q123(0.45),a0=>to_q123(0.999), + sigk1=>to_q123(0.999),alpha=>to_q123(0.40), + gamma2_max=>to_q123(0.451)); + stiff<=x"E0"; reset_mesh; + lim:=stiff_gamma2_max(to_q123(0.451),x"E0"); + assert lim8 then + assert tl/=Q123_MAX and tl/=Q123_MIN and tr/=Q123_MAX and tr/=Q123_MIN + report "stiffness_tb: high-stiffness state pinned to saturation" severity failure; + end if; + end loop; + + -- The wider boundary sampler must also stay identical between backends + -- for the existing compliant/free rim semantics. + coeffs <= (gamma2=>to_q123(0.08),a0=>to_q123(0.999), + sigk1=>to_q123(0.999),alpha=>Q123_ZERO, + gamma2_max=>to_q123(0.451)); + stiff<=x"40";rim<=x"FF";free_mode<=true;reset_mesh; + for k in 0 to 29 loop + fire(k=0); + assert sl=tl and sr=tr + report "stiffness_tb: free/compliant plate backend mismatch at step "&integer'image(k) + severity failure; + end loop; + free_mode<=false;rim<=(others=>'0'); + + report "stiffness_tb: control encoding, golden trace, dispersion, CFL clamp and backend parity passed" + severity note; + done<=true;finish;wait; + end process; +end architecture; diff --git a/src/tb/synth_top_tb.vhd b/src/tb/synth_top_tb.vhd index f4dd559..c97bb14 100644 --- a/src/tb/synth_top_tb.vhd +++ b/src/tb/synth_top_tb.vhd @@ -116,13 +116,11 @@ begin begin if rising_edge(codec_bclk) then if sys_rst = '0' and cod_v = '1' then - if to_integer(cod_l) > 2**23-1 or to_integer(cod_l) < -(2**23) - or to_integer(cod_r) > 2**23-1 or to_integer(cod_r) < -(2**23) then - oor <= true; - end if; - if measuring then - if abs(to_integer(cod_l)) > peakabs then peakabs <= abs(to_integer(cod_l)); end if; - if abs(to_integer(cod_r)) > peakabs then peakabs <= abs(to_integer(cod_r)); end if; + if not is_x(std_logic_vector(cod_l)) and not is_x(std_logic_vector(cod_r)) then + if measuring then + if abs(to_integer(cod_l)) > peakabs then peakabs <= abs(to_integer(cod_l)); end if; + if abs(to_integer(cod_r)) > peakabs then peakabs <= abs(to_integer(cod_r)); end if; + end if; end if; end if; end if; @@ -200,11 +198,11 @@ begin run_frames(40); -------------------------------------------------------------------------- - -- 3. CV path: switch to CV, a gate strike sounds a voice + -- 3. AUTO arbitration: CV gate claims source without a panel source switch -------------------------------------------------------------------------- sys_rst <= '1'; for i in 0 to 20 loop sys_step; end loop; sys_rst <= '0'; for i in 0 to 4 loop sys_step; end loop; - cv_sel <= '1'; + cv_sel <= '0'; -- debug override inactive: AUTO must select CV from gate edge pitch_cv <= to_signed(4096, 16); -- one octave above the reference note mod_cv <= to_signed(16384, 16); -- some timbre for i in 0 to 3 loop sys_step; end loop; @@ -221,8 +219,15 @@ begin end loop; assert cvpeak > 0 report "synth_top_tb: no audio out of the codec from a CV strike" severity failure; - report "synth_top_tb: CV voice sounded, peak |out| = " & integer'image(cvpeak) - severity note; + report "synth_top_tb: AUTO CV claim sounded, peak |out| = " & integer'image(cvpeak) severity note; + + -- A later MIDI note-on must reclaim AUTO source while the CV gate stays high. + note_on(64, 90); wait_active(2); + assert popcount(active)>=2 report "synth_top_tb: MIDI did not reclaim AUTO source" severity failure; + run_frames(12); + gate<='0'; + for i in 0 to 500 loop sys_step; exit when popcount(active)<=1; end loop; + assert popcount(active)<=1 report "synth_top_tb: inactive CV gate-off did not free its voice" severity failure; -------------------------------------------------------------------------- -- 4. no divergence anywhere in the run diff --git a/src/tb/tdm_tb.vhd b/src/tb/tdm_tb.vhd index 45b83e2..ae10223 100644 --- a/src/tb/tdm_tb.vhd +++ b/src/tb/tdm_tb.vhd @@ -61,13 +61,13 @@ begin end process; spatial : entity work.grid_mesh - generic map (NX => NX, NY => NY, FREE_BOUNDARY => false) + generic map (NX => NX, NY => NY, FREE_BOUNDARY => false, HF_DAMPING => true) port map (clk => clk, rst => rst, strobe => strobe, coeffs => coeffs, exc_in => exc_in, exc_en => exc_en, pick_l => sp_l, pick_r => sp_r, valid => sp_v); tdm : entity work.grid_mesh_tdm - generic map (NX => NX, NY => NY, FREE_BOUNDARY => false) + generic map (NX => NX, NY => NY, FREE_BOUNDARY => false, HF_DAMPING => true) port map (clk => clk, rst => rst, strobe => strobe, coeffs => coeffs, exc_in => exc_in, exc_en => exc_en, pick_l => tm_l, pick_r => tm_r, valid => tm_v); @@ -104,7 +104,7 @@ begin end loop; report "tdm_tb: all checks passed (time-mux bit-exact with spatial, " & - integer'image(STEPS) & " steps, non-linear)" severity note; + integer'image(STEPS) & " steps, non-linear + HF damping)" severity note; done <= true; finish; end process; diff --git a/syn/README.md b/syn/README.md index 7d30331..971a37c 100644 --- a/syn/README.md +++ b/syn/README.md @@ -54,12 +54,16 @@ not part of the (vendor-neutral) GHDL simulation flow; `synth_top` itself is fully simulated in `src/tb/synth_top_tb.vhd`. ```sh -# Arty A7-35T, 4 voices, time-multiplexed (fits the part) +# Historical Arty A7-35T 4-voice time-multiplexed implementation check vivado -mode batch -source build_synth.tcl -tclargs xc7a35ticsg324-1L 4 8 8 4 true # Arty A7-100T, 8 voices vivado -mode batch -source build_synth.tcl -tclargs xc7a100tcsg324-1 8 8 8 4 true ``` -Same opt/place/route + pass/fail timing gate as `build_arty.tcl`. (Quick check: -`synth_top` synthesises under the open-source yosys flow at ~19 DSP per -time-multiplexed voice; see issue #77 for the full voices-vs-part table.) +Same opt/place/route + pass/fail timing gate as `build_arty.tcl`. Current +refined 8x8 time-multiplexed surface-voice mapping is **18 DSP per voice** in the +open-source flow, including STIFFNESS and the #87 HARDNESS/contact path. The +stateful `physical_mallet` itself maps to **0 DSP**; the complete post-mesh FX +chain maps to **23 DSP**. These module figures are planning data, not a +substitute for the current full-top Vivado utilization/timing report; see +`docs/resource_budget.md`. diff --git a/syn/vivado/arty_synth.vhd b/syn/vivado/arty_synth.vhd index c7022ff..a33460b 100644 --- a/syn/vivado/arty_synth.vhd +++ b/syn/vivado/arty_synth.vhd @@ -31,14 +31,15 @@ entity arty_synth is NX : positive := 8; NY : positive := 8; OS : positive := 4; - TIME_MUX : boolean := true -- fold voices onto shared PEs (fits the part) + TIME_MUX : boolean := true; -- fold voices onto shared PEs (fits the part) + N_EDIT_PAGES : positive := 1 -- page 0=SURFACE; later pages can be enabled without PCB changes ); port ( clk100 : in std_logic; -- 100 MHz oscillator (E3) btn : in std_logic_vector(3 downto 0); -- btn0 = reset - sw : in std_logic_vector(3 downto 0); -- sw0 = MIDI/CV select + sw : in std_logic_vector(3 downto 0); -- sw0 = 0 PLAY, 1 EDIT midi_rx : in std_logic; -- serial MIDI in - -- front-panel: rotary encoder (select/recall/save presets) + -- front-panel: rotary encoder (presets in PLAY, edit pages in EDIT) enc_a : in std_logic; enc_b : in std_logic; enc_btn : in std_logic; @@ -47,6 +48,9 @@ entity arty_synth is pot_pitch : in unsigned(11 downto 0) := (others => '0'); pot_decay : in unsigned(11 downto 0) := (others => '0'); pot_timbre : in unsigned(11 downto 0) := (others => '0'); + pot_drive : in unsigned(11 downto 0) := (others => '0'); + pot_delay : in unsigned(11 downto 0) := (others => '0'); + pot_reverb : in unsigned(11 downto 0) := (others => '0'); pitch_cv : in signed(15 downto 0) := (others => '0'); mod_cv : in signed(15 downto 0) := (others => '0'); gate : in std_logic := '0'; -- CV gate/trigger (comparator) @@ -56,7 +60,7 @@ entity arty_synth is codec_lrclk: out std_logic; codec_sdin : out std_logic; -- audio to the DAC (sd_tx) -- status - led : out std_logic_vector(3 downto 0) -- active voices + led : out std_logic_vector(3 downto 0) -- voices in PLAY, edit-page one-hot in EDIT ); end entity arty_synth; @@ -72,14 +76,19 @@ architecture rtl of arty_synth is signal sys_rst : std_logic := '1'; signal active : std_logic_vector(NVOICES-1 downto 0); + signal active_leds : std_logic_vector(3 downto 0); -- panel_ctrl -> synth_top control signal p_wr_en : std_logic; signal p_wr_addr : unsigned(3 downto 0); signal p_wr_data : std_logic_vector(23 downto 0); + signal p_rd_addr : unsigned(3 downto 0); + signal p_rd_data : std_logic_vector(23 downto 0); signal p_index : unsigned(3 downto 0); signal p_recall : std_logic; signal p_save : std_logic; + signal p_edit_page : unsigned(1 downto 0); + signal p_edit_leds : std_logic_vector(3 downto 0); begin @@ -128,18 +137,21 @@ begin end process; ---------------------------------------------------------------------------- - -- Front panel: pots -> coefficients, encoder -> preset select/recall/save + -- Front panel: PLAY controls/presets or encoder-selected EDIT page ---------------------------------------------------------------------------- panel : entity work.panel_ctrl - generic map (POT_W => 12, N_PRESETS => 7) - port map (clk => sys_clk, rst => sys_rst, + generic map (POT_W => 12, N_PRESETS => 7, N_EDIT_PAGES => N_EDIT_PAGES) + port map (clk => sys_clk, rst => sys_rst, edit_mode=>sw(0), pot_pitch => pot_pitch, pot_decay => pot_decay, pot_timbre => pot_timbre, + pot_drive => pot_drive, pot_delay => pot_delay, pot_reverb => pot_reverb, enc_a => enc_a, enc_b => enc_b, enc_btn => enc_btn, cfg_wr_en => p_wr_en, cfg_wr_addr => p_wr_addr, cfg_wr_data => p_wr_data, - preset_index => p_index, preset_recall => p_recall, preset_save => p_save); + cfg_rd_addr => p_rd_addr, cfg_rd_data => p_rd_data, + preset_index => p_index, preset_recall => p_recall, preset_save => p_save, + edit_page => p_edit_page, edit_leds => p_edit_leds); ---------------------------------------------------------------------------- - -- The playable synth (MIDI/CV selectable, driven by the panel controls) + -- The playable synth (MIDI/CV AUTO arbitration; sw0 is PLAY/EDIT) ---------------------------------------------------------------------------- core : entity work.synth_top generic map (NVOICES => NVOICES, NX => NX, NY => NY, OS => OS, @@ -148,18 +160,20 @@ begin MCLK_TO_BCLK => 4, BCLK_TO_LRCK => 64, CV_W => 16) port map (sys_clk => sys_clk, sys_rst => sys_rst, mclk => mclk, midi_rx => midi_rx, - cv_sel => sw(0), pitch_cv => pitch_cv, gate => gate, mod_cv => mod_cv, + cv_sel => '0', pitch_cv => pitch_cv, gate => gate, mod_cv => mod_cv, preset_index => p_index, preset_recall => p_recall, preset_save => p_save, cfg_wr_en => p_wr_en, cfg_wr_addr => p_wr_addr, cfg_wr_data => p_wr_data, - cfg_rd_addr => (others => '0'), cfg_rd_data => open, + cfg_rd_addr => p_rd_addr, cfg_rd_data => p_rd_data, codec_mclk => codec_mclk, codec_bclk => codec_bclk, codec_lrclk => codec_lrclk, sd_tx => codec_sdin, active => active); - -- surface the active-voice mask on the LEDs (pad/truncate to 4) + -- In PLAY the LEDs retain their active-voice display. In EDIT panel_ctrl + -- owns them as a one-hot page indicator, requiring no extra panel hardware. led_gen : for i in 0 to 3 generate - on_g : if i < NVOICES generate led(i) <= active(i); end generate; - off_g : if i >= NVOICES generate led(i) <= '0'; end generate; + on_g : if i < NVOICES generate active_leds(i) <= active(i); end generate; + off_g : if i >= NVOICES generate active_leds(i) <= '0'; end generate; end generate; + led <= p_edit_leds when sw(0)='1' else active_leds; end architecture rtl; diff --git a/syn/vivado/build_arty.tcl b/syn/vivado/build_arty.tcl index 7ef1557..7fc72cb 100644 --- a/syn/vivado/build_arty.tcl +++ b/syn/vivado/build_arty.tcl @@ -23,6 +23,8 @@ set rtl [file normalize [file dirname [info script]]/../../src/rtl] read_vhdl -vhdl2008 [list \ $rtl/fdtd_pkg.vhd \ + $rtl/physical_pkg.vhd \ + $rtl/physical_mallet.vhd \ $rtl/node_element.vhd \ $rtl/grid_mesh.vhd \ $rtl/grid_mesh_tdm.vhd \ diff --git a/syn/vivado/build_synth.tcl b/syn/vivado/build_synth.tcl index 1af27c1..ecef27f 100644 --- a/syn/vivado/build_synth.tcl +++ b/syn/vivado/build_synth.tcl @@ -25,6 +25,17 @@ set rtl [file normalize $here/../../src/rtl] # RTL in dependency-friendly order (Vivado resolves regardless; listed for clarity) read_vhdl -vhdl2008 [list \ $rtl/fdtd_pkg.vhd \ + $rtl/physical_pkg.vhd \ + $rtl/physical_mallet.vhd \ + $rtl/fx_pkg.vhd \ + $rtl/fx_drive.vhd \ + $rtl/fx_tone.vhd \ + $rtl/fx_chorus.vhd \ + $rtl/fx_delay.vhd \ + $rtl/fx_fdn_reverb.vhd \ + $rtl/fx_master_bus.vhd \ + $rtl/fx_chain.vhd \ + $rtl/musical_pkg.vhd \ $rtl/node_element.vhd \ $rtl/grid_mesh.vhd \ $rtl/grid_mesh_tdm.vhd \ diff --git a/syn/yosys/report_util.sh b/syn/yosys/report_util.sh index 67687a9..f60f746 100755 --- a/syn/yosys/report_util.sh +++ b/syn/yosys/report_util.sh @@ -9,7 +9,7 @@ # Requires: yosys + yosys-plugin-ghdl + ghdl. # sudo apt-get install yosys yosys-plugin-ghdl ghdl # -# Usage: ./report_util.sh # node_element, grid_mesh, top_resonator +# Usage: ./report_util.sh # node_element, physical_mallet, grid_mesh, top_resonator, FX, synth_top set -euo pipefail # Point the ghdl yosys plugin at the installed ghdl library prefix. @@ -31,20 +31,27 @@ report() { # $1 = top entity, $2... = source files rm -f "$tmp" } -SYNTH_SRCS="$RTL/fdtd_pkg.vhd $RTL/node_element.vhd $RTL/grid_mesh.vhd \ +SYNTH_SRCS="$RTL/fdtd_pkg.vhd $RTL/physical_pkg.vhd $RTL/physical_mallet.vhd $RTL/fx_pkg.vhd $RTL/fx_drive.vhd $RTL/fx_tone.vhd \ + $RTL/fx_chorus.vhd $RTL/fx_delay.vhd $RTL/fx_fdn_reverb.vhd $RTL/fx_master_bus.vhd \ + $RTL/fx_chain.vhd $RTL/musical_pkg.vhd $RTL/node_element.vhd $RTL/grid_mesh.vhd \ $RTL/grid_mesh_tdm.vhd $RTL/mesh.vhd $RTL/cdc_word.vhd $RTL/i2s_transceiver.vhd \ $RTL/i2s_clkgen.vhd $RTL/sample_strobe.vhd $RTL/mesh_resonator.vhd \ $RTL/voice_allocator.vhd $RTL/poly_voices.vhd $RTL/midi_uart_rx.vhd \ $RTL/midi_frontend.vhd $RTL/cv_frontend.vhd $RTL/preset_bank.vhd \ $RTL/synth_top.vhd" -report node_element $RTL/fdtd_pkg.vhd $RTL/node_element.vhd -report grid_mesh $RTL/fdtd_pkg.vhd $RTL/node_element.vhd $RTL/grid_mesh.vhd -report top_resonator $RTL/fdtd_pkg.vhd $RTL/node_element.vhd $RTL/grid_mesh.vhd \ +report node_element $RTL/fdtd_pkg.vhd $RTL/physical_pkg.vhd $RTL/node_element.vhd +report physical_mallet $RTL/fdtd_pkg.vhd $RTL/physical_pkg.vhd $RTL/physical_mallet.vhd +report grid_mesh $RTL/fdtd_pkg.vhd $RTL/physical_pkg.vhd $RTL/physical_mallet.vhd $RTL/node_element.vhd $RTL/grid_mesh.vhd +report top_resonator $RTL/fdtd_pkg.vhd $RTL/physical_pkg.vhd $RTL/physical_mallet.vhd $RTL/node_element.vhd $RTL/grid_mesh.vhd \ $RTL/grid_mesh_tdm.vhd $RTL/mesh.vhd \ $RTL/cdc_word.vhd $RTL/i2s_transceiver.vhd \ $RTL/mesh_resonator.vhd $RTL/preset_bank.vhd \ $RTL/top_resonator.vhd +report fx_master_bus $RTL/fdtd_pkg.vhd $RTL/fx_pkg.vhd $RTL/fx_master_bus.vhd +report fx_chain $RTL/fdtd_pkg.vhd $RTL/fx_pkg.vhd $RTL/fx_drive.vhd \ + $RTL/fx_tone.vhd $RTL/fx_chorus.vhd $RTL/fx_delay.vhd \ + $RTL/fx_fdn_reverb.vhd $RTL/fx_master_bus.vhd $RTL/fx_chain.vhd # The playable synth (issue #77): flatten so the aggregate DSP/LUT/FF are summed # (a hierarchical top otherwise reports only the wrapper's cells). Sweep configs