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| 1 | +/* |
| 2 | + * Copyright (c) 2025 Arm Limited. |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: MIT |
| 5 | + * |
| 6 | + * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | + * of this software and associated documentation files (the "Software"), to |
| 8 | + * deal in the Software without restriction, including without limitation the |
| 9 | + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | + * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | + * furnished to do so, subject to the following conditions: |
| 12 | + * |
| 13 | + * The above copyright notice and this permission notice shall be included in all |
| 14 | + * copies or substantial portions of the Software. |
| 15 | + * |
| 16 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | + * SOFTWARE. |
| 23 | + */ |
| 24 | +#pragma once |
| 25 | + |
| 26 | +#ifdef ARM_COMPUTE_ENABLE_SME |
| 27 | + |
| 28 | + |
| 29 | +#include "../std_transforms_sme.hpp" |
| 30 | + |
| 31 | +namespace arm_gemm |
| 32 | +{ |
| 33 | + |
| 34 | +// Implementations |
| 35 | +void sme_interleaved_nomerge_fp32_mopa_1VLx4VL(const float *const A, const float *const B, float *const C, int ldc, const int M, const int N, const int K, const float *const bias, const Activation act, bool accumulate, float *const accumulator_buffer); |
| 36 | + |
| 37 | +class cls_sme_interleaved_nomerge_fp32_mopa_1VLx4VL |
| 38 | +{ |
| 39 | +public: |
| 40 | + typedef float lhs_operand_type; |
| 41 | + typedef float rhs_operand_type; |
| 42 | + typedef float result_type; |
| 43 | + |
| 44 | + typedef void (*kern_type)(const float *const A, const float *const B, float *const C, int ldc, const int M, const int N, const int K, const float *const bias, const Activation act, bool accumulate, float *const accumulator_buffer); |
| 45 | + |
| 46 | + /* Kernel blocking parameters */ |
| 47 | + static unsigned int out_height() |
| 48 | + { |
| 49 | + return sme::get_vector_length<float>() * 1; |
| 50 | + } |
| 51 | + |
| 52 | + static unsigned int out_width() |
| 53 | + { |
| 54 | + return sme::get_vector_length<float>() * 4; |
| 55 | + } |
| 56 | + |
| 57 | + static constexpr unsigned int k_unroll() |
| 58 | + { |
| 59 | + return 1; |
| 60 | + } |
| 61 | + |
| 62 | + static constexpr bool supports_bias() |
| 63 | + { |
| 64 | + return true; |
| 65 | + } |
| 66 | + |
| 67 | + static constexpr bool is_sme() |
| 68 | + { |
| 69 | + return true; |
| 70 | + } |
| 71 | + |
| 72 | + // Default to the generic kernel |
| 73 | + kern_type kernel = sme_interleaved_nomerge_fp32_mopa_1VLx4VL; |
| 74 | + |
| 75 | + StdTransformsSME<lhs_operand_type, result_type, 1, 4, 1> transforms = {}; |
| 76 | + |
| 77 | + cls_sme_interleaved_nomerge_fp32_mopa_1VLx4VL(const CPUInfo *) |
| 78 | + { |
| 79 | + } |
| 80 | +}; |
| 81 | + |
| 82 | +} // namespace arm_gemm |
| 83 | + |
| 84 | +#endif // ARM_COMPUTE_ENABLE_SME2 |
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